GB2089155A - Detecting pulses which do not have a predetermined spacing - Google Patents

Abstract

Detector apparatus for pulses which do not precede or succeed another pulse by a predetermined time comprises first and second delay devices (5 and 38) the second (38) of which is fed from an input terminal (1) via a detector circuit (3) which transmits an input pulse only if this pulse does not coincide with a preceding input pulse delayed in the first delay device (5). If a pulse is transmitted by the detector circuit it is delayed in the second delay device and applied to a blocking circuit (29) which only transmits it to an output terminal (2) if the pulse, thus delayed, does not coincide with another input pulse. If a monostable circuit (7) is absent the delays produced by the two delay devices are chosen equal to each other. The apparatus may be modified to respond to a range of pulse spacings by including the monostable circuit (7), the astable period of which is chosen to be equal to the difference between the two ends of this range, and making the delay produced by the second delay device greater by this difference than the delay produced by the first delay device. The signal at input terminal 1 may be delayed in a further delay device (102) by an amount equal to the delay produced by the second delay device (38) and applied to an AND gate (101) the other input of which is fed with the inverted signal at the output terminal (2), to form a pulse repetition interval filter. (Figure 1). <IMAGE>

Description

SPECIFICATION Signal event detection apparatus The invention relates to signal event detection apparatus.

It is sometimes useful to be able to detect those events in a signal which repeat at substantially equal intervals which are of a given size. Known arrangements for achieving this, used for example as pulse repetition interval filters, commonly comprise a delay line correlator which consists of a delay line and an AND gate, an input terminal being connected to one input of the AND gate directly and to the other input of the AND gate via the delay line. The delay produced by the delay line is equal to the pulse repetition interval to which the arrangement is required to correspond, so that when an input pulse follows another at this interval it coincides with the delayed first pulse at the AND gate, resulting in an output pulse from the AND gate. Such an arrangement is described, for example, in the article by B. J.

Brown entitled "Pulse repetition frequency discrimi natorwith complete harmonic suppression" in "IEEE Transactions on Aerospace and Electronic Sys tems",January 1973, pages 112 and 113. In the configuration shown in Figures 2 and 3 of this article the AND gate is inhibited by input pulses which have been delayed by amounts different to, but having a predetermined relationship to, the delay occurring in the signal path to the AND gate via the delay line, in order to suppress harmonics.

It is sometimes a disadvantage with these known arrangements that the first pulse of a pulse train to which the filter is tuned is not transmitted to the output. It is an object of the present invention to enable this disadvantage to be overcome.

According to one aspect the invention provides apparatus for detecting those events in an input signal which neither precede another such event by a predetermined time nor succeed another such event by said predetermined time, said apparatus comprising first delay means for delaying signals by at least said predetermined time, a coupling from the apparatus input to the input of said first delay means, a detector circuit to a first input of which the apparatus input is coupled and to a second input of which the output of said first delay means is coupled in such manner that the delay occurring in the signal path from the apparatus input to said second input will be greater by said predetermined amount than any delay occurring in the signal path from the apparatus input to said first input, said detector circuit being constructed to respond to the application of a signal to its first input which arises from the occurrence of a said event at the apparatus input by generating an output signal if and only if the signal at its first input does not coincide with the presence at its second input of a signal which arises from the previous occurrence of a said event at the apparatus input, second delay means, a coupling from the output of said detector circuit to the input of said second delay means, a coupling from the output of said second delay means to the apparatus output, and a signal transfer blocking circuit to a control input of which the apparatus input is coupled, said blocking circuit being constructed to block the transfer to the apparatus output of a said output signal by the second delay means if and only if the said output signal, after delay in said second delay means by a given amount, coincides with the presence at said control input of a signal arising from the occurrence of a said event at the apparatus input, said given amount, when added to any delay occurring in the signal path from the apparatus input to the detector output via said first input, being greater by said predetermined time than any delay occurring in the signal path from the apparatus input to said control input.

It has now been recognised that such a combination of first and second delay means, detector circuit and signal transfer blocking circuit will, when fed with an input signal comprising events, for example pulses, spaced in time, produce an output signal in response to only those events which neither precede nor succeed another such event by the predetermined time. Such an apparatus may be used, for example, as a pulse repetition interval stop filter (the output signal of which will be delayed with respect to the input signal by at least the said predetermined time).As an alternative a detector arrangement for detecting those events in an input signal which repeat at substantially equal intervals which are of a given size can be formed by means of a gate circuit, such an apparatus coupling the arrangement input to a control input of said gate circuit in such manner that the production of an output signal by the apparatus will block transmission through said gate circuit, and third delay means coupling the arrangement input to a second input of said gate circuit, said third delay means being constructed to delay signals passing through it by an amount equal to the delay occurring in the signal path from the arrangement input to the control input of said gate circuit via the first input of the detector circuit and the second delay means.Such an arrangement may be used, for example, as a pulse repetition pass filter which, in contradistinction to the known pulse repetition filters referred to above, will pass even the first pulse of a pulse train to which it is tuned, albeit at the expense of producing a delay between input signal and output signal, this delay being at least equal to the said predetermined time.

According to another aspect the invention provides apparatus for detecting those events in an input signal which neither precede another such event by a time which lies between predetermined minimum and maximum values nor succeed another such event by a time which lies between said predetermined minimum and maximum values, said apparatus comprising first delay means for delaying signals by a time at least equal to said predetermined minimum value, a coupling from the apparatus input to the input of said first delay means, a detector circuit to a first input of which the apparatus input is coupled and to a second input of which the output of said first delay means is coupled in such manner that the delay occurring in the signal path from the apparatus input to said second input will be greater by said predetermined minimum value than any delay occurring in the signal path from the apparatus input to said first input, said detector circuit being constructed to respond to the application of a signal to its first input which arises from the occurrence of a said event at the apparatus input by generating an output signal if and only if the signal at its first input does not coincide with the presence at its second input of a signal which arises from the previous occurrence of a said event at the apparatus input, a monostable circuit the astable period of which is equal to the difference between said maximum and minimum values, which monostable circuit is included in the signal path from the apparatus input to the second input of said detector circuit but not in the signal path from the apparatus input to the first input of the detector circuit, second delay means, a coupling from the output of said detector circuit to the input of said second delay means, a coupling from the output of said second delay means to the apparatus output, and a signal transfer blocking circuit to a control input of which the apparatus input is coupled via a monostable circuit the astable period of which is equal to the difference between said maximum and minimum values, said blocking circuit being constructed to block the transfer to the apparatus output of a said output signal by the second delay means if and only if the said output signal, after delay in said second delay means by a given amount coincides with the presence at said control input of a signal arising from the occurrence of a said event at the apparatus input, said given amount, when added to any delay occurring in the signal path from the apparatus input to the detector output via said first input, being greater by a time equal to said predetermined maximum value than any delay occurrence in the signal path from the apparatus input to said control input.

Such an apparatus may again be used, for example, as a pulse repetition interval stop filter, or as part of a pulse repetition interval pass filter. It can sometimes be an advantage with such filters that they are effectively tuned to a range of values of pulse repetition interval rather than narrowly to a specific value thereof. In the interests of economy of components the monostable circuit included in the coupling from the apparatus input to said control input may be constituted by the monostable circuit which is included in the signal path from the apparatus input to the second input of the detector circuit.

In order to make use of digital techniques said first delay means may comprise a first read/write memory, an address signal generator a first output of which is coupled to an address signal input of said first read/write memory, said address signal generator being constructed to generate at said first output a continuous sequence of addresses which comprises first and second interleaved cyclically repeating subsequences where the second cyclically repeating subsequence is identical to the first cyclically repeating subsequence but is cyclically displaced relative thereto, each member of said first subsequence being different from all other members thereof, and means for applying a write signal to said first read/write memory in conjunction with the application to said first read/write memory of the members of one of said repeating subsequences and for applying a read signal to said first read/write memory in conjunction with the application thereto of the members of the other of said repeating subsequences, a data signal input of said first read/write memory constituting the input of said first delay means and a data signal output of said first read/write memory constituting the output of said first delay means, and said second delay means, said detector circuit and said blocking circuit may together comprise a second read/write memory to an address signal input of which a second output of said address signal generator is coupled, said address signal generator being constructed to generate at its second output successive members of a first cyclically repeating sequence of addresses in synchronism with the generation at its first output of the successive members of one of said repeating subsequences, each member of said first cyclically repeating sequence being different from all other members thereof, to generate at its second output, when a signal at a control input thereof has a first value, successive members of a second cyclically repeating sequence of addresses in synchronism with the generation at its first output of the successive members of the other of said repeating subsequences, said second cyclically repeating sequence being identical to said first cyclically repeating sequence but being cyclically displaced relative thereto, and to cyclically displace said second cyclically repeating sequence for as long as the signal at its control input has a second value, means for applying a read signal to said second read/write memory in conjunction with the application to said second read/write memory of the members of said first cyclically repeating sequence of addresses and for applying, each time a said event occurs at the apparatus input, a write signal to said second read/write memory in conjunction with the application to said second read/write memory of a member of said second cyclically repeating sequence of addresses or of a member of the cyclically displaced version thereof, and a coupling circuit coupling the apparatus input and the output of said first delay means or of the cascade combination of said first delay means and the monostable circuit firstmentioned above (if present) to a data signal input of said second read/write memory and to the control input of the address signal generator, said coupling circuit being constructed to apply, each time a said event occurs at the apparatus input, a signal having one of said first and second values to the control input of the address signal generator if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the monostable circuitfirst-mentioned above (if present), a signal having the other of said first and second values to the control input of the address signal generator if a signal which arises from the previous occurrence of a said event at the apparatus input is not present at the output of the first delay means or of the cascade combination of said first delay means and the monostable circuit first-mentioned above (if present), a signal having a first value to the data signal input of the second read/write memory if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the monostable circuitfirst-mentioned above (if present), and a signal having a second value to the data signal input of the second read/write memory if a signal which arises from the previous occurrence of a said event at the apparatus input is not present at the output of the first delay means or of the cascade combination of said first delay means and the monostable circuit first-mentioned above (if present), a data signal output of said second read/write memory being coupled to the apparatus output. Such a construction can enable the apparatus to be programmable, i.e. can enable the aforesaid predetermined time, or predetermined minimum and maximum values, to be changed.

In the interests of simplicity, each member of the cyclically displaced version of said second cyclically repeating sequence of addresses is preferably identical to the member of said first cyclically repeating sequence of addresses which immediately precedes or succeeds it at the address signal input of the second read/write memory.If this is so then the address signal generator may comprise a cyclic counter, a clock signal generator having an output coupled to a clock signal input of said cyclic counter, first and second controllable digital adder or subtractor circuits each having an input to which the output of said cyclic counter is coupled and being controllable between first and second states in the first of which it generates at its output a digital number equal to any digital number present at its input and in the second of which it generates at its output a digital number equal to any digital number present at its input plus or minus a given digital number and with any resulting carry digit ignored, a coupling from an output of said clock signal generatorto a control input of said first adder or subtractor circuit so that said first adder or subtractor circuit will be controlled to its first state and to its second state for each count in said counter, and couplings from an output of said clock signal generator and from the control input of said address signal generator to a control input of said second adder or subtractor circuit in such manner that said second adder or subtractor circuit will be controlled to its first state and to its second state for a given count in said counter each time a said event occurs at the apparatus input if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the monostable circuit first-mentioned above (if present), and will be controlled solely to a given one of its states otherwise, the outputs of the first and second adder or subtractor circuits constituting the first and second outputs respectively of the address signal generator. Such a construction can generate the required address signals in a very economical manner.

It should be noted that copending Patent Application 80 (PHB 32736) of even date describes and claims a signal delay device comprising a read/write memory, a coupling from the device input to a data signal input of said memory, a coupling from a data signal output of said memory to the device output, a cyclic digital counter, a clock signal generator having an output coupled to a clock signal input of said counter, a coupling from a count signal output of said counter to an address signal input of said memory, and a coupling from an output of said clock signal generator to a read/write control input of said memory, characterised in that the coupling from the count signal output of said counter to an address signal input of said memory includes a controllable digital adder or subtractor circuit to which a staticdigital-number generator is coupled, said controllable digital adder or subtractor circuit being controllable between first and second states in the first of which it generates at its output a digital number equal to any digital number present at its input plus or minus a given first digital number and with any resulting carry or borrow digit ignored, and in the second of which it generates at its output a digital number equal to any digital number present at its input plus or minus a given second digital number and with any resulting carry or borrow digit ignored, said given second digital number being determined by the output of said static-digital-number generator, and a coupling from an output of said clock signal generator to a control input of said controllable digital adder or subtractor circuit so that said controllable digital adder or subtractor circuit will be controlled to its first state and to its second state each time the signal at the address signal input of the memory is stationary and a read operation will take place in said memory each time the controllable digital adder or subtractor circuit is in one of said states and a write operation will take place in said memory each time the controllable digital adder or subtractor circuit is in the other of said states.In such a device the address signal input of the memory is fed with a continuous sequence of addresses which comprises first and second interleaved cyclically repeating subsequences where the second cyclically repeating subsequence is identical to the first cyclically repeating subsequence but is cyclically displaced relative thereto.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which Figure 7 shows a first embodiment, Figure 2 shows a second embodiment, Figure 3 shows a possible construction for part of the embodiment of Figure 2, and Figure 4 shows an alternative construction to that shown in Figure 3.

The part of Figure 1 in full lines (with block 7 replaced by a direct connection) is a diagram of apparatus for detecting those events in an input signal applied to an input terminal 1 which neither precede another such event by a predetermined time nor succeed another such event by said predetermined time. It is assumed that the input signal is in the form of a succession of short pulses, each pulse constituting a said event, and the apparatus is constructed to generate a (delayed) pulse at an output terminal 2 in response to each input pulse, provided that that input pulse neither precedes nor succeeds another such pulse by a predetermined time.

The input terminal 1 is coupled to the input 6 of a first delay line 5 which produces a delay T1 equal to said predetermined time, and to one input of an AND gate 3. The output 4 of delay line 5 is coupled to the other input of the AND gate 3 via an inverter 100. The output of AND gate 3 is coupled to the input 37 of a second delay line 38 which also produces a delay T1 equal to said predetermined time. The output 32 of delay line 38 is coupled to one input of a second AND gate 29 the other input of which is fed from input terminal 1 via a second inverter 35. The output of AND gate 29 is coupled to the output terminal 2.

The apparatus of Figure 1 shown in full lines operates as follows. Each time a (logic "1") pulse occurs at input terminal 1 it inhibits AND gate 3 via inverter 100 after a time equal to the delay T1 produced by delay line 5. Thus an input pulse at terminal 1 is only transmitted by AND gate or detector circuit 3 if it does not succeed another such pulse by a time equal to the delay T1 produced by delay 5. If it is transmitted by AND gate 3 it appears at the output of delay line 38 after a delay equal to the delay T1 produced by delay line 38 and is applied to AND gate or signal transfer blocking circuit 29.

Each input pulse at terminal 1 also inhibits AND gate 29 via an inverter 35 and thus, if an input pulse is transmitted by gate 3, it only results in an output pulse at terminal 2 if it does not precede another such pulse at terminal 1 by a time T1. Thus input pulses at input terminal 1 give rise to corresponding pulses at output terminal 2 (after a delay T) if and only if these input pulses neither precede nor succeed another such input pulse by a time T1.

The apparatus of Figure 1 shown in full lines may form part of a detector arrangement for detecting those events in an input signal which repeat at substantially equal intervals (T1). Thus, for example, a further AND gate 101 may be provided, one input of which is fed from input terminal 1 via a third delay line 102 which produces a delay (T1) equal to the delay produced by delay line 38 and the other input of which is fed from output terminal 2 via a further inverter 103. If this is done, each input pulse at terminal 1 appears at the output of delay line 102 after a delay T1. If this input pulse should be transmitted by gate 3, delay line 38 and gate 29 it also appears at output terminal 2 after a delay T1 and inhibits gate 101 at that time.Thus an input pulse at terminal 1 only gives rise to an output pulse at a terminal 2A (after a time T1) if it does not also give rise to a pulse at terminal 2, i.e. if it precedes and/or succeeds another input pulse by a time T1. Thus if a succession of input pulses occurs at terminal 1 with a period T1 each of these pulses (including the first) will give rise after a delay T1 to an output pulse at terminal 2A. This is in contradistinction to conventional pulse repetition interval filters in which at least the first pulse of such a succession is lost.

The apparatus of Figure 1 shown in full lines may be modified to detect those events in an input signal at terminal 1 which neither precede another such event by a time which lies between predetermined minimum (T1) and maximum (T1 + T2) values nor succeed another such event by a time which lies between these predetermined minimum and maximum values by including a monostable circuit 7 in the signal path from the input terminal 1 to the first delay line 5 and to the inverter 35, and by increasing the delay produced by the second delay line 38 to (T + T2).The astable period of the monostable circuit 7 is equal toT2, and the trigger input 8 of circuit 7 is fed from terminal 1. lfthis is done each input pulse at terminal 1 gives rise to a pulse of length T2 at the output 4 of delay line 5, this pulse starting at a time T1 after the pulse at terminal 1 occurred. Thus a pulse at terminal 1 is now only transmitted by gate 3 if it does not succeed another such pulse after a time lying within the range T1 to (T1 + T2). If it is transmitted by AND gate 3 it now appears at the output of delay line 38 after a delay (T1 + T2) and is applied to AND gate 29.Each input pulse at terminal 1 now also inhibits AND gate 29 via monostable circuit 7 and thus, if an input pulse is transmitted by gate 3, it only results in an output pulse at terminal 2 if it does not proceed another such pulse at terminal 1 by a time lying within the range T1 to (T1 + T2). (If it precedes another such pulse by a time T1 the monostable 7 will be at the end of its astable period when the pulse appears at the output of delay line 38, and if it precedes another such pulse by a time (T1 + T2) the monostable 7 will be at the beginning of its astable period when the pulse appears at the output of delay line 38).

The components 101, 102 and 103 may be added to such a modified apparatus, the delay produced by delay line 102 again being equal to the delay produced by delay line 38, i.e. now being equal to (T1 + T2).

If a delay, T3 say, occurs in the direct signal path from the input terminal 1 to the AND gate 3 the delay produced by delay line 5 will have to be increased by T3 and the delay produced by delay line 38 will have to be decreased by T3. If, alternatively or in addition, a delay, T4 say, occurs in the signal path from input terminal 1 to AND gate 29 via inverter 35 the delay produced by delay line 38 (and by delay line 102 if present) will have to be increased by T4.

The part of Figure 2 shown in full lines (with block 7 replaced by a direct connection) is a diagram of another apparatus for detecting those events in an input signal applied to an input terminal 1 which neither precede another such event by a predetermined time nor succeed another such event by said predetermined time. Components of the apparatus of Figure 2 which have counterparts in Figure 1 have been given corresponding reference numerals. The apparatus of Figure 2 makes use of digital techniques and it is again assumed that the input signal is in the form of a succession of short pulses, these pulses now each having a duration equal to one period of a clock pulse signal produced by a clock pulse generator 14 at an output 104 thereof and being synchronised with this clock pulse signal.

(This can be ensured by providing a circuit 27, possible constructions for which will be described below, in the input signal path to terminal 1, i.e. in the signal path from an auxiliary input terminal 1Ato input terminal 1).

Clock pulse generator 14 forms part of an address signal generator 11 having a control input 105 and first and second outputs 10 and 106 respectively. The outputs 10 and 106 of the generator 11 are connected to the address signal inputs 9 and 30 respectively of read/write memories 5 and 38 respectively which correspond to the first and second delay lines respectively of Figure 1. Each of these memories is capable of storing a single data bit at each address. The data input 6 of memory 5 is fed from input terminal 1 and the data output 4 thereof feeds the inverter 100. The data input 37 of the memory 38 is fed from the AND gate 3 and the data output 32 thereof feeds the output terminal 2. Memories 5 and 38 have "chip enable" inputs 107 and 108 respectively, and "write enable" inputs 109 and 110 respectively.

Address signal generator 11 also includes a cyclic up or down digital counter 12 the clock signal input 13 of which is fed from the output 104 of the clock signal generator 14. The (multiple) count output 15 of counter 12 is connected to one (multiple) input 16 of an adder or subtractor circuit 17 the other (multiple) input 18 of which is fed steadily with a predetermined digital number by a unit 19, for example another read/write memory or a register.

The (multiple) output 20 of the adder or subtractor circuit 17 is connected to a first (multiple) input 21 of a data selector 22 the other (multiple) input 23 of which is fed from the output 15 of the counter 12.

The (multiple) output 24 of the data selector 22 has the same width as the output 15 of the counter 12, so that any carry signal generated in the circuit 17 is ignored at the output 24. The control signal input 25 of data selector 22 is fed from the output 104 of clock signal generator 14.

It will be seen that the components 17, 19 and 22 together with their interconnections effectively constitute a controllable adder or subtractor circuit; when the signal at control input 25 has one value the digital number at the output 15 of counter 12 is fed directly to the output 24 of selector 22, whereas when the signal at control input 25 has its other value the digital number appearing at output 24 is the sum of, or the difference between, the digital numbers then present at the outputs of the counter 12 and the unit 19, with any resulting carry signal ignored. The number at the output 25 (and hence at the first output 10 of generator 11) is used as the address signal for the memory 5. The "write enable" input 109 of memory 5 is fed from the output 104 of clock pulse generator 14 and the "chip enable" input thereof is fed from a second output 111 of clock pulse generator 14.The form of the signals generated by generator 14 at its outputs 104 and 111 is indicated adjacent these outputs; the signal at output 104 may be obtained by frequency-dividing the signal at output 111 by two.

The part of the arrangement of Figure 2 comprising the components of generator 11 so far described together with the components 5, 3 and 100 operates as follows. As previously mentioned it is assumed that each pulse of the signal applied to input terminal 1 is one clock signal period (at output 104 of generator 14) along and is synchronised with this clock signal.

The count in the counter 12, and thus at the input 23 of selector 22, repeatedly cycles through its complete range of values in response to the clock pulses applied to its input 13. Therefore the digital number at the output 20 of adder or subtractor 17, and thus at the input 21 of selector 22, also repeatedly cycles through this complete range, but leads or lags the cycle at the input 23 of selector 22 by a time determined by the digital number at the output of unit 19. It will be assumed that counter 12 is positive edge responsive and therefore the signal at the control input 25 of selector 22 and at the write enable input 109 of memory 5 is logic "1" for the first half of each period when the count in counter 12 is stationary, and logic "0" for the second half thereof.

Thus for each count in counter 12 this count is applied unchanged to the address input 9 of memory 5 for part, for example the first half, of the relevant period, and is applied in a modified form, i.e.

increased or decreased by the quantity present at the output of unit 19, forthe remaining part, for example the second half, of the relevant period. Each time the count in counter 12 is applied unchanged to address signal input 9 the ignal at write enable input 109 has one value, for example, logic "1", and chip enable input 107 (fed from output 111) also becomes logic "1", and each time the count in counter 12 is applied to input 9 in modified form the signal at write enable input 109 has its other value, for example logic "0", and chip enable input 107 again becomes logic "1".

With the above assumptions and assuming moreov erthat, for example, counter 12 is an up-counter and unit 17 is a subtractor, it will be seen that the signal at data input 6 of memory 5 is written into successive locations of memory 5 during the first halves of successive clock pulse periods, and that these locations are subsequently read out during the second halves of successive clock periods after a time delay determined by the time by which the succession of values at the output of subtractor 17 lags the corresponding succession of values at the output of counter 12, and hence by the output of unit 19. This delay is chosen to correspond to the delay T1 produced by the delay line 5 of Figure 1.

Assuming, as previously mentioned, that monostable circuit 7 is replaced by a direct connection, it will be seen that an input pulse at terminal 1 will be transmitted unchanged by AND gate 3 if and only if it does not coincide with the read out from memory 5 of a pulse previously written into memory 5, i.e. if and only if it does not succeed another such pulse by a time equal to the aforesaid time lag.

Monostable 7, the astable period of which is longer than one clock signal period at the output 104 of generator 14, performs, if present, the same function as the monostable 7 of Figure 1. In the presence of monostable 7 the lengths of the pulses written into memory 5 will be increased, so that an input pulse atterminal 1 will be transmitted un changed by AND gate 3 if and only if it does not succeed another such pulse at input terminal 1 by a time lying between the aforesaid time lag and the aforesaid time lag increased by the astable period of monostable 7.

The address signal generator 11 of Figure 1 also includes an (optional) second adder or subtractor 112 one (multiple) input 113 of which is fed from the output 20 of adder or subtractor 17 and the other (multiple) input 114 of which is fed with a predetermined digital number by an (optional) unit 115, for example another read/write memory or a register.

The (multiple) output 116 of adder or subtractor 112 is connected to a first (multiple) input 117 of a data selector 118 the other (multiple) input 119 of which is fed from the output 15 of counter 12. The (multiple) output 120 of the data selector 118 has the same width as the output 15 of the counter 12, so that any carry signal generated in the circuits 17 and 112 is ignored at the output 120. The control signal input 121 of the data selector 118 is fed from the control signal input 105 of the generator 11. (If the components 112 and 115 are omitted the output 20 of adder orsubtractor 17 should be connected directly to input 117 of data selector 118).

It will be seen that the components 17,19 and 118, and 112, 115 if present, together with their interconnections effectively constitute a second controllable adder or subtractor circuit; when the signal at control input 105 has one value the digital number at the output 15 of counter 12 is fed directly to the output 120 of data selector 118 and hence to the second output 106 of generator 111, whereas when the control signal at input 105 has its other value the digital number appearing at the output 105 will be the digital number appearing at the counter output 15 increased or decreased by the output of unit 19, and increased or decreased by the output of unit 115 if present, with any resulting carry digit ignored.As previously mentioned, the number at the output 106 of generator 11 is used as the address signal for memory 38, the "write enable" input 110 of which is fed from the output 104 of clock signal generator 14 via an inverter 122 and an OR gate 223.

The "chip enable" input 108 of memory 38 is fed from the output 111 of clock signal generator 14 via an AND gate 123 the second input of which is fed from input terminal 1 and output 104 of generator 14 via an OR gate 124. Thus the chip enable input 108 of memory 38 is always fed with a logic "1" in the first half of each period of the clock signal at output 104, and is also fed with a logic "1" in the second half thereof if logic "1" should be present at input terminal 1 (or at the output of monostable 7 if present).Because "write enable" input 110 of mem ory 38 is fed from output 104 of generator 14 via the inverter 122 memory 38 is always read in the first half of each period of the clock signal at the output 104, and is also written into during the second half of that period if a logic "1" should then be present at the input 1 (because of the effect of the "chip enable" signal).

Control input 105 of generator 11, and hence control input 121 of data selector 118, is fed with the output of a NOR gate 125 the inputs of which are fed from the output 104 of generator 14 and from the output of AND gate 3 respectively.

Making, for example, the previously-mentioned assumptions for the natures of the components 12, 17 and 22, i.e. that counter 12 is a positive-edgeresponsive up-counter, that component 17 is a subtractor, and that data selector 22 is such that its input 21 is connected to its output 24 when the signal at its control input 25 is a logic "0" and its input 23 is connected to its output 24 when the signal at its control input 25 is logic "1 ", and assuming moreover that, for example, the components 7, 112 and 115 are omitted and that data selector 118 is such that its input 119 is connected to its output 120 when the signal at its control input 121 is logic "0" and its input 117 is connected to its output 120 when the signal at its control input is logic "1", it will be seen that the number at the output 106 of address signal generator 11, and hence at the address input 30 of memory 38, will be the number at the output of counter 12 during the first half of each clock period at the output 104 of generator 14, i.e. when memory 38 is read, will also be this number during the second half of each said clock period, (i.e. when memory 38 is written into if a pulse is present at input terminal 1) if the output of gate 3 is logic "1", and will be the number at the output of counter 12 reduced by the number at the output of unit 19 during the second half of each said clock period if the output of gate 3 is logic "0".Thus during the first half of each said clock period memory 38 is read at an address corresponding to the count in counter 12, and during the second half of each said clock period (when memory 5 is read out) a logic "1" signal will be written into the same address if the output of gate 3 is logic "1" and a pulse is present at input terminal 1, and a logic "0" signal will be written into an address in memory 38 corresponding to the count in counter 12 decreased by the number at the output of unit 19 if the output of gate 3 is logic "0" and a pulse is present at input terminal 1. If no pulse is present at input terminal 1 there will be no write operation into memory 38 during the second half of the clock pulse cycle.This means that if an input pulse at terminal 1 coincides with the appearance of a logic "0" signal at the output 4 of memory 5 a logic "1" signal will be written into memory 38 at a given address. If another input pulse occurs at terminal 1 after an interval at which counter 12 has progressed to a count which, if reduced by the number at the output of unit 19, will result in the same address being accessed in memory 38, i.e. if the second pulse occurs a time T1 after the first pulse, the previously written logic "1" will be overwritten by a logic "0". The bit stored at the relevant address, whether overwritten or not, will in any case be read out to output terminal 2 after a time corresponding to the complete cycle time of counter 12. Thus the functions of the components 38,29 and 35 of Figure 1 are performed with, effectively, a further delay line being inserted between the output of delay line 38 and the output terminal 2 of Figure 1, the combined delay produced by this further delay line and delay line 38 being equal to the complete cycle time of counter 12 of Figure 2.

In orderthata logic "1 " written into memory 38 should not be read out more than once the output 32 of memory 38 is also connected to the data input 225 of a positive-clock-pulse-edge-responsive D-type flip-flop 224 the Q-output 226 of which is connected to the other input of OR-gate 223. The "clear" input 227 of flip-flop 224 is fed from the output 111 of clock pulse generator 14, and the clock input 228 of flip-flop 224 is fed from the 0 output 229 of a positive-edge-responsive monostable 128 the input 230 of which is also fed from the output 111 of clock pulse generator 14. The astable period of monostable 128 is longer than the access time of memory 38 but shorter than the durations of the "chip-enable" pulses at the output 111.Thus, if a logic "1" appears at the output of memory 38 during a read operation therein, a logic "1" is substantially immediately applied to the write enable input 110 thereof, causing the output signal of gate 3 to be written at the same address. Each time this occurs flip-flop 224 is reset or cleared when the next leading edge occurs in the signal at output 111 of clock pulse generator 14. If the action of flip-flop 224 causes the duration of each logic "1" signal at output terminal 2 to be too short, terminal 2 can be fed from the output 226 of flip-flop 224 instead of directly from memory 38.

If monostable 7 is provided in the apparatus of Figure 2 then the components 112 and 115 should also be provided (to produce the effect of making the delay produced by the delay line 38 of Figure 1 greater than the delay produced by the delay line 5 by an amount equal to the astable period of monostable 7 as previously described). The increase in the effective delay will be determined by the number at the output of unit 115, which number should therefore be chosen accordingly. Monostable 7 may conveniently be formed by a counter circuit to a clock signal input of which the output 104 of clock signal generator 14 is connected, this counter circuit being constructed to respond to the occurrence of a pulse at input terminal 1 by counting through a number of counts determined by the content of a register and generate a signal for the duration of each such counting operation.If monostable 7 is constructed in this way the correct correspondence between its astable period and the difference between the delays effectively produced by the memories 5 and 38 may be automatically obtained by using the unit 115 as the said register.

As previously indicated, the up-counter 14 may be replaced by a down-counter and/or the subtractors 17 and 112 may be replaced by adders. Moreover the two inputs of each subtractor 17 and 112 may be interchanged.

Although the apparatus of Figure 2 is arranged so that a logic "1" signal written into memory 38 appears, possibly after being overwritten by a logic "0" signal, at output terminal 2 a time equal to the cycle time of counter 12 after it has been written, it will be evident that this is not essential. It is merely necessary that the signal is read from memory 38 after it has had the possibility of being overwritten and before the corresponding address is next written into.Thus, for example, an inverter may be included in all the signal paths from output 104 of generator 14 other than the path to counter 12, so that memory 5 is read and memory 38 is written into during the first half of each period when the count in counter 12 is stationary, and memory 5 is written into and memory 38 is read during the second half of each said period, provided that NOR gate 125 is replaced by an OR gaite having an inverter in its input from gate 3.This will result, during the first half of each said period, in a logic "1" being written into an address in memory 38 corresponding to the count in counter 12 if the output of gate 3 is logic "1" and a pulse is present in the input signal, and in a logic "0" being written into an address in memory 38 corresponding to the count in counter 12 decreased by the number(s) atthe output(s) of unit(s) 19 (and 115) if the output of gate 3 is logic "0" and a pulse is present in the input signal and, during the second half of each said period, in a read operation at the latter address.

It has been assumed that, in the apparatus of Figure 2, the information at the output 4 of memory 5 during a read operation in memory 5 becomes reliable immediately at the start of the relevant chip-enable pulse at the memory input 107. If memory 5 does not have this property a D-type positive-clock-pulse-edge-responsive fl ip-flop (not shown) may be included in the signal path from the output of gate 3 to the memory 38 and to the gate 125, i.e. in such manner that its D-input is fed from gate 3 and its Q-output feeds gate 125 and data input 37 of memory 38, the clock input of this flip-flop being fed from output 104 of clock pulse generator 14.Because this flip-flop will effectively produce an additional delay equal to one period of the clock pulse signal at the output 104 a compensating delay should, in such a case, be introduced in the signal path from input terminal 1 to gate 124 (and in the signal path through delay device 102 if present). This compensating delay can be produced by providing a further positive-clock-pulse-edge-responsive D-type flip-flop (not shown) in the signal path from terminal 1 (or monostable 7 if present) to gate 124, i.e. in such manner that its D-input is fed from terminal 1, its clock input is fed from output 104 of clock pulse generator 14, and its Q-output feeds gate 124.

As previously mentioned, it is assumed that the pulses making up the input signal at terminal 1 of Figure 2 each have a length of one period of the output signal of clock pulse generator 14 and are each synchronised with this output signal. If this is not the case a pulse of the required length can be generated from each pulse of the input signal by including the unit 27 in the input signal path to terminal 1. One possible construction for the unit 27 is shown in Figure 3.

As shown in Figure 3, the unit 27 of Figure 2 may comprise a pair of resettable D-type flip-flops 39 and 40 respectively the outputs 41 and 42 of which are connected to respective inputs of an EXCLUSIVE-OR gate 43 the output of which is connected to the terminal 1 of Figure 2. The inputterminal 1Aof Figure 2 is connected to the D-input 44 of flip-flop 39 and is also connected to the reset inputs 45 and 46 of the two flip-flops via an inverter 47. The output 41 of flip-flop 39 is connected to the D-input 48 of flip-flop 40, and the clock inputs 49 and 50 of the two flip-flops are fed from a terminal 51 which is connected to the output 104 of the clock pulse generator 14 of Figure 2. When a pulse occurs in the input signal to terminal 1A flip-flop 39 is set when the next clock pulse occurs, producing an output from gate 43.When the next clock pulse occurs flip-flop 40 is also set, returning the output of gate 43 to logic "0". Both flip-flops are reset via the inverter 47 when the input pulse terminates.

It may be that the apparatus of Figure 2 is required to only respond to an input signal having the "correct" pulse repetition interval if that signal also satisfies one or more other requirements. Figure 4 shows a possible alternative construction for the unit 27 of Figure 2 which renders the apparatus of Figure 2 responsive to input signals having the "correct" pulse repetition interval only if the pulses thereof have lengths which lie between predetermined limits.

The unit 27 of Figure 4 comprises an up-counter 77 the (multiple) count signal output 52 of which is connected via a multiple gate 78 to the (multiple) address signal input 53 of a further memory 54 which is capable of storing a single bit at each address. The data output 55 of memory 54 is connected to the terminal 1 of Figure 2. The input terminal 1A of Figure 2 is connected to the countenable input 57 of counter 77, to the reset inputs 58, 59 and 60 of data flip-flops 61,62 and 63 respectively and, via an inverter 64, to the data input 65 of flip-flop 61. The outputs 66 and 67 of flip-flops 61 and 62 respectively are connected to the data inputs 68 and 69 respectively of flip-flops 62 and 63 respectively and to respective inputs of an EXCLUSIVE-OR gate 70. A second EXCLUSIVE-OR gate 71 has its respective inputs fed from the outputs 67 and 72 of the flip-flops 62 and 63.A clock signal input terminal 51, fed from the output 104 of the clock pulse generator 14 of Figure 2, is connected to the clock inputs 73,74, 75 and 76 of the flip-flops 61,62 and 63 and the counter 77 respectively. The output of EXOR gate 70 is connected to the control or enable input 79 of gate 78 and also to the "read" input 80 of memory 54. The output of EXOR gate 71 is connected to the reset input 81 of counter 77.

The unit 27 of Figure 4 operates as follows. When a (positive or logic "1 "-going) pulse appears in an input signal at terminal 1Athe flip-flops 61,62 and 63 are both logic "0" and gate 78 and memory 54 are both disabled. Counter 77 (the count in which is initially zero; see below) is enabled and starts to count up underthe control of the clock pulses at terminal 51. When the input pulse eventually terminates, counter 77 is disabled and flip-flops 61,62 and 63 are set via inverter 64 by the first, second and third subsequent clock pulses respectively, so that EXOR gate 70 produces a logic "1" for the duration of the said first subsequent clock pulses and EXOR gate 71 produces a logic "1" forthe duration ofthe said second subsequent clock pulse.The first of these logic "1's causes the count in counter 77 (which corresponds to the duration of the pulse in the input signal) to be applied to the address input 53 of memory 54 and the bit at the corresponding address to be applied to terminal 1. The second of these logic "1 "s resets counter 77. The memory 54 is pre-programmed in such a way that it contains a 1-bit at all those addresses which correspond to counts in counter 77 which correspond to an input pulse length to which it is required that the arrangement responds, and 0-bits everywhere else. Therefore an input pulse at terminal 1A gives rise to a one-clock-period-long output pulse at terminal 1 if and only if the input pulse length is such as to give rise to a final count in counter 77 which addresses a 1-bit in memory 54, i.e. if and only if this length is one to which the unit has been preprogrammed to respond.

Claims (9)

1. Apparatus for detecting those events in an input signal which neither precede another such event by a predetermined time nor succeed another such event by said predetermined time, said apparatus comprising first delay means for delaying signals by at least said predetermined time, a coupling from the apparatus input to the input of said first delay means, a detector circuit to a first input of which the apparatus input is coupled and to a second input of which the output of said first delay means is coupled in such manner that the delay occurring in the signal path from the apparatus input to said second input will be greater by said predetermined amount than any delay occurring in the signal path from the apparatus input to said first input, said detector circuit being constructed to respond to the application of a signal to its first input which arises from the occurrence of a said event at the apparatus input by generating an output signal if and only if the signal at its first input does not coincide with the presence at its second input of a signal which arises from the previous occurrence of a said event at the apparatus input, second delay means, a coupling from the output of said detector circuit to the input of said second delay means, a coupling from the output of said second delay means to the apparatus output, and a signal transfer blocking circuit to a control input of which the apparatus input is coupled, said blocking circuit being constructed to block the transfer to the apparatus output of a said output signal by the second delay means if and only if the said output signal, after delay in said second delay means by a given amount, coincides with the presence at said control input of a signal arising from the occurrence of a said event at the apparatus input, said given amount, when added to any delay occurring in the signal path from the apparatus input to the detector output via said first input, being greater by said predetermined time than any delay occurring in the signal path from the apparatus input to said control input.

2. Apparatus for detecting those events in an input signal which neither precede another such event by a time which lies between predetermined minimum and maximum values nor succeed another such event by a time which lies between said predetermined minimum and maximum values, said apparatus comprising first delay means for delaying signals by a time at least equal to said predetermined minimum value, a coupling from the apparatus input to the input of said first delay means, a detector circuit to a first input of which the apparatus input is coupled and to a second input of which the output of said first delay means is coupled in such manner that the delay occurring in the signal path from the apparatus input to said second input will be greater by said predetermined minimum value than any delay occurring in the signal path from the apparatus input to said first input, said detector circuit being constructed to respond to the application of a signal to its first input which arises from the occurrence of a said event at the apparatus input by generating an output signal if and only if the signal at its first input does not coincide with the presence at its second input of a signal which arises from the previous occurrence of a said event at the apparatus input, a monostable circuit the astable period of which is equal to the difference between said maximum and minimum values, which monostable circuit is included in the signal path from the apparatus input to the second input of said detector circuit but not in the signal path from the apparatus input to the first input of the detector circuit, second delay means, a coupling from the output of said detector circuit to the input of said second delay means, a coupling from the output of said second delay means to the apparatus output, and a signal transfer blocking circuit to a control input of which the apparatus input is coupled via a monostable circuit the astable period of which is equal to the difference between said maximum and minimum values, said blocking circuit being constructed to block the transfer to the apparatus output of a said output signal by the second delay means if and only if the said output signal, after delay in said second delay means by a given amount coincides with the presence at said control input of a signal arising from the occurrence of a said event at the apparatus input, said given amount, when added to any delay occurring in the signal path from the apparatus input to the detector output via said first input, being greater by a time equal to said predetermined maximum value than any delay occurring in the signal path from the apparatus input to said control input.

3. Apparatus as claimed in Claim 2, wherein the monostable circuit included in the coupling from the arrangement input to said control input is constituted by the monostable circuit which is included in the signal path from the apparatus input to the second input of the detector circuit.

4. Apparatus as claimed in any of Claims 1 to 3, wherein said first delay means comprises a first read/write memory, an address signal generator a first output of which is coupled to an address signal input of said first read/write memory, said address signal generator being constructed to generate at said first output a continuous sequence of addresses which comprises first and second interleaved cyclically repeating subsequences where the second cyclically repeating subsequence is identical to the first cyclically repeating subsequence but is cyclically displaced relative thereto, each member of said first subsequence being different from all other members thereof, and means for applying a write signal to said first read/write memory in conjunction with the application to said first read/write memory of the members of one of said repeating subsequences and for applying a read signal to said first read/write memory in conjunction with the application thereto of the members of the other of said repeating subsequences, a data signal input of said first read/write memory constituting the input of said first delay means and a data signal output of said first read/write memory constituting the output of said first delay means, and wherein said second delay means, said detector circuit and said blocking circuit together comprise a second read/write memory to an address signal input of which a second output of said address signal generator is coupled, said address signal generator being constructed to generate at its second output successive members of a first cyclically repeating sequence of addresses in synchronism with the generation at its first output of the successive members of one of said repeating subsequences, each member of said first cyclically repeating sequence being different from all other members thereof, to generate at its second output, when a signal at a control input thereof has a first value, successive members of a second cyclically repeating sequence of addresses in synchronism with the generation at its first output of the successive members of the other of said repeating subsequences, said second cyclically repeating sequence being identical to said first cyclically repeating sequence but being cyclically displaced relative thereto, and to cyclically displace said second cyclically repeating sequence for as long as the signal at its control input has a second value, means for applying a read signal to said second read/write memory in conjunction with the application to said second read/write memory of the members of said first cyclically repeating sequence of addresses and for applying, each time a said event occurs at the apparatus input, a write signal to said second read/write memory in conjunction with the application to said second read/write memory of a member of said second cyclically repeating sequence of addresses or of a member of the cyclically displaced version thereof, and a coupling circuit coupling the apparatus input and the output of said first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present) to a data signal input of said second read/write memory and to the control input of the address signal generator, said coupling circuit being constructed to apply, each time a said event occurs at the apparatus input, a signal having one of said first and second values to the control input of the address signal generator if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present), a signal having the other of said first and second values to the control input of the address signal generator if a signal which arises from the previous occurrence of a said event at the apparatus input is not present at the output of the first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present), a signal having a first value to the data signal input of the second read/write memory if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present), and a signal having a second value to the data signal input of the second read/write memory if a signal which arises from the previous occurrence of a said event at the apparatus input is not present at the output of the first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present), a data signal output of said second read/ write-memory being coupled to the apparatus output.

5. Apparatus as claimed in Claim 4, wherein each member of the cyclically displaced version of said second cyclically repeating sequence of addresses is identical to the member of said first cyclically repeating sequence of addresses which immediately precedes or succeeds it at the address signal input of the second read/write memory.

6. Apparatus as claimed in Claim 5, wherein said address signal generator comprises a cyclic counter, a clock signal generator having an output coupled to a clock signal input of said cyclic counter, first and second controllable digital adder or subtractor cir cuits each having an input to which the output of said cyclic counter is coupled and each being controllable between first and second states in the first of which it generates at its output a digital number equal to any digital number present at its input and in the second of which it generates at its output a digital number equal to any digital number present at its input plus or minus a given digital number and with any resulting carry digit ignored, a coupling from an output of said clock signal generatorto a control input of said first adder or subtractor circuit so that said first adder or subtractor circuit will be controlled to its first state and to its second state for each count in said counter, and couplings from an output of said clock signal generator and from the control input of said address signal generatorto a control input of said second adder or subtractor circuit in such manner that said second adder or subtractor circuit will be controlled to its first state and to its second state for a given count in said counter each time a said event occurs at the apparatus input if a signal which arises from the previous occurrence of a said event at the apparatus input is present at the output of the first delay means or of the cascade combination of said first delay means and the first-mentioned monostable circuit of Claim 2 (if present), and will be controlled solely to a given one of its states otherwise, the outputs of the first and second adder or subtractor circuits constiputing the first and second outputs respectively of the address signal generator.

7. A detector arrangement for detecting those events in an input signal which repeat at substantially equal intervals which are of a given size, comprising a gate circuit, apparatus as claimed in any preceding Claim coupling the arrangement input to a control input of said gate circuit in such manner that the production of an output signal by the apparatus will block transmission through said gate circuit, and third delay means coupling the arrangement input to a second input of said gate circuit, said third delay means being constructed to delay signals passing through it by an amount equal to the delay occurring in the signal path from the arrangement input to the control input of said gate circuit via the first input of the detector circuit and the second delay means.

8. Apparatus for detecting those events in an input signal which neither precede another such event by a predetermined time nor succeed another such event by said predetermined time, or for detecting those events in an input signal which neither precede another such event by a time which lies between predetermined minimum and maximum values nor succeed another such event by a time which lies between said predetermined minimum and maximum values, substantially as described herein with reference to Figure 1 or Figure 2 of the drawings.

9. A detector arrangement for detecting those events in an input signal which repeat at substantially equal intervals which are of a given size, substantially as described herein with reference to Figure 1 or Figure 2 of the drawings.