GB2088666A - Electrical filter circuits and methods of filtering electrical signals - Google Patents

Abstract

Electrical filters are described which are akin to digital wave filters but which employ analogue computation. The filters are made up of multiport adaptor cells incorporating unit delays, and each cell computes reflected signals at ports from incident signals by using analogue techniques to solve equations relating incident and reflected signals. The adaptor cells use capacitors coupled by switches operated in two phases. For example, in first phases, capacitors C1 to C3 receive voltages corresponding to incident signals, and capacitors C4 and C5 receive voltages representing differences between incident signals. In second phases reflected signals corresponding to additions, subtractions and multiplications of the voltages held by the capacitors are derived by reconnecting the capacitors. Each cell is part of a unit element or represents an inductance or capacitance as determined by a feedback network in which in first phases the reflected signal at one port is stored in a capacitor C6 and used, in the next phase, as the incident signal at that port. <IMAGE>

Description

SPECIFICATION Electrical filter circuits and methods of filtering electrical signals The present invention relates to electrical filter circuits and methods of filtering which though akin to wave filters and digital wave filters do not employ resonant sections of microwave circuits or digital computers. The invention is particularly useful in the construction of integrated circuit electrical filters.

The properties of many filters, such as active filters, are sensitive to variations in their elements. However inductance/capacitance (LC) filters present the least problems in this respect when realised in the form of suitable designed ladder filters. From the theory of microwave transmission line filters it is known that is is always possible to construct filters by cascading a certain number of lengths of transmission line with different characteristic impedances so forming a filter with similar properties.

A development from wave filters is the "wave digital filter" described by Fettweis in "Digital filter structures related to classical filter networks', Arch. Elek Ubertrug (Germany), Vol. 25, No.

2, pp. 79 - 89, February 1971. Briefly, the signal to be filtered is applied to an analogue-todigital converter. The digital values so obtained are passed to a computer which calculates an output signal by simulating the delays which occur in various sections of a wave filter and by combining signals representing the outputs of these sections. The output of the filter is then applied to a digital-to-analogue converter to provide an analogue output signal.

In a later paper (IEEE Transactions on Circuit Theory, Page 668, 1972) Fettweis has shown that the digital wave filter retains the property of minimising sensitivity which is found in ladder networks.

In his February 1971 paper Fettweis discloses that digital filters can be formed by a plurality of n-port adaptors with the ports of each adaptor receiving signals after a delay T/2 from, and transmitting signals after a delay T/2 to, other adaptors, where T is the sampling period for providing digital signals from analogue signals. Each pair of delays T/2 represents a unit element of a particular characteristic impedance. Fettweis shows how digital wave filters can be simulated by n-port adaptors and delays. At the kth port of an n-port adaptor where the ports are connected in parallel, the reflected wave Bk is given by Bk = AoAk equation 1 where Ak is the incident wave at the kth port and

equation 2 ak = 2Gk/ (G, + G2 - - - - + G,), and Gk = the reciprocal of the resistance of the kth port.

Where n-ports are connected in series Bk = A - PkAo, and equation 3

equation 4 where Pk = 2Rk/ (R, + R2 + - - - - + Rn) and Rk = the resistance of the kth port.

The wave digital theory developed by Fettweis shows that a number of cascaded sections of transmission line can be simulated for example by a series of two-port adaptors with a port of each adaptor passing a computed output to a port of the next adaptor in the series and vice versa, the computed signals passing by way of unit delays, corresponding to unit elements.

For adaptors of such filters Fettweis gives the equations B, = A2 + a(A2A,), and equation 5 B2 = A, + a!A2A) equation 6 where B1 and B2 are reflected waves at ports 1 and 2, respectively, A1 and A2 are incident waves at ports 1 and 2, respectively, OL = (R,R2)/(R, + R2), and R1 and R2 are the resistances of the first and second ports respectively. Note that a < 1 for non-negative resistance values.

When it is required to design a solid state integrated circuit filter, ladder networks cannot be used as such since they require lumped inductances, microwave filters employing transmission lines are only suitable at very high frequencies and digital wave filters require the use of a computer such as a microprocessor which is too complicated for mass production and too slow to achieve filters with reasonably high frequency characteristics.

As an alternative active filters employing high gain operational amplifiers connected to simulate inductances have been used In such filters the resistances required are difficult to make accurately in solid state form and have therefore been replaced to some extent by switched capacitors; that is each resistor is replaced by a capacitor in series with a switch which is operated above the Nyquist frequency. A problem which arises in using switched capacitors is that in each filter section at least two capacitors are required and the ratio of capacitances may be of the order of 1 00:1. This requires a capacitor of comparatively large size in each section and these capacitors require a large amount of area on an integrated circuit chip.A further problem is that comparatively complicated amplifiers are required which have a fair number of components and therefore also take up a relatively large chip area. A disadvantage of some switched capacitor filters is that their bandwidth is restricted to a low percentage, about 10%, of the Nyquist frequency because the theoretical model of the filter used becomes inaccurate at higher frequencies.

According to a first aspect of the invention there is provided an electrical filter circuit having a plurality of interconnected multiport adaptor cells, each adaptor cell comprising means for computing, using sampled analogue signals, output signals for the ports of that cell from input signals when applied to the ports of the cell, computation being carried out according to equations representing the calculation of reflected waves from the ports when incident waves are applied to the ports, and the constants of the equations, the number of adaptor cells and the interconnection of adaptor cells being selected to provide a required filter characteristic.

In computing each output signal the computing means of each adaptor cell may make output signals available at respective predetermined times and thus the adaptor cells of the present invention then incorporate the above mentioned unit delays. In other forms of the invention delay circuits may be connected between adaptor cells.

According to a second aspect of the invention there is provided a method of filtering electrical signals using a plurality of calculation stages each of which corresponds to a multiport adaptor cell, the method comprising calculating, using sampled analogue signals, for each said stage, output signals for the ports of that stage from input signals when applied to the ports of that stage, the calculation being carried out according to equations representing the reflected waves from the ports when incident waves are applied to the ports, and the constants of the equations, the number of adaptor stages and the selection of output signals for use after a predetermined delay as input signals to other stages being arranged to provide a required filter characteristic.

A main advantage of the present invention is that since the computing means of each cell employs analogue signals, it can be formed, as will be explained, by capacitors and switching transistors but no resistors, and it is therefore ideal for integrated circuit construction using metal oxide silicon (MOS) or complementary MOS(CMOS) techniques.

Further advantages are that capacitance ratios are relatively small, about 30:1 maximum for the usually fabricated filter designs allowing small capacitors to be used, and that the cut-off frequency of the filter may be above 45% of the clock frequency which is used in switching the transistors if the sin(x)/x effect which is present in any sampled system is compensated for in some way or is acceptable.

In effect in this form of the invention where switching means is employed, analogue samples of signals are applied to, and used within, the filter. The use of samples allows wave equations to be used in calculating output signals at ports.

The adaptor cells may for example be n-port parallel adaptors, or n-port series adaptors, or two port adaptors. For n-port parallel adaptors equations 1 and 2 given above are used in calculating reflected waves and for n-port series adaptors equations 3 and 4 are used.

The quantities A1, A2, B, and B2 in equations 5 and 6 are voltage wave quantities as explained by Fettweis. However using different equations current or power waves can be modelled. In the specific embodiments of the invention described below voltage representation is chosen.

Equations 1 to 6, inclusive, can be rewritten with lower case A's and B's to represent instantaneous equations or samples of the original wave quantity. For example: - for parallel adaptors bk = a0 -

for series adaptors bk = ak - Pkao

b, = a2 + a(a2 - a1) equation 7 b2 = a, + a(a2 - a1) equation 8 where b,, b2, a, and a2 are voltages. Note that in the theory these calculations are performed with no delay whatsoever and then a delay is artificially added. In the embodiments of the invention described below the delay is merged with the adapator in order to allow time for the results required to be computed.

In designing a filter according to the invention the required characteristic is first decided and appropriate parameters are selected according to standard filter theory to define a known type of ladder filter, for example a Chebyshev filter, or a Butterworth filter, or an elliptical filter. Such parameters are readily available, and the theory is well known and both are given for example in the text books: "Network Theory: Analysis and Synthesis", by Shlomo Karni, published by Ally and Bacon in 1966; and "Active Filters for Communications and Instrumentation", by P.

Bouron and F.W. Stephenson, published by McGraw Hill in 1 979.

Having obtained the required parameters the interconnection of the adaptors and the selection of equations for the constants are then carried out according to the theory developed by Fettweis and given in his February 1971 paper.

Each adaptor cell with n-ports may comprise a common terminal (for example at system ground potential) and n-pairs of terminals, one pair for each port and each pair comprising an input terminal and an output terminal. The computing means in each cell may then calculate output signals for the output terminals from input signals when applied to the input terminals.

One important form of the invention employs a series of two-port adaptors.

Thus, a filter circuit according to the invention may comprise a series of two-port adaptor cells having first and second ports in which the second port of each cell is coupled to the first port of the next cell in the series, except for the first cell in the series where the first port is coupled to the input of the filter circuit and the last cell in the series where the second port is coupled to the output of the filter circuit, the computing means of each cell computing reflected signals b, and b2 for the first and second ports, respectively, of that cell from incident signals a, and a2 when applied to the first and second ports, respectively, of that cell according to the equations:: - b, = a2 + a(a2 - a1) and b2 = a, + a(a2 - a1), the constant a and the number of adaptor cells in the said series being selected to provide a required filter characteristic.

In a filter according to the third aspect of the invention, each adaptor cell may comprise a common terminal, and two pairs of terminals, the first pair consisting of a first input terminal and a first output at which, in operation, the signals a, and b,, respectively, appear, and the second pair consisting of a second input terminal and a second output terminal at which, in operation, the signals a, and b2, respectively, appear.

Preferably the computing means for each cell comprises capacitors interconnected by switching means operated in a switching cycle to charge to voltages used in calculating equations 7 and 8. Addition may be carried out by summing the voltages across two or more capacitors and multiplication by factors less than one may be carried out by transferring charges between capacitors of different values.For example in order to calculate equation 7 a cell may comprise first switching means controlled by a switch control circuit to apply an input voltage appearing at one input terminal of the cell to a first capacitor in a first switching interval, second switching means controlled by the switch control circuit to apply both the said input voltage and a second input voltage appearing at the other input terminal to a second capacitor to form the difference between these voltages across the second capacitor in the first or a second switching interval, third switching means controlled by the switch control circuit to couple the second capacitor to a third capacitor in a further switching interval, the third capacitor having a capacity which is y times that of the second 1-a capacitor, where y = , and the third capacitor being coupled in series with the first a capacitor with the result that the voltage across the series combination so formed is equal to the voltage at the said one input terminal plus a times the difference between the input voltage at the said other input terminal and that at the said one input terminal.

Buffer amplifiers with high input impedance and low output impedance, and advantageously of unity gain, are preferably so arranged in the cells that ports which are interconnected are buffered.

Another important form of the invention employs three port adaptor cells, which may be either series or parallel (see the paper by Fettweis, February 1971 for an explanation of series and parallel adaptors). In general any filter employing lumped series and shunt reactances can be simulated using unit elements and series and parallel adaptor cells. The filter is first transformed using Kuroda transforms into shunt and series reactances separated by unit elements and then the reactances and unit elements are replaced by three port adaptor cells. As is mentioned below series adaptor cells may be replaced by modified parallel adaptor cells. Filter transformation using Kuroda transforms is described in the paper "On the Design of Wave Digital Filters with Low Sensitivity Properties", by K. Renner and S.C. Gupta, IEEE Trans. Circuit Theory, Vol.

CT - 20, No. 5, Sept., 1973 pages 555 - 567 and the book "Modern Filter Theory and Design", edited by G.C. Temes and S.K. Mitra, Wiley, New York, 1973, see Chapter 7, particularly.

For parallel three-port adaptors the equations to be solved by analogue calculation are: - bk = a,a, + a2a2 + a3a3 - equations 9 where ak and bk are the incident and reflected signals at the kth port, a = 2Gj/(G, + G2 + G3), and Rj = 1 /Gj = the reference resistance of the ith port. For the derivation of these equations see Fettweis, February 1971. It follows from the above equation for a, that a, + a2 + a2 = 2, and this fact is of crucial importance in the realisation of these adaptors.

The exact circuit form required to implement the adaptor using voltage-sampled-data techniques depends on which, if any, of the alpha multipliers is greater than one. In a large proportion of practical circuits it will be found that one of the alphas is greater than one and for that reason it will be assumed that one such multiplier exists. If all the alphas are less than one the adaptor implementation is slightly more complex though it can still be achieved using the invention.

Assuming that a, is greater than one, then equations 9 may be rewritten as follows: - b, = (a1 - 1 )a1 + a2a2 + a3a3 equation 10 b2 = b, + a1 - a2 equation 11 b3 = b, + a1 - a3 equation 12 The equation for b, can be solved by simply separately charging three suitably ratioed capacitors to voltages a,, a2 and a3 and then connecting them in parallel.

The equations for b2 and b3 can be solved by connecting capacitors precharged to (a1 - a2) and (a1 - a3) in series with the b, output.

For series adaptors the equations to be solved by analogue calculation are: - bk = ak = ak(a, + a2 + a3) equation 1 3 where ak = 2Rk/(R, + R, + R3) and R1 is the resistance of the ith port.

To solve these equations use is made of an equivalence which exists between a three-port series adaptor and a three-port parallel adaptor. This equivalence is shown in Fig.10 and will now be explained.

A three-port parallel adaptor solves the equations b, = (a1 - 1) a, + a2a2 + a3a3 b2 = &alpha;1a1 + (&alpha;2 -1)a2 + &alpha;3a3 b3 = &alpha;1a1 + a2a2 + (a3 - 1 )a3 Let a' and b1' be as shown in Fig. 10. Then we have a1 = a,'; a2 = - Xa21 ; a3 = - Ya31 b, = b11 ; b2 = Xb2,; b3 = Yb3' where X = (a,/a2) and Y = (a1/a3) Now consider the relationship between the dashed variables.

bi' = b, = (a1 - 1)a1 + a2a2 + a3a3 = (&alpha;1 - 1)(- a1')+ &alpha;2( - Xa2') + &alpha;3( - Ya3') = a1' - &alpha;1a1' - X&alpha;3a2' - Y&alpha;3a3' Therefore b,' = a11 - a1(a11 + a2' + a3) and this is one of the equations for a series adaptor (see equations 13).

Similarly b2' = b2/X = (a2/a,)b2 &alpha;2 So b2' = [a,(a,') + (a21)(Xa2') + a3(Ya3')] a1 = a21 - a2(a11 + a21 + a31) This is another of the equations for a series adaptor and the last equation, that for b3,, may be found similarly.

Consider now the consequences of the extra multipliers introduced by this equivalence.

The output b3' is connected to the input a3' by a time delay only if the adaptor connects a capacitor into the circuit, and by a time delay followed by a negation if the adaptor connects an inductor into the circuit. In both these cases the multiplication by Y is cancelled by the following multiplication of (1 /Y) and only the extra negation has any effect. This extra negation makes the feedback for a capacitor look like that for an inductor and vice versa.

The multiplier X (i.e. a,/a2) causes signal scaling to occur within the filter. Thus if a series adaptor is replaced by a parallel adaptor which has all its inputs negated the output from the modified parallel adaptor will be X times that which would have been present had a genuine series adaptor been used. As a result if the value of X is not too small (or too large) the through gain of the filter is varied, without otherwise altering its amplitude response.

Certain embodiments of the invention will now be described with reference to and as shown in the accompanying drawings, in which: - Figure 1 is the flow diagram of a wave filter, Figure 2 is a block diagram of a filter according to the invention for putting into effect the flow diagram of Fig. 1, Figure 3 is a circuit diagram of an adaptor cell used in the filter of Fig. 2, Figure 4 is a circuit diagram of a pair of adaptor cells which may be used in a filter of Fig. 2, Figures 5a, 5b and 5c show exemplary characteristics of low pass filters according to the invention, Figure 6 is a circuit diagram of a reference filter for a band-pass filter, using lumped reactances, which can be transformed into a filter according to the invention, Figure 7 shows the filter of Fig. 6 after resonating and the application of the Kuroda transformation, Figure 8 shows the wave-flow diagram of the filter of Fig. 6 using series and parallel adaptors, Figure 9 is a circuit diagram of a parallel adaptor cell for a filter according to the invention, Figure 10 illustrates the equivalence which exists between a series adaptor and a parallel adaptor, Figures 11 to 16 are circuit diagrams of adaptor cells corresponding to the adaptors 80, 82, 87, 88, 89 and 90 of Fig. 8 respectively, and Figure 17 shows the characteristics of a filter equivalent to that of Fig. 6 but constructed using the adaptor cells of Figs. 11 to 1 6.

In Fig. 1 the flow diagram of a wave filter comprises four adaptor stages 11 to 1 4 each equivalent to a two-port adaptor cell and three equal delays 15, 1 6 and 1 7. Each adaptor stage carries out the calculations given by equations 7 and 8 with different values of a as obtained in the way described above. The filter of Fig. 1 is a third order structure which requires for stages.

Each stage shows an incident wave "a'' and a reflected wave "b" with two subscripts, the first corresponding to the port number and the second to the second figure of the designation of the stage; for example b3 is the reflected wave at the first port of stage 1 3. The input signal for the filter is a" and the output signal b24. The signal a24 is usually zero as it usually represents the reflection from a matched resistive load and the signal B1, can be passed to termination or used as another output signal which has a frequency characteristic proportional to the inverse of the main filter characteristic corresponding to b24.

The second port of each stage is coupled to the first port of the next stage. Thus the reflected wave of one stage is incident on the next stage, and the reflected wave of the said next stage is incident on the said one stage.

An analogue voltage wave filter according to the invention for putting into effect the flow diagram of Fig. 1 is shown in Fig. 2. Signals to be filtered are applied to the sample-and-hold circuit 1 7 from a generator 1 8. The output of the sample-and-hold circuit is connected to a series of four adaptor cells 19, 20, 21 and 22 which are equivalent to the adaptor stages of Fig. 1. Of course other numbers of cells are used in other filters according to the invention.

These cells are described in more detail below but use capacitors and switches to carry out the calculations required by equations 7 and 8. In order to operate the switches mentioned a master oscillator 23 controls a P phase clock generator 24 which provides P switching signals on clock switching lines 25. Switching is at twice the Nyquist frequency and results in sample voltages, a sequence of which are regarded as being equivalent to the waves (incident and reflected) of wave filters.

The cells 1 9 to 22 have a system common terminal 26 which is often connected to ground. A terminal 30 which is equivalent to signal a24 of Fig. 1 is usually connected to system ground or buffered to be equivalent to this condition, while a terminal 10 equivalent to signal b1, is left floating; but these terminals may be used to provide additional or alternative filter output terminals.

The output of the cell 22 takes up the correct value in certain time slots and for this reason a sample-and-hold circuit 27 also receiving the timing waveform from the P phase clock generator 24 samples the output of the cell 22 at the appropriate time and holds the signal obtained.

Thus the output of the sample-and-hold circuit 27 is a stepped waveform and this is passed to a low pass filter 28 which by removing high frequencies "smooths" the output and provides a waveform suitable for a load 29.

A suitable adaptor cell for the circuit of Fig. 2 is shown in Fig. 3. In this special case P = 2 and the clock generator 24 is two-phase. A first port of the cell has a terminal 31 and this terminal is shown connected to a signal source 32 having a voltage a,. The signal a, may be from a second port of a previous cell or if the cell shown is the first in the filter than it is the input signal to the filter.

A further input terminal 33 is connected to a signal source 34 of voltage a2 and the voltage a2 is obtained from the first port of the next cell in the filter. In the case of the last cell in the filter there is no signal a2 and the input terminal 33 is suitably terminated.

Two switching waveforms are, as has been mentioned, supplied from the clock generator 24 and these switching waveforms are rectangular waveforms having "on" intervals which are slightly shorter than the "off' intervals. The waveforms are in antiphase so that only one waveform is "on" at a time and there is a small time lag between one waveform being "on" and the next waveform being in this state.

The first switching waveform closes switches 35 to 39 and this has the effect of charging a capacitor 40 to the voltage a, by way of the switch 35, the switch 38 connecting the other side of the capacitor 40 to ground. In a similar way a capacitor 41 is charged to the voltage a2. At the same time a capacitor 42 is charged to the voltage a2 - a1 by way of the switches 36 and 37. Note that at this time a capacitor 45 is fully discharged because of the short circuit placed across it by the switch 38.

When the first switching waveform comes to the end of its "on" period the switches 35 to 39 are opened and there is a short interval before the second switching waveform commences its "on" period when switches 43 and 44 closes. These switches transfer the charge on the capacitor 42 to the capacitor 45 but since the capacity of the capacitor 45 is y times the capacity of the capacitor 42 where y= (1 - a)/a the voltage on the capacitor 45 becomes a(a2 - a1).

The adaptor cell has output ports constituted by terminals 46 and 47 and these output terminals are buffered by amplifiers 48 and 49. The amplifier 48 receives an input signal which is the sum of the voltages across the series combination of capacitors 40 and 45 the latter also being in parallel with capacitor 42 in a two-phase system, that is it is the vo!tage: - a1 + a(a2 - a1) Similarly the amplifier 49 receives an input voltage: - a2 + a(a2 - a1) Thus calculations required by equations 7 and 8 are completed by the cell of Fig. 3, and the signals b, and b2 appear at the terminals 47 and 46, respectively.

The buffer amplifiers 48 and 49 have preferably a gain of i 1 and provide a low impedance output for the connection of ports of the previous and next cells in the series or for the load of the filter.

The way in which two cells are connected is shown in Fig. 4 where a cell 52 is identical to Fig. 3, but this figure also illustrates that a in equations 1 and 2 can be either positive or negative for a particular cell. In a cell 51 to the left of Fig. 4, a is negative since the lower terminal of the capacitor 45 is connected to ground but in a cell 52 to the right of Fig. 4, a is positive because the upper terminal of the capacitor 45 is connected to ground. Note that the switch 38 is always connected to the grounded side of the capacitor 45. The effect of making a negative can alternatively be achieved by interchanging a, and a2 while also interchanging b, and b2 in a cell for which a would otherwise be positive.

A succession of cells such as that shown in Fig. 4 can be regarded as having a forward path for signals from the input terminal 31 of the cell 51 to the output terminal 46 of the cell 52 and a reverse path such as would occur by reflection in a microwave filter from the input terminal 33 of the cell 52 by way of the output terminal 47 of this cell connected back to the input terminal 33 of the cell 51 and output terminal 42 of cell 51. This "reflected" signal is tapped off by way of the capacitors in each cell and combined with the forward travelling signal to give the required filter characteristic. Further filter characteristics are obtainable at the output terminal 42 of the first cell in the series.

The flow diagram of Fig. 1 shows delays 1 5 to 1 7 corresponding to unit elements. In the arrangement of Fig. 2 and that of Fig. 4 these delays are implicity by supplying reverse phases of the switching signal at alternate stages. Thus in Fig. 4 corresponding switches of the cell 52 are switched in antiphase to those of the cell 51 with the result that, for example, the output voltage of the amplifier 48 of the cell 51 is applied immediately by way of the switch 35 of the cell 52 to the capacitor 40 but the output voltage of the amplifier 49 of the cell 52 is delayed by the switch 39 of the cell 51 before it is applied to the capacitor 41.

If cells of the type shown in Fig. 4 are used the sample-and-hold circuit 1 7 of Fig. 2 is not required since the switches and capacitors of the first cell carry out this function.

At the present time the most appropriate way of building a filter of the type described with reference to Figs. 2, 3 and 4 is to provide an integrated circuit using the MOS or CMOS techniques. In this way the switches are formed by MOS transistors which have good switching characteristics and the capacitors can be accurately formed and are not dependent on the voltage between the substrate and applied signals. No resistors are required and none of the capacitors act as resistors as in the known form of switched capacitor filter. A further important advantage is that the buffer amplifiers 48 and 49 can be simply formed from a single pair of complementary transistors and this is an important saving in space and complication over an active filter where high gain multi-stage operational amplifiers are required.

As to choice of capacitor values, a one picofarad capacitor in MOS is sufficient to swamp parasitic capacitances and thus if the capacitor 42 in Fig. 3 is one picofarad the capacitor 45 may need to have a value of up to 30 picofarads. The capacitors 40 and 41 may also be about one picofarad. Such values have proved successful in MOS filters according to the invention but it is believed that smaller values are possible if some parasitic capacitances are allowed to become significant.

Nearly all types of electrical filter can be provided by connecting adaptor cells in a series as has been described; for example the filters can be low pass, band pass or high pass and they can be for example Butterworth filters and Chebyshev filters. If, for example, a low pass Butterworth filter is required the design is approached by considering the characteristic required and using tables to obtain the various coefficients and the number of sections for a ladder filter in the way well known to filter designers and described, for example, in Chapter 1 3 of the book "Network Theory: Analysis and Synthesis" by Shlomo Karni published by Ally and Bacon in 1 966. Having obtained the coefficients these are then appropriately substituted by an for each section in the way described by Fettweis.If the number of filter sections is N then the number of adaptor cells required is N or N + 1 when 3 or 2 port adaptors, respectively, are used.

A third order Chebyshev low pass filter is chosen here as an example which can be constructed according to Figs. 2, 3 and 4. The transfer function is: -

where T3 is the third order Chebyshev function, e is related to the passband ripple, O = with o, as the sampling frequency and 00= 1r(X/X5) with coo as the passband edge frequency.

Since a third order filter is to be constructed from two-port adaptors there will be four adaptors, and these can be regarded as equivalent to three sections of transmission line and a terminating resistor.

The value of is first determined from the passband ripple since 1 + 2 is the ratio of the maximum to the minimum value in the passband. Knowing e and He the values of the characteristic impedances of the three sections of transmission line are found from table 3 of R.

Levy "Tables of element values for the distributed low pass prototype filter", IEEE Trans. Vol.

MTT - 13, No. 5, Sept. 1965, pp. 514 - 536. The tables apply where the terminating impedances for the external filter terminals are each one ohm. The terminal 30 in Fig. 2 is connected to ground to provide a termination equivalent to one ohm and the terminal 10 is left floating. Levy's tables explain how other terminating impedances can be used. The four adaptors each have a different value of as defined in equations 5 and 6. The resistances of the ports (R1,R2) are equal respectively to the characteristic impedance of the section of transmission line or terminating impedance connected to that port as found from the procedure described above.

The appropriate capacitance ratios are then found as already described.

Figs. 5a, b and c show the characteristics of various low pass filters of different order constructed with MOS techniques according to the present invention. The vertical divisions are 10 dB and the horizontal divisions-are 500 Hz. In Fig. 5a the curve 55 was obtained from a third order filter with a cut-off frequency of 1.25 kHz and this is compared with a fifth order filter with identically designed cut-off indicated by the characteristic 56.

Fig. 5b compares the third order filter adding the characteristic 55 with a seventh order filter with a characteristic 57. In Fig. Sc the characteristics 56 and 57 are compared for the fifth and seventh order filters, respectively.

Using three-port adaptors any network comprising series and shunt reactance can be transformed using Kuroda transforms into a network comprising series and shunt reactances each separated by a unit element from each other reactance. This process is illustrated in Figs. 6 and 7. For example the band pass filter shown in Fig. 6 and comprising shunt capacitors 60 and 61, and a series inductor 62 can be transformed using Kuroda transforms to the filter shown in Fig. 7. In this transformation while the source impedance 63 remains at 1 ohm the load impedance changes from 1 ohm to another value which is given below. The transformed network (Fig. 7) comprises unit elements 65 to 69 separating capacitors 70, 73 and 74 and inductors 71, 72 and 75. Resistances 77 and 78 are the source resistance Rs and the load resistance Rp.

To construct the network of Fig. 7, each shunt reactance is replaced by a three-port parallel adaptor with a unit element so connected at one-port that it represents either a shunt capacitance or a shunt inductance. For example in the flow diagram of Fig. 8 which is equivalent to the circuit diagram of Fig. 7, a three-port parallel adaptor 80 represents the capacitor 70 since is has a unit element 81 connected at its third port, and a parallel three-port adaptor 82 represents the inductor 71 since it has a unit element 83 connected at its third port but with an inversion, represented by the symbol - 1, at the terminal 84. The unit element 65 is represented by delays 85 and 86 each having a duration of half a unit delay.Similarly, series adaptors 87 and 88 represent the inductor 72 and capacitor 73, respectively, and the parallel adaptors 89 and 90 represent the shunt capacitor 74 and the shunt inductor 75.

The implementation of a parallel adaptor cell to solve equations 10, 11 and 1 2 is now described in connection with Fig. 9. In this figure the letters a and b are followed by a single subscript denoting the port at which the signal occurs. The adaptor cell employs a number of switches operated in a two phase mode. Those switches which are closed during clock phases "one" are shown with a plain moving arm while those switches which are closed during clock phases "two" are shown with an arrow on the moving arm. Clock phases one and two alternate. During clock phase one capacitors C1, C2 and C3 become charged to the input voltages a1, a2 and a3 respectively. In addition capacitor C4 becomes charged to the voltage a1 - a2 and a capacitor C5 becomes charged to the voltage a2 - a3. In phase two the capacitors C1, C2 and C3 are connected in parallel and therefore the voltage V0 which appears on a line 91 is given by: - C, C2 C3 VO= a1 + a2 + as CT CT CT where C1, C2 and C3 are the capacities of the capacitors C1, C2 and C3, respectively, and CT = C1 + C2 + C3.

C, If = (a1 - 1), CT C2 = &alpha;2, and CT C3 = a3 CT the output voltage V0 across the three capacitors C1, C2 and C3 is the solution to equation 10 and is therefore employed in phase two as the output signal b,.

By equation 11 the output signal b2 = b, + a1 - a2 and while b, appears on the line 91, a1 - a2 appears across capacitor C4. Thus in phase two the signal b2 appears at an electrode 92 of the capacitor C4. Similarly the output signal for b3 is the sum of the voltage on line 91 and the voltage across the capacitor C5.

Buffer amplifiers 93 and 94 are provided to output the signals b, and b2 and a similar buffer amplifier would be to output the signal b3 but as is described in the next paragraph the required buffer 95 appears in a feedback path between the terminals of the third port.

In order to provide an adaptor which represents a capacitor the output signal b3 is fed back as input signal a3 by way of a delay 81 (see Fig. 8). The pairs of delays T/2, corresponding to unit elements, are incorporated in the adaptor shown in Fig. 9 by means of the two phase operation of switches. Thus the output signal b, does not appear until a time T/2 after the input signal a,.

Half the delay T, required by the delay circuit 81, has therefore been provided by the time the signal b3 appears and another delay of T/2 is provided by switches 96 and 97. The output signal b3 charges a capacitor C6 by way of the buffer amplifier 95 and the switch 97 during clock phases two and the voltage across the capacitor C6 is applied as input signal a3 during phase one by way of the switch 96 and the buffer amplifier 95. As will be described later when it is necessary to provide a parallel adaptor representing an inductor arrangements are made to invert signals passing through the feedback network.

An example of a parallel adaptor to connect a capacitor of value 1 Farad into a filter is now given.

The input and output port resistances in this example are chosen to be Rin = 0.5 ohms and Rout = 1.8 ohms. Thus R, = 0.5 ; R2 = 1.8 ; R3 = 1.0 From equations 9 a, = (9/8); a2=(S/16) ; a3=(9/16) Then from equation 10 b, =(1/8)a, + (5/ 16)a2 + (9/ 16)a3 let C1 = C the capacitors, then required in the circuit of Fig. 9 are C1 = C ; C2 = (a2/a,)C; C3 = (a3/a1)C or Cl = C; C2=(5/18)C; C3=(1/2)C As has been mentioned it is difficult to connect a mixture of series and parallel adaptors and for this reason the series adaptors 87 and 88 of Fig. 8 are transformed into parallel adaptors according to the explanation already given.This transformation is summarised in Fig. 10 where a series adaptor 99 and an equivalent parallel adaptor 100 are shown. Each adaptor contains a symbol denoting its type. Two pairs of scaling factors and three inversions are involved. The first pair of scaling factors Y and 1 /Y at the third port are self-cancelling and the second pair X and 1 /X simply affect the magnitudes of the signals a2 and b2 of the second port and can be treated as part of an overall filter loss or compensated by amplification. Note that in Fig. 10 X = a,/a2 and Y = a,/a3. The three inversions are achieved by inverting the signals a1, a2 and a3. A convenient way of inverting these input signals is illustrated below.

An implementation of the filter shown in Figs. 6 and 7 is now described. In this filter the capacitors 60 and 61 each equal 1.189469 Farads and the inductance 62 equals 1.154193 Henrys. By transforming to a band pass filter and applying the Kuroda transforms the reference filter becomes as shown in Fig. 7 with the following element values: - Resistor 77 = 1.0 ohms Capacitor 70 = 2.961656 Farads ; Unit element 65=1.036667 ohms Inductor 71 = 0.393637 Henrys; Unit element 66=0.081604 ohms Inductor 72 = 0.944866 Henrys; Unit element 67 = 0.481835 ohms Capacitor 73 = 1.626329 Farads ; Unit element 68 = 1.285518 ohms Capacitor 74 = 0.306396 Farads ; Unit element 69 = 0.635412 ohms Inductor 75 = 3.450482 Henry ;Resistor 78 = 0.536597 ohms Note that the value of the load resistor, is not equal to one due to the Kuroda transforms.

This reference filter resulted in a wave filter having a flow diagram of the form shown in Fig.

8 with multipliers as set out in Table 1.

Table 1 Adaptor Number 1 a2 a3 80 0.405985 0.391626 1.202389 82 0.122420 1.555181 0.322399 87 0.108206 0.638909 1.252885 88 0.404524 1.079254 0.516223 89 0.585309 1.184152 0.230540 90 0.844486 1.000000 0.155514 Although the adaptors used to implement the filter are based on Fig. 9 they are in fact rather different because the value which is greater than one is different in each case.

The circuit of an adaptor cell corresponding to the adaptor 80 is shown in Fig. 11, the delays 85 and 86 being included in the cell. In Figure 11 (and Figures 1 2 to 1 6) the conventions relating to switches are the same as those in Fig. 9 and the capacitors are designated in the same way; that is the capacitors Cl, C2 and C3 receive the input signals a,, a2 and a3, respectively, while the capacitors C4 and C5 accumulate the signal differences required in forming the output signals b, and b2.

Since a3 is greater than one in the adaptor 80 equations 10, 11 and 1 2 are re-written as follows: - b3 = (a3 - 1)a3 + a2a2 + a2a2 + a1a1 equation 14 b2 = b3 + a3a2 equation 15 b, = b3 + a3 - a1 equation 16, where subscripts relating to the adaptor cell designation are omitted. In clock phase one capacitors C1 and C2 receive signals corresponding to input signals a" and a21. As is explained later the capacitor C3 already holds the signal a3, at this time. The capacitor C4 holds a signal corresponding to the difference between the signals a3, and a" and similarly the capacitor C5 holds a signal corresponding to the difference between the signals a3, and a2,. Thus in clock phase two a signal corresponding to the equation 16 appears at a terminal 101 and a signal corresponding to equation 1 5 appears at a terminal 102.Since the capacitors Cl, C2 and C3 are connected in parallel in clock phase two the signal corresponding to equation 14 appears at a terminal 1 03. Since the signal b3, is fed back to form the signal a3, by way of the buffer amplifier 95, the signal a3, is stored on the capacitor C3 until it is required in the next clock phase one and at that time it is also applied to the capacitors C4 and C5.

An adaptor cell corresponding to the adaptor 82 is shown in Fig. 1 2 and is similar, except for the feedback network, to the adaptor shown in Fig. 9 with the following two exceptions: (a) phase one switches have become phase two switches and vice versa, this is to allow for the progressive connection of the adaptors along the filter; and (b) terminal numbers have changed because it is a3 which is greater than 1.

In view of the latter difference, equations 1 0, 11 and 1 2 are re-written as follows: - b3 = (a2 - 1)a2 + a,a, + a3a3 equation 17 b, = b2 + a2 - a1 equation 18 b3 = b2 + a2a3 equation 19.

By following the same kind of reasoning as given above in relation to Fig. 11 it will be seen that appropriate signals b,2, b22 and b32 are derived provided the action of the feedback network which is next described is taken into account.

Since the impedance represented by the adaptor cell of Fig. 1 2 is the inductor 71 the signal b33 has to be inverted before being applied as the signal a32. During clock phase one when the correct signal appears at a terminal 104 the capacitor C6 is charged with its upper electrode (as shown) in Fig. 1 2 earthed. However when this signal is read out for application as the signal a32 in the next clock phase two it is the lower terminal which is earthed. Thus the required inversion is achieved.

An adaptor cell corresponding to the series adaptor 87 takes the form of the modified parallel adaptor cell shown in Fig. 1 3. Since it is a3 which is greater than one equations 14, 1 5 and 1 6 are modified by inverting all input signals to give equations: - b3 = (a3 - 1 )a3 - a2a2 - a1a1 equation 20 b2 = b3 - a3 + a2 equation 21 b1 = b3 - a3 + a1 equation 22.

Inversion of the signal a33 is achieved by connecting one side of the capacitors C1, C2 and C3 to earth during phase one and the other side to earth during phase two. Thus in phase two the capacitors Cl, C2 and C3 hold inverted signals corresponding to the signals a12, a23 and a33, respectively. An inversion of the signals held in the capacitors C4 and CS is achieved by the connections used between terminals 105 and 106 in phase one and the common connection to a terminal 107. During clock phase one a rail 98 is earthed but during clock phase two it serves to parallel the capacitors C1, C2 and C3 and apply the parallel output voltage to a terminal 108 as is required by equation 20.The buffer amplifier 96 applies the signal b33 to one side of the capacitors C4 and C5 so that the signals required by equations 21 and 22 appear at terminals 109 and 110 during clock phase two. Since Fig. 13 represents the inductor 72 the signal appearing in clock phase two at the terminal 108 is inverted in the same way as is described in connection with Fig. 1 2 before being applied to the input of the amplifier 96 in the next clock phase one so that it appears at the terminal 107 as the signal a33.

Adaptor cells corresponding to the adaptors 88, 89 and 90 are shown in Fig. 14, 1 5 and 1 6 respectively. The adaptor of Fig. 14 having a2 greater than one implements equations 17, 1 8 and 1 9 but since it simulates a series adaptor signals a,4, a24 and a34 are inverted. Figs. 1 5 and 1 6 also calculate equations 17, 1 8 and 1 9 but without the inversion of the signals a,5, a25 and a35.Since Fig. 1 5 represents a capacitor there is no inversion between the signals b35 and a35 but in Fig. 1 6 which represents an inductor inversion between the signals b35 and a26 is provided. The operation of the adaptor cells of Figs. 14, 1 5 and 1 6 will be apparent from the explanation of the operation of the adaptor cells previously described.

In implementing the adaptor cells of Figs. 11 to 16, the buffers 93 and 94 may be multiplexed so reducing the total number of buffers required from 1 8 to 1 2.

In all of the adaptor cells the values of capacitors C4, C5 and C6 are not important and have been arbitrarily set at 1 on. In one embodiment, the buffers were formed from LF 356 operational amplifiers in voltage follower mode and CMOS 4066 quad switches were used in the circuit. The values of capacitors C1, C2 and C3 for each of the adaptors are given in Table 2. Since the value of the capacitor C2 in the adaptor 90 is zero, this capacitor is omitted from Fig. 16.

Table 2 Adaptor Number C1 (pF) C2 (pF) C3 (pF) 80 8200 7910 4088 82 1808 8200 4762 87 1389 8200 3246 88 6426 1259 8200 89 8200 2580 3230 90 8145 - 1500 In the filter described scaling factors have not been introduced into the circuit and therefore the filter exhibits attenuation within its pass band. The replacement of the series adaptor 87 by a modified parallel adaptor cell results in a loss of (0.638909/0.1.8206) and the replacement of the series adaptor 88 incurs a loss of (1.079254/0.404504). These figures are 1 /(a2/a1) for each of the two series adaptors. A further loss of /1 /0.535697 is due to the fact that the load resistor is no longer one ohm because of the use of Kuroda transforms. These losses result in the filter displaying an attenuation of 26.65 dB in the pass band.

The output of the filter may be amplified by 26.65 dB to compensate for these losses, and the resulting filter response is shown in Fig. 1 6. In a filter constructed as described it has been found that when the filter is clocked at 10 kHz, the measured response agrees very closely with the theoretical response for a Chebyshev band pass filter over the complete DC to Nyquist frequency range.

In other embodiments of the three-port filters described, dynamic range can be increased by building scaling factors into the filter.

From the description of specific embodiments of the invention given above, it will be appreciated that the invention can be put into practice in many different ways. For example the analogue computations carried out by adaptor cells can be performed in many different ways with many different configurations of components. In some arrangements it may be preferable to employ other numbers of switching phases, such as four or six, allowing the calculations to be carried out using more calculation steps and/or connecting portions of the circuit to ground at various parts of the calculation cycle in order to reduce the effect of parasitic capacitances.A four phase switching signal may comprise four different waveforms with leading edges spaced at 90 and each waveform having an "on" period of almost 90 . Similarly the leading edges of a six phase waveform are spaced at 60 , assuming a complete calculation cycle is carried out in 360".

A further way in which the present invention can be put into practice is by using adaptors having more than two or three ports.

In accordance with the invention may different types of filters may be provided, for example Butterworth, Chebyshev, elliptical and non-minimum phase filters can be constructed using different arrangements of adaptor cells.

Clearly filters according to the invention can be put into practice using discrete integrated circuits rather than forming a filter from a single specially designed integrated circuit. Other techniques of construction than MOS may also be used.

The filters made according to this invention may be made programmable by changing their coefficients which may be undertaken in the example given by varying the appropriate capacitor values by some means.

Claims (14)

1. An electrical filter circuit having a plurality of interconnected multiport adaptor cells, each adaptor cell comprising means for computing, using sampled analogue signals, output signals for the ports of that cell from input signals when applied to the ports of that cell, computation being carried out according to equations representing the calculation of reflected waves from the ports when incident waves are applied to the ports, and the constants of the equations, the number of adaptor cells and the interconnection of adaptor cells being selected to provide a required filter characteristic.

2. A filter circuit according to Claim 1 wherein in each adaptor cell the computing means is constructed to apply the calculated output signals to output terminals of the cell after a predetermined delay has occurred since incident signals were applied to the cell.

3. A filter circuit according to Claim 1 or 2 wherein in at least one adaptor cell having nports, computing means computes reflected signals (bk) for the klh port according to equations of the form bk = a0 -

where ak=2Gk/(G,+G2+G3+ - - - - - - - - - - +G) Gk = 1 /Rk, and R1 is the resistance of the ith port.

4. A filter circuit according to Claim 1, 2 or 3 wherein in at least one adaptor cell having nports, the computing means computes reflected signals (bk) for the kth port according to equations of the form bk = ak - Pkao where

Pk = 2Rk/(R, + R2 + R3 + - - - - - - - - - - Rn) and Rk is the resistance of the kth port.

5. A filter circuit according to Claim 2, or Claim 3 or 4 insofar as dependent on Claim 2, wherein each adaptor cell comprises a plurality of capacitors interconnected by a plurality of groups of switch means, the switch means of each group being controlled to conduct together, and the groups being so controlled that conduction by the switch means in the groups occurs in a repeating sequence of groups, the operations of addition, subtraction and multiplication for computing output signals being carried out by summing the voltages across at least two of the capacitors, subtracting the voltages across at least two of the capacitors and transferring charged between at least two of the capacitors, respectively.

6. A filter circuit according to any preceding claim comprising a series of two-port adaptor cells having first and second ports in which the second port of each cell is coupled to the first port of the next cell in the series, except for the first cell in the series where the first port is coupled to the input of the filter circuit and the last cell in the series where the second port is coupled to the output of the filter circuit, the computing means of each cell computing reflected signals b, and b2 for the first and second ports, respectively, of that cell from incident signals a, and a2 when applied to the first and second ports, respectively, of that cell according to the equations b, = a2 + a(a2 - a1) and b2 = a1 + a(a2 - a1), the constant a and the number of adaptor cells in the said series being selected to provide a required filter characteristic.

7. A filter circuit according to Claim 6 wherein in order to calculate the signal b, at least one adaptor cell comprises first switching means controlled by a switch control circuit to apply an input voltage appearing at one input terminal of the cell to a first capacitor in a first switching interval, second switching means controlled by the switch control circuit to apply both the said input voltage and a second input voltage appearing at the other input terminal to a second capacitor to form the difference between these voltages across the second capacitor in the first or a second switching interval, third switching means controlled by the switch control circuit to couple the second capacitor to a third capacitor in a further switching interval, the third capacitor having a capacity which is y times that of the second 1-a capacity. where y = , and the third capacitor being coupled in series with the first a capacitor with the result that the voltage across the series combination so formed is equal to the voltage at the said one input terminal plus a times the difference between the input voltage at the said other input terminal and that at the said one input terminal, and the signal b2 being in operation also calculated using capacitors and switching means.

8. A filter circuit according to Claim 7 wherein at least some of the capacitors and switching means are common to the calculation of both the signal b, and the signal b2.

9. A filter circuit according to any of Claims 1 to 3 or Claim 5 insofar as dependent on any of Claims 1 to 3, comprising a series of three-port adaptor cells having first and second ports in which the second port of each cell is coupled to the first port of the next cell in the series, except for the first cell in the series where the first port is coupled to the input of the filter circuit and the last cell in the series where the second port is coupled to the output of the filter circuit, the third port of each cell being connected to a respective feedback network for feeding the signal reflected from the third port back as the incident signal to the third port, and thecomputing means of each cell computing reflected signals b,, b2 and b3 for the first, second and third ports, respectively, of that cell according to the equations b1 = (a1 - 1 )a1 + a2a2 + a3a3 b2 = b1 + a1 - a3 b3 = b1 + a1 - a3, where a, is greater than one, the constants a,. a2 and a3, the number of adaptor cells in the said series, and the feedback networks being selected to provide a required filter characteristic.

10. A filter circuit according to Claim 9 wherein each adaptor cell and its associated feedback network represents one component in a theoretical filter derived from a prototype discrete-component filter.

11. A filter circuit according to Claim 9 or 10 wherein at least one adaptor cell comprises first, second and third capacitors arranged to be charged to voltages appearing at input terminals of the first, second and third ports, respectively, of that cell during first phases of two alternate clock phases, fourth and fifth capacitors arranged to be charged to respective differences between voltages appearing at predetermined pairs of the said input terminals during the first clock phases, the first, second and third capacitors being arranged to be connected in parallel during second clock phases, and to an output terminal of a first of the ports, the fourth and fifth capacitors being arranged to be respectively connected in series with the parallel connected first, second and third capacitors during the second clock phases, and output terminals of a second and a third of the ports being connected, during the second clock phases, to receive voltages representative of the combined voltages across the fourth capacitor and the parallel connected capacitors, and the fifth capacitor and the parallel connected capacitors, respectively.

1 2. A filter circuit according to Claim 9, 10 or 11 wherein at least one of the feedback networks comprises a storage capacitor connected to be charged during first phases of two alternate clock phases to the voltage at an output terminal of the third port of the adaptor cell to which the network is connected, and an input terminal of the third port of the adaptor cell to which the network is connected being connected to receive the voltage across the storage capacitor during second clock phases.

1 3. A filter circuit according to any of Claims 9 to 12 wherein at least one adaptor cell represents an inductor and the feedback network associated with that cell inverts the signal fed back before it is received by the input terminal of the third port of that cell.

14. A filter circuit according to any of Claims 9 to 1 3 wherein each adaptor cell is constructed to compute the equations of a parallel adaptor but at least one adaptor cell is connected to invert incident signals to all ports in order to cause that adaptor cell to represent a series adaptor.

1 5. A method of filtering electrical signals using a plurality of calculation stages each of which corresponds to a multiport adaptor cell, the method comprising calculating, using sampled analogue signals, for each said stage, output signals for the ports of that stage from input signa's when applied to the ports of that stage, the calculation being carried out according to equations representing the reflected waves from the ports when incident waves are applied to the ports. and the constants of the equations, the number of adaptor stages and the selection of output signals for use after a predetermined delay as input signals to other stages being arranged to provide a required filter characteristic.

1 6. A filter circuit substantially as hereinbefore described with reference to, and as shown in, Fig. 2. or Figs. 2 and 3, or Figs. 2 and 4 of the accompanying drawings.

1 7. A filter circuit substantially as hereinbefore described with reference to Figs. 7 to 1 6 of the accompanying drawings.

1 8. A filter circuit substantially as hereinbefore described with reference to, and as shown in, Figs. 11 to 1 6 of the accompanying drawings.