GB2087694A - Electric circuit arrangement for digital data transmission systems - Google Patents

Abstract

In a receiver arrangement for a quadrature phase-shift digital data transmission system data timing signals are derived from transitions occurring during predetermined data signal sequences, in one stream of received data signals only when these sequences coincide with other predetermined sequences in the other stream of signals.

Description

SPECIFICATION Electric circuit arrangements for digital data trans mission systems The present invention relates to digital data transmission systems.

In known quadrature phase-shift digital data transmission systems data timing or clock signals are derived in a receiver arrangement by forming pulses in response to all transitions in the incoming data streams and phase-locking a local oscillator to these pulses. In reduced-bandwidth transmission systems, particularly under conditions of multipath fading, the received signals can be so degr-aded that transitions occur almost randomly in time, and if a conventional clock extraction scheme were used the phase lock loop would not hold lock.

According to one aspect of the present invention in a receiver arrangement for a quadrature phase shift digital data transmission system comprising quadrature phase detectors for deriving respective streams of digital data signals from modulated sign als received by said receiver arrangement, there are provided means to derive data timing signals only from predetermined sequences of data signal values occurring in said streams of digital data signals.

Preferably said means is arranged to derive the data timing signals, or clock signals, in response to one or more predetermined sequences in one of said streams coinciding with one or more predetermined sequences in the other of said streams.

According to another aspect of the present inven tion in a receiver arrangement for a quadrature phase-shift digital data transmission system com prising quadrature phase detectors, an adaptive equalising regenerator for regenerating digital data signals detected by said detectors, and means selectively to add incremental values to the output signals from the respective detectors before said output signals are applied to said regenerator in depen dence upon the value or values of one or more preceding digits, there are provided means responsive to a predetermined sequence of data signal values occurring in the regenerated digital data signals to select one or more signal value transitions in the corresponding sequence of output signals from one of said detectors, and means to derive data timing signals only from said selected one or more signal value transitions.

Preferably said signal value transitions are detected by a threshold detector having as a refer ence a signal level dependent upon one of said incremental values which is selectively added to the output signals from said respective one of the detectors and which is derived at least in part from regen erated data signals from the other of said detectors.

A receiver arrangement for a digital data transmis sion system, the arrangement including an electric circuit arrangement in accordance with the present invention, will now be described by way of example with reference to the accompanying drawings, of which: Figure 1 shows part of the receiver arrangement schematically, Figures 2,3, 5, 6 and 7 show parts of the receiver arrangement in greater detail, and Figure 4 shows voltage waveforms illustrating the operation of part of the receiver arrangement.

Referring first to Figure 1, the receiver arrangement comprises a receiver head and down-changer 1 which is arranged to receive phase-shift modulated radio frequency signals and to apply corresponding intermediate frequency signals to a pair of phase detectors 2 and 3. Local oscillator signals at the intermediate frequency are applied in quadrature to the two detectors from a voltage-controlled oscillator 4, there being for example a ninety degree phase shift circuit 5 in the path from the oscillator 4 to the detector 3.

Output signals from the phase detectors 2 and 3 are applied by way of respective low-pass filters 6 and 7 to a two-symbol cross-coupled adaptive equalising regenerator 8, which provides two streams of regenerated digits on paths 9 and 10 and a phase control voltage for the oscillator 4 by way of a differential amplifier 11 and a low-pass filter 12.

Referring now to Figure 2, which shows effectively half of the regenerator 8, signals from, say, the phase detector 2 are applied by way of the filter 6 and a buffer amplifier 13 to a transmission path 14, which is connected in common to respective inputs of an upperthreshold detector 15, a lowerthreshold detector 16 and a main threshold detector 17. The signals on the path 14 are not in general of ideal rectangular waveform, and the output decisions of the threshold detectors 15,16 and 17 are entered into respective bistable circuits 18, 19 and 20 at approximately the midpoints of the received data digit periods under the control of timing signals or clock signals derived from, say, transitions in the signals on the path 14.An output from the bistable circuit 20 is passed to the path 9, while an output from a corresponding bistable circuit (not shown) in the other half of the regenerator 8 is passed to the path 10 (Figure 1).

Connected to the transmission path 14 are four current switches 21 to 24 which are arranged to apply to the line 14 currents of respective values dependent upon weighting signals applied to the switches 21 to 24 over paths 25 to 28. The current values are also dependent respectively on outputs from the bistable circuit 20, a further bistable circuit 29 and outputs from corresponding bistable circuits (not shown) in the other half of the regenerator 8.

The bistable circuits 20 and 29 effectively store the values of the two digits preceding that present on the path 14 at any given time.

Reference voltages for the threshold detectors 15, 16 and 17 are set up in a circuit 30, those for the detectors 15 and 16 having superimposed on them antiphase triangular waveforms from a generator 31.

These triangular waveforms enable logic circuits (not shown) receiving signals from the threshold cir cuits 15, 16 and 17, and the corresponding circuits in the other half (not shown) of the regenerator 8, to adapt the mean values of the reference or threshold voltages set up in the circuit 30 to suit the amplitudes of the signals on the path 14, and also to adapt the values of the weighting signals applied to the current switches 21 to 24. In this way the signal levels on the path 14 and the threshold voltages are arranged to vary so that the received data digits are equalised and regenerated accurately.

Referring to Figure 3, to derive a measure of a particular contribution to the inter-symbol degradation of each data digit stream, correlations are made between the appropriate delayed digit signal sequences and the degraded signals. In this way the various interference contributions may be separately determined. Positive and negative interferences produce corresponding effects on the digital sequence at the output of say, the detector 15, and the output of this detector is correlated digitally in a circuit40 with each of the interfering sequences, (for example, with the main signal delayed by one symbol period, from the output of the bistable circuit 20, in which case intersymbol interference from the previous bit is measured).The output of the correlator 40 is converted into a constant amplitude bipolar signal and used via a low-pass filter (not shown) and a high-gain amplifier (not shown) as the weighting signal for a respective one of the switches 21 to 24.

The triangular waveform sweep voltage superim posed on the upper and lower decision reference voltages enables, say, the mean levels of the respective bipolar signals to be made proportional to the departure of the degraded signals from the respec tive threshold voltages, at least over a range of levels determined by the amplitude of the triangular waveform.

Referring now to Figure 4, when the phase of the local oscillator signals is substantially correct the two data streams are correctly equalised as shown in waveforms 32 and 33, where the dashed lines 34,35 and 36 represent respectively the upper, main and lowerthreshold voltages. If the local oscillator phase is incorrect in either sense there is a degree of crosstalk between the data streams such that the waveform 33 say becomes distorted in one or other sense as shown by waveforms 37 and 38.

To derive a phase correcting voltage from these waveforms a logic function L is developed by means of a logic circuit arrangement 39 such that L = {UB. M8 + LB MB) (3MA where the terms M,, MB, UB and L8 have the value "1" when the signal values applied to the respective threshold circuits are above the respective main thresholds of the A and B channels and the upper and lower thresholds of the B channel respectively, and the operators ".", "+" and "' are logic "AND, "OR" and "Exclusive OR" respectively.

By inspection it will be seen that the function L has the value"0" continuously for the waveform 37 and the value "1" continuously for the waveform 38.

For lesser phase errors than those represented by the waveforms 37 and 38 the triangular waveforms superimposed on the threshold voltages 34 and 36 have the effect of producing alternating values for L such that the mean value of this function varies progressively between the two extremes over a range of phase errors centred on the correct phase.

Corresponding logic functions L developed in the two halves of the regenerator 8 are applied to the differential amplifier 11 to derive the phase control voltageforthe local oscillator4.

Referring now to Figure 5, which shows in detail one of the current switches 21 to 24, for example the switch 24, signals representing the value of the digit last received and its inverse are applied from the bistable circuit 20 (Figure 2) to inputs 41 and 42. By means of these digit value signals one or other of two long-tail pair switching circuits 43 and 44 is arranged to connect a respective path 45 or 46 to the path 14, in dependence upon whether the last received digit was a one or a zero, the other path 45 or 46 then being connected to a 6 volt supply line.

A substantially constant current from a source 47 is split between the two paths 45 and 46 by a longtail pair differential amplifier circuit 48 in dependence upon the value of the weighting signal applied over the path 28.

By means of this circuit a current can be effectively added or subtracted from the incoming signal on the path 14 in dependence upon whether the last received digit was a one or a zero, the current having any negative or positive value over a range of values in dependence upon the weighting signal on the path 28.Thus, denoting the currents in the paths 45 and 46 as 1, and 12 respectively and the constant current from the source 47 as I,:- Ii + 12 = lo Writing: Ii = 2 (11 + 12) + 2 (1112) it can be seen that: Ii = +2.1(11-12) Similarly: 12 =21lo21(l1 - 12) Thus there is a constant standing current of-'-lO flowing in the path 14 by way of the switching circuits 43 and 44 with o -12) being added to this standing current when the signal at input 41 is a zero and being subtracted from this standing current when the signal at input 41 is a one.It can be seen that the current difference (li - 12) will be dependent upon the weighting signal on the input path 28.

The transistors used in the circuit arrangement shown in Figure 5 are all N-P-N transistors, resulting in fast switching and ease of integration.

Referring again to Figure 1 clock signals are extracted from transitions occurring in the unregenerated data signals from the output of the filter 6, these transitions being detected by a limiting amp lifier 49 when the instantaneous data signal value exceeds a threshold voltage applied to the amplifier 49 over a path 50. The transitions are converted into pulses in a converter arrangement 51, shown schematically in Figure 6, only when particular data signal sequences occur in the regenerated signals on the paths 9 and 10, as detected by a gating pattern selector 52, shown schematically in Figure 7.

Referring to Figure 7, regenerated signals on the paths 9 and 10 are applied at X and Y respectively to respective series of bistable circuits 53 and 54, out puts of which are applied by way of gates 55 and 56 to a further bistable circuit 57. The bistable circuit 57 is arranged to be set only upon the occurrence of a sequence of digit values of either 0001 or 0011 on the path 9 coincidentally with either of the sequences 0000 or 1000 on the path 10.

Referring to Figure 6 the convertor 51 is arranged to give a pulse signal output on a path 58, of a pulse length determined by a delay circuit 59, in response to the 0 to 1 transition in the sequence 0001 or 0011 detected by the amplifier 49 in the corresponding data signal sequence at the output of the filter 6, a delay circuit 60 being utilised to match the delays introduced by the regenerator 8. Each transition in this data signal sequence is applied by the amplifier 49 to the path 61 of the convertor 51, but only those selected by a signal on an input path 62 when the ioistable circuit 57 (Figure 7) is set are arranged to provide an output pulse on the path 58. These output pulses provide the reference timing signals for a phase lock loop clock signal generator.

During multipath fade conditions the intersymbol interference from the other data stream effectively shifts the D.C. level of the signals at the output of the filter 6. This shift in level is approximately proportional to the value of the weighting signal selectively applied to the one stream of data signals in dependence upon the value of the preceding digit in the other stream of data signals. Hence the timing extraction performance is improved by making the threshold voltage on the path 50 (Figure 1) dependent upon the value of this particular weighting signal.

Claims (6)

1. A receiver arrangement for a quadrature phase-shift digital data transmission system comprising quadrature phase detectors for deriving respective streams of digital data signals from modulated signals received by said receiver arrangement, wherein there are provided means to derive data timing signals only from predetermined sequences of data signal values occurring in said streams of digital data signals.

2. A receiver arrangement in accordance with Claim 1 wherein said means is arranged to derive the data timing signals, or clock signals, in response to one or more predetermined sequences in one of said streams coinciding with one or more predetermined sequences in the other of said streams.

3. A receiver arrangement for a quadrature 'phase-shift digital data transmission system comprising quadrature phase detectors, an adaptive equalising regeneratorforregenerating digital data signals detected by said detectors, and means selectively to add incremental values to the output signals from the respective detectors before said output signals are applied to said regenerator in dependence upon the value or values of one or more preceding digits, wherein there are provided means responsive to a predetermined sequence of data signal values occurring in the regenerated digital data signals to select one or more signal value trans itions in the corresponding sequence of output signalps from one of said detectors, and means to derive data timing signals only from said selected one or more signal value transitions.

4. A receiver arrangement in accordance with Claim 3 wherein said signal value transitions are detected by a threshold detector having as a reference a signal level dependent upon one of said incremental values which is selectively added to the output signals from said respective one of the detectors and which is derived at least in part from regenerated data signals from the other of said detectors.

5. A receiver arrangement in accordance with any preceding claim wherein said data timing signals are derived only from the occurrence of the data signal values 0001 or 0011 in one sequence coincidentally with either 0000 or 1000 in the other sequence of data signal values.

6. A receiver arrangement for a quadrature phase-shift digital data transmission system including means to derive data timing signals substantially as hereinbefore described with reference to Figures 1,6 and 7 of the accompanying drawings.