GB2086110A

GB2086110A - Opto-electronic Apparatus for Reading Information Contained in an Information Carrier

Info

Publication number: GB2086110A
Application number: GB8028139A
Authority: GB
Original assignee: Interlock Sicherheitssysteme GmbH; Interflex Datensysteme GmbH
Current assignee: Interlock Sicherheitssysteme GmbH; Interflex Datensysteme GmbH
Priority date: 1977-10-20
Filing date: 1978-10-20
Publication date: 1982-05-06
Also published as: JPS54102832A; FR2406854A1; GB2009477A; FR2406854B1; IT7828974A0; IT1099424B; GB2009477B; JPS627586B2; GB2086110B

Abstract

An opto-electronic apparatus is provided for reading data represented on a carrier as patterns of areas which are transparent or opaque to radiation. The apparatus includes at least one reading assembly comprising a radiation source and associated receiver. The carrier is guided through the reading assembly or assemblies for reading thereby, the outputs of the reading assemblies being connected to electronic data processing means. There is provided means for operating the reading assemblies in two different modes. In a first standby mode, only one reading assembly is supplied at intervals with short low power pulses. In a second reading mode, all the reading assemblies receives high power pulses adjusted to the maximum reading speed. The lower power pulses occur at a lower frequency than the high power pulses and at such a frequency that the assemblies can be switched into the high power mode before the data patterns have reached the reading assembly.

Description

1 GB 2 086 110 A 1

SPECIFICATION Opto-electronic Apparatus for Reading Information Contained in an Information Carrier

The invention relates to an opto-electronic information reader. More particularly, the invention relates to an opto-electronic apparatus for reading preferably coded information placed on an information carrier. In use, the information carrier is moved relative to reading heads or sensors. A particular field of application is the reading of coded cards having cover plates that are transparent substantially only to infrared light and between which are placed code sheets that define a sequence of alternatingly bright and dark, i.e. transparent and non-transparent, regions. The apparatus further includes at least one light source and a corresponding light receiver as well as electronic processor circuits.

An opto-electronic apparatus for reading 85 information contained in an information carrier is described and claimed in our Patent Specification

No.2009477.

Information carriers, for example coded cards which contain invisible codes which are placed between only semi-transparent or weakly transparent cover sheets, require a substantial light intensity for correct reading. Accordingly, a suitable reader must have available to it a substantial amount of electric current, i.e., power.

On the other hand, coded cards of this type are very popular due to their substantial resistance to forging and are widely used as credit cards, checking account cards and personal identification cards. All known opto-electronic readers for reading these cards employ the full operating power both during standby operation as well as during the reading operation and thus require considerable operating power at all times.

They therefore must be supplied by a power 105 source of substantially infinite capacity, for example, the commercial power grid, and the light sources normally employed, i.e., light-emitting photodiodes, are required to produce the maximum light intensity continuously.

Accordingly, the known card readers are unsuitable for battery operation and, at the same time, have a relatively short operational lifetime.

According to the invention, there is provided an opto-electronic apparatus for reading data from a 115 data carrier that may be moved with respect to the apparatus for presentation thereto of the data which is represented by patterns of areas, each area being either transparent or opaque to the passage of radiation, the apparatus comprising at 120 least one reading assembly comprising a source of radiation and an associated receiver of radiation, means for guiding the data carrier relative to the at least one reading assembly so as to allow radiation from the source to pass through 125 the transparent ones of the pattern areas to be received by the at least one radiation receiver, electronic data processing means for evaluating the data on the data carrier, and means for operating the at least one reading assembly in at least two different operational modes, in a first of which only one of the at least one reading assemblies is supplied at intervals with short low power sensing pulses, and in a second of which all of the reading assemblies in the apparatus are provided with pulses adjusted to the maximum reading speed and having relatively high power for carrying out the reading operation, the frequency of said low power sensing pulses being less than that of the relative high power pulses and being such that in relation to the speed of movement of the data carrier the system can be switched into the high power reading mode prior to the moment the data patterns have reached the reading assembly.

A preferred opto-electronic apparatus for reading stored coded data can operate at a substantially lower power than the apparatus known in tlie art. A substantially greater lifetime of the reading head assembly than can be provided by any known reader can be achieved.

Such an information reader may be used with commonly available storage batteries acting as power sources.

The processing circuitry may be used in pulse operation both during standby and during the actual reading. Inasmush as no coordination is expected or takes place between the insertion speed of the information carrier and the clocked operation in the pulse mode, no errors can occur because various circuit elements enter a standby mode or operate in a loop mode.

The standby operation of the apparatus may be defined as that status when the reader is ready to operate but requires only a minimum standby power because only a simple circuit element, preferably only a single one of a plurality of reader heads, is actually operating and even this single head is operating only when relatively short and low power sensing pulses are present. Accordingly, the entire standby power is very low. On the other hand, even during the actual reading operation, the reading heads and possibly even the entire electronic supply and processing circuits also operate only in a pulsed mode, at a somewhat higher operating frequency than during standby operation and with a substantially higher pulse power, permitting the operation of lightemitting diodes with substantially increased current and thus increased light intensity. Inasmuch as pulsed operation during the actual reading of the information carrier is possible, and the information carrier itself is provided with a clock generating track, it is possible to dispense with a continuous insertion mechanism for the card carrier. The clocking of the apparatus can be provided by alternatingly light and dark spaces in a clock track which is interrogated by associated reading heads whose output signals provide a criterion for correct or incorrect insertion of the information carrier.

The power consumption of the apparatus may be still further reduced by switching off any power-intensive portions of the circuit during 2 GB 2 086 110 A 2 standby operation and to operate the circuit during the reading of the data with clock pulses whose length need be only a fraction of the length of the reading pulses.

The switchover from standby operation to 70 reading operation may take place automatically in dependence on the nonoccurrence of a sensor pulse at at least one of the reading heads.

Accordingly, the apparatus can switch automatically from standby operation to reading operation as soon as one of the reading heads which is operated intermittently detects a light to-dark transition, i.e. as soon as a coded card or information carrier is inserted into the reader.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a front elevational view of a preferred card reader; Figure 2 is a top view of the apparatus of 85 Figure 1; Figure 3 is a side view of the apparatus of Figure 1; Figure 4 is a block circuit diagram of a first exemplary embodiment of the invention; Figure 5 is a partial illustration of an information carrier, embodied as a code-carrying card with data and clock tracks; Figure 6 is a detailed circuit diagram of some of the elements shown as blocks in Figure 4; Figure 7 is a second detailed circuit diagram of further circuit elements shown as blocks in Figure 4; Figure 8 is a pulse timing diagram illustrating the pulse trains generated by a multi-phase oscillator and other pulse trains when an information carrier is present within the apparatus; Figure 9 is a pulse timing diagram similar to that of Figure 8 when an information carrier is present in the apparatus; Figure 10 illustrates a second exemplary embodiment of an information carrier having selfclocking code tracks; Figure 11 is a block diagram of part of a 110 processor circuit associated with the information carrier of Figure 10; and Figure 12 is a block circuit diagram of the whole of an embodiment of a processor circuit, including the part shown in Fig. 11, associated with the information carrier of Figure 10 for pulsed operation.

The overall construction of the preferred information reader includes a frontal frame 1 having a slot 2 for receiving an information 120 carrier, for example a coded card, and equipped with lower and lateral guide surfaces 3 and 4 for ensuring the correct insertion and withdrawal of the coded card. An error indicated signal lamp 5 is provided to alert a user to faulty operation of the apparatus. The rear portion of the card reader is provided with a protective housing 6 which holds a total of 4 printed circuit boards 7, 8, 9 and 10, which are fastened within the frontal frame 1 in such a manner as to lie in a plane inclined by 130 approximately 51 from the plane defined by the insertion slot 2. The inclination of the circuit boards is provided to prevent the intrusion of light from the outside into the interior of the card guide channel formed by the interior circuit boards 8 and 9. Figure 3 further illustrates how the apparatus may be mounted in a bezel plate 11 of some frame or housing, not further shown.

The information carrier whose information is to be read out by the preferred apparatus is illustrated in one exemplary embodiment in Figure 5 as a coded card which may consist, for example, of three substantially parallel and permanently joined foils. The upper and lower foils consist preferably of a material that is transparent only to infrared light and is of such a strength as to give to the coded card the required stiffness and rigidity. The central foil constitutes the actual code or data carrier and it is made of an opaque material in which the data or codes are formed by sequential rectangular openings disposed in a particular pattern. The alternating bright and dark fields of the code track 21 constitute a clocking track, whereas the smaller rectangles in rows 22 and 23, in the present example 16 rectangles per track, constitute the actual information bits and represent particular binary words depending on their combination. It will be noted from Figure 5 that the individual openings 17, 18 and 19 in the clocking track are separated from another by a distance corresponding to their own width whereas the openings in the data track 22 are of such a width that two of such openings lie directly underneath each of the openings 17, 18, 19 while two adjacent of the smaller rectangles in the data track 22 come to lie underneath the opaque part of the clocking track 2 1. It will be further noted that the data bits of the second data track 23 are displaced with respect to those of the data track 22 by one-half width of one of the small data openings.

Shown schematically in Figure 5 are two datareading heads S and F whose separation in the long direction of the data and is seen to be unequal to the separation of alternating light and dark fields. In the present example, the separation is about one and a half time as large as the distance between adjacent clocking track openings. It will be appreciated that, when the coded card is inserted into the reader, there will be produced in the reading heads S and F two separate pulse trains of substantially rectangular shape but with a relative phase difference equal to one-half pulse width, provided that the insertion speed is uniform. By an examination of these two phase-shifted pulse trains in coordination with the data contained in the data tracks 22, 23, it is possible to distinguish correct card insertions from insertion which occurs too rapidly or too slowly or is, in some manner, excessively irregular.

Figure 4 is a block circuit diagram of the basic components of the data processing circuit, containing the electronic circuitry of the card reader which would be disposed on the printed 3 GB 2 086 110 A 3 circuit boards 7, 8, and 9. The blocks shown in Figure 4 constitute functionally associated circuit groups.

The card reader of the present exemplary embodiment is seen to include a total of four reading head assemblies, each consisting of a lightemitting photodlode and a light-sensitive phototransistor, and respectively labeled F,S,D and E. The outputs of these reading head assemblies are connected to a comparator 24 serving at the same time as an amplifier and including adjustable thresholds provided by a threshold switch 27. The comparator 24 is further engaged by an amplifier 28. All four of the light- emitting photodiodes in the four reading head assemblies are connected to a high power switch 26. Additionally, the light emitting diode associated with the reading head 5 is also connected to a low power switch 25 whose output signal also goes to the aforementioned threshold switch 27. The low and high power switches 25 and 26 are controlled by separate outputs of a pulse selection processor 33, the amplifier 28 being connected to the same output of that processor as is the low-power switch 25. Further included in the processor circuit of Fig. 4 is a multi-phase oscillator 29, a card recognition register 30, a status register 3 1, a synchronizing circuit 32, a clock register 34, a status counter 35, a status decoder 36, a program memory 37 for storing particular pulse sequences in the clocking track, a memory 38, a power switch 39 for the program memory 37, an error switch 40 for shutting off the program memory when a legitimate card is inserted erroneously or when an illegitimate card is inserted, a speed sensor 41 which senses the speed of insertion of the coded card and which activates the error switch 40 in association with one output of the processor 33, and a buffer 42 engaged by the status decoder 36 for the purpose of generating status signals and error signals.

The various pulse trains generated by the multiphase oscillator 29 serve as sensing and reading pulse trains as well as for clocking the system. It is the purpose of the pulse selecting processor 33 to use the pulse trains generated by the multi-phase oscillator 29 and to pass them on, according to the various operational states and according to a predetermined program, to the light-emitting diodes of the four reading heads as well as to the other circuit groups of the apparatus. The circuit 33 is controlled by the status register 31 which also engages the multi- phase oscillator and which is itself controlled by the card recognition register 30 and the status decoder 36. The input of the card recognition register 30 is connected firstly to the output of the comparator 24 associated with the reading head S which operates during standby operation as well as to one control output of the processor 33 which signalizes the fact that a coded card is present in the card reader. The status register 31 can distinguish between various states of the system, namely standby operation, card reading, card reading completed, as well as reading operation and error status.

The status counter 35 is also cycled by the multi-phase oscillator 29 via the processor 33 and its input is connected to the program storage 37 while its output is connected to the status decoder 36 and to the program storage 37. The timing or clocking track register 34 is connected at its input to the outputs of the comparator 24 associated with the clock track reading heads F and S and, at the same time, to the output of the processor 33 for the purpose of synchronizing or rastering while its output goes to the program storage circuit 37.

The stored information associated with a particular card reader is stored in the data memory 38 whose inputs are connected to the multi-phase oscillator 29 acting via the processor 33. These stored data are used for a comparison and/or identification with the data read from the information carrier, i. e., the coded card. The data stored on the coded cards in binary code is read by the two reading heads D and E and is fed to the data memory 38 for a comparison with the stored data.

The card reader described so far functions as follows. In standby operation, i.e., when no coded card is present in the card reader, the diode associated with the reading head S is supplied, for example, with pulses having a duration of 20 ms and an intensity of 10 mA. Depending on the application, the time between pulses can be relatively rapid so as to recognize the presence of an inserted card or can be relatively long but, in any case, of a duration which ensures that the duty cycle is substantially less than continuous operation. Each pulse also switches on the comparator-amplifier combination 24. When no coded card is present, the phototransistor associated with the reading head S receives the light pulse generated by the associated diode and generates a voltage which is at least two to three times as high as the threshold of the comparator. Accordingly, the comparator output associated with the reading head S switches over to indicate the condition "bright". The negative-going edge of this pulse triggers the card recognition register 30 indicating that no card is present. This whole cycle is repeated after the expiration of approximately 1 to 5 ms. The average current consumption or power consumption is very low because the circuitry is switched on only for a very short time. Furthermore, a capacitor connected to the power supply acts as a power reserve for providing the sensing pulses so that the power supply is required to provide only the average current which, depending on the duty cycle, may lie, for example between 150 ya and 1 mA. This very low power consumption makes it possible to use the card reader with batteries acting as power supplies.

When a coded card is inserted into the reader, the apparatus switches over automatically from standby operation to reading. The insertion of the coded card causes the next light pulse in the 4 GB 2 086 110 A 4 reading head S to be interrupted so that it cannot reach the phototransistor of the reading head S.

The card recognition register thus recognizes the presence of a coded card and switches over to the card-reading operation status at least when, for example, the negative-going edge of the pulse from the pulse selection processor 33 is also received. This triggers a pulse lasting approximately 20 ms which serves to apply relatively high reading power to the lightemitting diodes. As a consequence, all four of the light emitting diodes of the reading heads F, S, D, E are supplied with pulses of between 100 and 400 mA causing the emitted light intensity to be so high that it can pass through cards having a transparency of less than 1 percent. During the further insertion of the card, the phototransistors respond to the presence or absence of the opaque and transparent portion, i.e., the coded information in the central foil, and generate 85 appropriate pulse trains which are amplified by the comparator-amplifier combination 24. The clocking or timing pulses are applied to the timing track register 34 and are then fed to the program memory 37. The data track signals are fed into the data storage memory 38. The various negative-going edges of these pulse trains alter the logical states in the timing register 34 and they also actuate the status program in the program memory 37. On the basis of the received information, the program memory 37 makes a decision as to whether a proper and legitimate coded card was inserted. After the expiration of approximately 200 1As, the light pulses are repeated, beginning with a low-powered pulse applied via the low power switch 25 to the reading head S to check the presence or absence of a card. Subsequently, a high-powered pulse is applied to all four reading heads to read the code contained on the card. During the reading 105 operation, the power is turned on for approximately 10 percent of the time resulting in an overall power consumption of approximately mA. When the card is removed from the apparatus, the entire system returns to standby operation.

The program memory 37 contains the overall function and status program of the card reader.

The memory 37 receives the timing data read from the inserted card and compares it with the 115 stored system status data in the status counter which includes a sub-status register. When the physical position of the card is changed drastically, the program memory 37 writes a new status into the sub-status register of the status 120 counter 35. During each reading cycle, the program memory 37 needs to be turned on only for approximately 1 or 2 ps. During the reading operation its average power consumption is approximately 1.5 mA. Preferably, the status counter 3 5 and the sub-status register contained therein is embodied in CMOS-logic and thus stores data with very low power consumption.

This CMOS circuit is advantageously coupled with a PROM acting as the program memory 37 and embodied as a Schottky-type circuit which is turned on only for very short periods of time.

The status counter 35 and the sub-status register contained therein store the position of the card at all times so that changes in that position can be compared and processed. The PROM 37 compares the data of the changed position of the card with the stored data of the previous position and causes a phase shift of 901 to check if the card is being inserted or removed. The PROM 37 also decides if any return motion of the card during insertion is greater than an acceptable amount, in the present exemplary embodiment greater than 3 bits, which would constitute an error, and also if the card has been inserted beyond the previous point of insertion. The alternating occurrence of light and dark regions and the concurrent generation of logically high (1) or logically low (0) states at the reading heads F and S are checked to determine whether their sequence constitutes a further advance of the coded card in which case the read bits in the data tracks are stored in the memory 38. When the card is fully inserted, that status is recogniz ed as a "completely read" status and the high power pulse sequence is turned off. If the card is accidentally reversed beyond the acceptable amount prior to being fully inserted and before the reading operation is complete, the high powered pulses are also turned off and the error indicator is caused to indicate malfunction. Furthermore, the insertion speed is checked by the speed sensor 41. If the time elapsing between data bits is greater than 0.6 seconds, the system returns to low-power standby operation and indicates a malfunction. In both high power operation and error status Operation, a check is made to determine if the coded card is actually inserted and, when the card is removed, the entire system returns to standby status.

In the present exemplary embodiment, the system makes four checks with respect to the motion and direction of motion of the card for each change in the bright-dark pattern, thereby defining four linear reference points.

The preferred apparatus does not require continuous sensing of the data but only that the frequency of relatively short sensing pulses is definitely higher than the occurrence of observable light-dark patterns which could be generated during the most rapid insertion of a coded card. This periodic sensing of the moving light-dark patterns can be used to define light and dark states by the occurrence of two or more sequential light or dark signals.

Because the light-emitting diodes are turned on at full power only approximately 10 percent of the time, it is possible to apply a higher current to them when they are actually energized, resulting in a substantially higher light intensity and yet a very pronounced prolongation of life, for example approximately 10 years. At the same time, the overall energy consumption is reduced.

The detailed circuitry of the various block diagrams of Figure 4 will now be described in GB 2 086 110 A 5 connection with a description of their function 65 during operation of the apparatus.

The detailed circuit diagrams of the blocks shown in Figure 4 are given in Figures 6 and 7 where circuit elements constituting the functional blocks of Figure 4 are surrounded by dashed lines and carry the same reference numerals as in Figure 4.

A principal component of the-preferred apparatus is the multi-phase oscillator 29 shown in detail in Fig. 7 which serves to generate the 75 various pulse sequences illustrated in Figs. 8 and 9 which serve for the selective control and triggering of various circuit elements, for example the pulsed operation of the reading heads, etc., although the pulse trains A, B, C, D and E shown in Figs. 8 and 9 should be regarded as merely exemplary and subject to change according to particular requirements of a given apparatus. The major component of the multi-phase oscillator 29 illustrated in Fig. 7 is a cascade of any desired number of flip-flops, the output of each of which generates a particular one of the previously mentioned pulse trains. These flip-flops are combined with intermediate circuits 29a, 29b containing diodes which serve to cause time delays in the propagation of output pulses from one flip-flop to the next, depending on the sign of the edge of the pulse. In this way, and further due to the presence of the feedback lines 29c and 29d, a large variety of pulse train patterns may be generated. For example, the positive edge of the pulse train A, which is generated at the output of the first flip-flop 29e, rapidly triggers the subsequent flip-f lop 29f because the pulse passes quickly through the diode of the sub-circuit 29a, whereas the negative edge of the pulse train A resets the output pulse train B of the flip-flop 29f substantially later. Similar remarks apply to the generation of the pulse train C. The circuit loop is closed for the purpose of generating oscillations via the line 29d. In this manner, there are produced the pulse trains shown in Fig. 8, and these pulse patterns are repeated continuously when at least one of the sensing heads associated with the information carrier determines that no information carrier is present within the region of the reading heads. This determination is made as follows.

Timing Pattern in the Absence of a Coded Card As seen in Fig. 7, the B pulse train passes through the inverter 52 and the gate 53 to one input of the gate 50. The gate 50 also receives the pulse train A and the combination of these two pulses causes the generation of a short negative sensing pulsjN- at the point 54 which is applied to the input of a transistor 55, shown in 120 Fig. 6, which causes the activation of a selected light-emitting diode 111 associated with the reading head assembly S. The presence of a card in the reading slot would prevent the propagation of the light from the diode Ill to the associated phototransistor Ilia, thereby causing the subsequent comparator 56 to respond and to generate at the point 57 a card signal C which is fed to the D-input of a memory or f lip-flop 58 shown in the lower right portion of Fig. 7 at the point 57. The clock pulse train for the D-flip-flop 58 is the B pulse train from the inverter 52.

Accordingly, the Q-output of the flip-flop 58 carries a signal related to a logical 1 (in the present example) whereas it has a signal related to a logical 0 when the information carrier or coded card is absent.

It should be noted at this point that all of the logical states are merely exemplary indications and it is possible, as is well known to the person skilled in the art, to employ different logical relative switching states to obtain similar or identical overall functioning of the apparatus.

As seen in Fig. 8, approximately ha(f-way in the negative-going portion of the pulse trairi-N-, and as triggered by the edge of the pulse train T which is the inverted pulse train B, a test is made relative to the presence or absence of the information carrier. If this test is negative, i.e., no card is present, the gate 60 connected behind the last flip-flop 29g of the oscillator 29 remains blocked via the line 59 and the E pulse train remains zero as illustrated in Fig. 8. This cycle is repeated periodically as shown in Fig. 8 until the test for the presence of an information carrier finally becomes positive due to the insertion of a coded card.

Timing Signals When an Information Carrier is Present The various pulse trains which occur when a card carrier is present are shown in Fig. 9. Inaccordance with the above discussion, the presence of a card causes a short pulse 61 within the pulse sequence E which endures as long as the corresponding pulse in the D pulse train lasts. This short pulse 61 and the E pulses which are present when an information carrier is inserted, are fed via the rapid-return line 29c to cause an almost instantaneous switching back of the A pulses compared with the much longer duration of these A pulses as shown in Fig. 8 if the signal is returned via the integrating sub-circuit consisting of the resistor 62 and the capacitor 63. Furthermore, the switchover of thE-Q- output of the flip-flop 58 is passed via lines 64, 65 to the gate circuit 66 which thereby switches and_ causes the generation of the running pulses R which open the gates 67,68, pass the inverter 69 and generate the high power actuation pulses LED at the point 70 from the combination of the pulse trains A and ff. These pulses are received at the point 70 in Fig. 6 and are passed through the amplifier chain 71, 73 and the connecting line 74 to the remaining light-emitting diodes, 1, 11 and IV which constitute a part of the reading head system while the light-emitting diode III receives a high-powered reading pulse LED from the associated amplifier 72.

The above-mentioned rapid signal return shortens the A pulse also results in shortening the 6 GB 2 086 110 A 6 reading pulses LED whose associated pulse train is labeled P in Fig. 9.

Whenever a reading process is terminated, the entire cycle including the actuation of the diode III 5 with a first sensing pulse is repeated.

Only when the presence of an information carrier is sensed, do the diodes I-IV receive the high-powered reading pulses. The control pulse train for the diode III is labeled-N' in Fig. 9 and it is composed of the sensing puls_N_ of Fig. 8 and the later occurring reading pulse LED corresponding to the pulse train 1R.

In summary, the overall sequence of events is to sense the presence of an information carrier and subsequently to generate the high-powered reading pulses LED while at the same time switching to a higher operating frequency.

Activation of Circuit Components for the Reading Cycle When the overall circuit contains sub-groups or individual circuits which tend to consume 85 relatively high current, it is advantageous to activate these latter circuits only if the presence of an information carrier has been determined. In the present exemplary embodiment, such a circuit is the program memory 37 in Fig. 7 which is embodied in bipolar technology and thus requires considerably more current than the CMOS circuitry and this circuit is activated only when needed. As will be seen in the pulse timinj diagrams of Fig. 9, the reading pulse train 1 is composed of the pulses from the pulse trains A and C, which are fed via lines 76 and 77, respectively, to an AND gate 78 feeding a further AND gate 79 which releases the short reading pulses shown in Fig. 9 to the program storage only if its other input receives a signal indicating the presence of the information carrier from the information carrier indicating flip-flop 58. The PROM 37 is then activated by the amplifier 80. It will be appreciated that other power-intensive circuits might be actuated in this manner or that the actuating circuit can be omitted if the apparatus does not contain power-intensive circuit elements.

Read-out of Clock Information The illustration of Fig. 5 shows that the present exemplary embodiment, which is particularly suitable for dynamic pulsed reading, contains a separate clocking or timing track 21 associated with one or more data tracks 22, 23, etc. The exact number of clock tracks and data tracks is arbitrary, but the clock or timing track must be such as to yield enough usable alterations that each of the data bits present in the data tracks can actually be received by the reader. In the present exemplary embodiment of Fig. 5, only a single clock track is provided, which is read out by two reading heads, labeled F and S, respectively, in Figs. 5 and 6. The other two reading heads, designated D and E, respectively, are used for reading the data on the data tracks. The clock track system has two main tasks and these are 1. the release of the data tracks for reading, once a clear determination has been made that a new bit status has been obtained during the insertion of the information carrier; and 2. to prevent reading when the above condition is not met, i.e., if the last position defined by the clock track and the associated reading heads S and F and, possibly, by any intermediate memory, all these constituting a "clock generator", has not changed or if a retrograde motion has been determined. Each of the data bits present in the data tracks must be associated with a particular different clock track configuration, whereupon it is fed to the program memory 37, permitting the latter to read the associated bit or bits on the data tracks.

For the purpose of simplification, the exemplary embodiment shown in Fig. 5 has a clock track design formed from alternating bright and dark fields which, together with the disposition of two reading heads F and S whose distance from one another is not equal to the separation of light and dark fields, results in the generation of a four-valued so-called period of the overall clock generator. For this reason, it is possible to move the information carrier backward during the reading process by as many as three clock track values until a fourth identical value is obtained and the system must admit failure and switch over to a malfunction indication.

To illustrate these events, let it be assumed that a relative displacement takes place between the clock track heads F and S and the clock track 21. Two possible positions of the reading heads F and S are shown in the figure, one of these being drawn in solid circles and the other shown in dashed circles. If the passages of the edges of the light and dark fields over the heads are considered as timing events, one obtains the following four states which define a "period" of the clock generator.

Reading Heads F S 1 1 1 1. 0 0 0 1 a b a c it will be further seen from Fig. 5 that, for each one of these states of the clock generator, the data track reading heads D and E are placed squarely above a light field or a dark field of the bit pattern in the tracks 22 and 23. In the representation of Fig. 5, all of the data fields are shown to be bright, although it will be appreciated that, in reality, a usable bit pattern would normally have a different and essentially arbitrary distribution of light and dark fields.

7 GB 2 086 110 A 7 The pulse train C illustrated in Fig. 9 is used to generate an overall clock signal which is carried on line 85 in Fig. 7 to a point 86 which enters the circuit illustrated in Fig. 6 at a similar point 86 where it is applied to the clock inputs of two receiver flip-flops 87 and 88 which receive the output signals of comparator-amplifiers 89 and 56, associated, respectively, with the clock track reading heads F and S. The outputs 90 and 9 1, associated, respectively, with the Q outputs of the flip-flops 87 and 88, then carry clock track signals which are fed to inputs 1 and 2, respectively, of the program memory 37 illustrated in detail in Fig. 7.

Evaluation of Read-out Clock Track Information The valuation of the read-out clock track information is performed substantially by the previously mentioned program memory 37 and an associated status counter 35. For synchronized, 85 rastered operation, the 1 pulse train formed from the A and C pulse trains and available at the output of the gate 78 is used as a general stepping pulse train which is carried via a line 92 to the clock inputs 93 and 94 of bistable flip-flops 96 and 95 whose purpose will be described below and which is further carried on line 92 to the clock input CL of the status counter 35. The status counter 35 alters its content to the next higher level provided that its EP input receives an appropriate enabling pulse via the line 97. The dimensions of the status counter 35 are such as to correspond to the number of bits in the data track, i.e., in the present case 16 bits. The outputs Q1, Q2, Q3, and Q4 of the status counter 35 are used to transmit the contents of the status 100 counter 35 obtained by the stepping of the program memory 37 back into the latter memory 37 at appropriate address inputs 3, 4, 5 and 6.

This address corresponds to the next expected bit pattern in the clock track information if the information carrier is inserted still further into the apparatus for a continuation of the reading of the data. The clock track information is fed to the 45 inputs 1 and 2 of the program memory 37 from points 90 and 91 of the clock register 34 so that the program memory, i.e., the PROM 37, as it will be called below, waits for an appropriate coincidence and only thereafter will it provide 50 appropriate stepping signals, data receipt signals or malfunction signals at its outputs 9, 10, 11 and 115 12. In other words, the PROM generates a nominal value for the next to-be-expected reading head signala, b, c and d corresponding to the 55 aboveshown table and waits for this nominal value to be delivered to it by the status counter 120 35 in the form of an appropriate address. If this nominal combination does not appear at its inputs 1 and 2, the PROM 37 enters a holding status and 60 prevents the stepping of the status counter 35 by placing a disabling signal at the enabling input of 125 the status counter 35. Initially, let the case be considered in which a "proper", i. e., relatively uniform insertion of the information carrier is performed so that in the normal case the bit pattern generated from the four possible bit patterns of the clock track generator is present at the inputs 1 and 2 of the PROM 37, and that the PROM decides that a coincidence is occurring on the basis of the present address supplied by the status counter 35. In that case, its output 12 generates a shift signal which is fed to the D input of the synchronizing flip-flop 96 which receives the clock pulse through the line 93 for the purpose of rastering the information. The line 97 will then carry a shifting pulse S which is applied at 97 in Fig. 6 to the clock inputs CR of data registers 98, 99 which permit the data received from the comparators 100 and 10 1 associated with the reading heads D, E and which are present at the data inputs DR of the registers 98, 99 tb be admitted to these registers. The shifting signal S occurs only once, because, at the same time, the PROM 37 causes the status counter 35 to step up by one step over the line 97, so that the address is changed and a coincidence between the clock track information which may still be present and the new address no longer occurs.

Prevention of Reading During Retrograde or Irregular Motions of the Information Carrier It has already been noted that the four different states of which the clock track coding is capable permit the PROM 37 to allow as many as three changes of state during a reverse or retrograde motion of the information carrier and to remember them without causing the entire reading system to enter the failure or malfunction mode. Only when the retrograde motion reaches the fourth state again, which would correspond to the supposedly correct new state, does the PROM 37 give up its efforts and switch over to a failure mode. A sub-memory or marker flip-flop 95 is set by the output 11 of the PROM 37 if the expected clock bit pattern does not occur at its inputs 1 and 2 but rather another one which necessarily corresponds to a reverse or retrograde motion. In that case, the input 7 of the PROM 37 receives a locking signal from the Q output of the marker flip-flop 95 via the line 102, and, as long as this locking signal or retrograde signal is present, the PROM 37 rejects all clock bit patterns or combinations which do not correspond to the pattern which it had reached prior to the setting of the markerflip-flop 95. If a further retrograde motion results in a receipt of the expected clock track pattern while the locking signal is still present, then the outputs 9 and 10 of the PROM generate termination signals which are fed via lines 103a, 103b to gates 104 and 105, respectively. The gate 105, via the line 106', switches the L input of the status counter 35 to "load", which causes the latter to assume the counter status "full" as its output Q5, and this full signal is fed to gates 107 and 106. It will be appreciated that, due to the fact that the Q and outputs of the marker flip-flop 95 are coupled to the remaining inputs of the gates 107 and 106, respectively, while the marker flip-flop 95 is still 8 GB 2 086 110 A 8 set corresponding to the retrograde motion of the information carrier beyond the third permissible pattern, the output of the gate 106 generates an error signal F beyond the inverter 108, whereas, in the opposite case, i.e., if the marker flip-flop 95 has not been set, a termination signal E occurs which controls the orderly and normal termination of the reading operation.

If the information carrier is moved forward again prior to exceeding the clock bit combination which the PROM 37 is able to remember in retrograde motion, then the setting of the marker flip-flop 95 is nullified and the reading operation proceeds without having been affected by any jittering or retrograde motions of the information carrier. During this entire process, the PROM does not put out any shift signal S which alone would have made it possible to store any information from the reading heads D and Malfunction Due to Excessive Delay An important signal necessary for the function of the overall system is the running signal 9 present at the output of the gate 66. In one of the states of that gate 66, i.e., whenever the Q5 output of the status counter 35 applies a signal indicating a terminated reading process while at the same time the U output of the flip-flop 58 applies a signal indicating the absence of an information carrier at the other input of the gate 66, the running signal R permits only low-power or low-current sensing pulses shown in the R pulse train of Fig. 8. The running signals 9 enter their other state-if an information carrier is present while, at the same time, the status counter 35 is reset to zero or registers a continuing reading process. These running signals, which cause the release of the highcurrent LED pulses, are applied via a branching line 109 to one input of a gate 110, the other input of which receives the shift signal S from the flip-flop 96, and the output of the gate 110 goes to a timing circuit 111 which expires after a predetermined time interval if no further reading pulses are received, which is the case if the information carrier is not inserted further into the apparatus after an excessive period of time. In that case, the next clock pulse of the sequence -9, which corresponds to the T sequence of Fig. 8, sets a flip- flop 112 which applies to the input 15 of the PROM 37 a time expiration signal, causing the PROM 37 to generate output signals for terminating a reading process similar to the occurrence of a malfunction signal F. The timing circuit 111 may be of any suitable design and is represented by an RC element in the exemplary embodiment shown.

Transfer of Data Track Information In the exemplary embodiment illustrated, each data track is 16 bits long, although this number is arbitrary. Furthermore, a given clock track may be associated with any number of data tracks which are read out in parallel whenever the data track control generates an appropriate reading signal S.

It is advantageous if the intermediate registers 98, 99 are double registers in which the contents of the first register are transferred by a transfer signal U either in parallel or in series into the second register after the eighth step, whereupon the first register receives the second half of the data track information. The interrogation and further processing of the data which are stored on the data track in the form of a bit pattern takes place via the output lines 113, i.e., eight bits at a time in parallel in overall serial interrogation. This manner of transfer is arbitrary in principle, as is the manner of treating the collected information from the data track. The data transfer can take place if the line 114 carries the termination signal E from the output of the gate 107, indicating a properly terminated reading process. The transfer signal U is formed from the combination of gates 115, 116 shown in the top left of Fig. 7, which receives a signal indicating the eighth step from the output Q1 of the status counter 35 via line 117, as well as receiving the clock signal via the line 85. The gate 116 is also shown to receive a strobe signal St on the line 118 coming from a further data processing system not illustrated.

Second Exemplary Embodiment of the Apparatus The second exemplary embodiment of the information carrier shown in Fig. 10 illustrates a self-clocking code track having at least two, and generally only two, code tracks for a binary system. These two code tracks, respectively labeled 120a and 120b, are so formed that a change of the value takes place after each bit on one or the other of the two tracks 120a, 120b, but where a simultaneous change on both halves of the code track is not permitted. The basic principle of this exemplary embodiment is that one of the code tracks, for example, 120a, has the logical value 1, whereas the other code track, for example, 120b, has the logical value 0. Accordingly, when the possibility of self-clocking, independently of the insertion speed and including the possibility of stops and even reverse motion, is taken into account, the customary 16 bits on each code track result in an overall number of 65,536 possible code patterns. Each of the code tracks 120a, 120b has an associated reading head 121 a, 121 b. In the exemplary embodiment, the overall coded and stored information corresponds to a particular number or digit which is tested by an evaluation circuit for generating appropriate control signals, for example, for opening a lock. In such a case, the information carrier which carries the two code tracks 1 20a, 1 20b represents a kind of key which might also be inserted into the locked opening carrying the reading heads 121 a, 121 b in the opposite orientation.

As already pointed out in the exemplary embodiment shown, a change must take place in either the right or left code track 120a, 120b after each bit. By sensing the occurrence of positive- or 9 GB 2 086 110 A 9 negative-going edges of the pulses generated by the reading heads, it is possible to realize the principle of self-clocking. Each pulse edge signal is a clock signal and can be used, for example, for shifting a shift register which receives the detected data and may reproduce it, for example, in parallel. The shift register is filled with the bit pattern derived from the two code tracks by assigning to each change in the parity of the left code track the status of a logical 1, while 75 assigning to each parity change in the right code track 120b the status of a logical 0. The information carrier illustrated in Fig. 10 also includes a starting bit 122 followed by a directional bit 123 for insuring that even when the information carrier (key, coding card, etc.) is inserted in the opposite direction, the coded information will be read out in the proper sense.

At the end of the tracks there is provided a stop bit 124.

The starting bit 122, which in this case consists of a bright segment on both tracks, permits the reading apparatus to anticipate a coded track. The directional bit 123 indicates the direction in which the code is to be read. The directional bit has a bright segment on one track and a dark segment on the other, and the dark segment may be associated, for example, with the code track 120a, which has the value of a logical 1.

The embodiment of the data carrier shown in Fig. 10 may be used in association with many of the circuit systems illustrated in Figs. 3-9 and described above. Furthermore, in this embodiment, the coded information including the 100 clock information is read out in pulsed operation.

However, a standby operation is maintained by the generation of very weak sensor pulses as described above.

A part of a preferred apparatus will first be described so as to illustrate more clearly self clocking operation with the code carrier of Figure 10. This part of the apparatus is illustrated in Fig.

11 and includes the two aforementioned reading heads 12 1 a, 121 b consisting of two light sources 110 126 and two light receivers 127, respectively embodied as light-emitting diodes and phototransistors. The signals from the two light receivers 127 are preamplified at 128 and pass to edge detectors 129, which recognize a change in signal levels, i.e., a change from light to dark and vice versa in the two code tracks. The edge detectors generate output signals which are fed via lines 130a, 130b to an OR gate 131 and together they forma clock pulse sequence which permits the evaluation of the data bits. The clock pulse sequence is transmitted via a delay member 132 to the transfer input 133 of a register 134 that stores the data pattern. The data are received by an intermediate register 135, constituted by an RS flip- flop, and so connected that it changes its status only if a previous triggering at one of the inputs 135a, 135b is followed by a triggering at the other input. Any sequential trigger pulses at the same input result in no switching of the flip-flop 135. It will be appreciated that the clock pulse sequence automatically shifts the shift register 134 and, depending on the distribution of data bits on the two code tracks 120a, 120b, the output of the intermediate register 135 constitutes the logical states which result from the distribution of bright and dark fields in the code tracks. These signals are fed via a further gate, preferably an exclusive OR gate 136, to the data input 137 of the shift register 134. It is the property of the exclusive OR gate to change the parity or value of the output signal from the intermediate register 135, while addressing a directional register 138 which is set by the first directional bit 123 on the code carrier 120. Depending on which of the tracks 120a, 120b carries the directional bit, the output signal of the directional register 138 is changed. The register 138 may be a simple f lip-flop, and its effect isto cause the correct evaluation of the distribution of light and dark fields, i.e., as a logical 0 or a logical 1, to be fed into the shift register 134 in accordance with the output of the exclusive OR gate 136. 90 In Fig. 10, the code pattern from the data bits generated by the distribution of light and dark fields is shown adjacent to the code tracks. The directional register 138 is released in the first instance by a start register 139 via a line 140 whenever the start register 139, which may be a simple gate, recognizes the starting bit 122 on both tracks of the data carrier. Similarly, the starting register 139 may take over the transfer of the read-out data information, the resetting of the memory and the preparation for the next reading operation after the termination of the reading process and the arrival of the stop bit 124. The circuit of Fig. 11 includes a timing circuit 140 which generat ' es a malfunction signal when no edge signal is present for a predetermined amount of time.

In a particularly preferred version of the apparatus, it is possible to avoid preliminary storage of the bit pattern carried by the information carrier and to use the first insertion of the information carrier to set the reading device to the specific bit pattern exhibited by that particular information carrier in a permanent way. For this purpose, the circuit of Fig. 11 includes a so-called random access memory (RAM) which receives both data and clock signals during a first reading via connecting lines 142, 143. The memory 141 retains these data permanently, unless a special reset circuit is activated. A coincidence circuit 144 associated with the shift register 134 and the RAM 141 serves to indicate the recognition of the correct data bits by comparing the contents of the shift register 134 with those of the memory 141 after the arrival of the stop bit and to generate an acceptance signal G when coincidence is obtained.

Data Readout in Pulsed Operation In order to adapt the part of the apparatus shown in Fig. 11 for use in reading data in pulsed GB 2 086 110 A 10 operation of the reading heads, which is a manner 55 of operation that has many advantages, especially resulting in increased life and low current consumption, it is only required to provide a supplementary clock generator 145, shown in Fig. 12, which may be embodied, for example, in the manner of the multi-phase oscillator 29 of the first exemplary embodiment and which cooperates in similar manner with the pulse selection processor 33. The pulse generator 145 applies appropriate pulses to the reading head system via the line 146, while a second line 147 leads to an intermediate storage 148 required to perform pulse operation. The intermediate storage, which may consist of two flip-flops, each assigned to receiving information from one of the two coded tracks, generates pulse trains at its outputs 148a, 148b which may be used by the edge detectors 129'. Each of the flip-flops in the intermediate storage 148 is triggered into its respective second state by the change of signals at its input. The remaining circuit elements of the variant of Fig. 12 are not discussed in further detail as they are the same as those in Fig. 11 and carry the same reference numerals, except for a prime symbol. The pulses carried by the line 147 to the intermediate storage 148 and to the starting register 139' cause the transfer of the information present at the data inputs when that information has changed. It should be noted that the information carrier in the illustrations of Figs.

11 and 12 is identified by the numeral 150 and may be, for example, an identification card, a coded card, a key or the like.

An advantage of the apparatus described by the foregoing specification is that individual circuit groups and even large, coherent electronic 90 components which cooperate functionally may also be replaced by an appropriately programmed microprocessor or a similar device, and the use of such a microprocessor is considered to be completely within the frame and scope of the present invention.

The memory 141 shown in Fig. 11 (not shown in Fig. 12 for the sake of clarity) may also be replaced by any memory whatever. Preferably, it may be set in parallel so that the initial setting, i.e., programming to a particular data pattern, causes the information to be received initially in the shift register, from which it is transferred in parallel to the memory 141.

The foregoing description relates to merely preferred exemplary embodiments and variants of the present invention, it being understood that other embodiments are possible within the scope of the invention.

Claims

1. An opto-electronic apparatus for reading data from a data carrier that may be moved with respect to the apparatus for presentation thereto of the data which is represented by patterns of areas, each area being either transparent or opaque to the passage of radiation, the apparatus comprising at least one reading assembly comprising a source of radiation and an associated receiver of radiation, means for guiding the data carrier relative to the at least one reading assembly so as to allow radiation from the source to pass through the transparent ones of the pattern areas to be received by the at least one radiation receiver, electronic data processing means for evaluating the data on the data carrier, and means for operating the at least one reading assembly in at least two different operational modes, in a first of which only one of the at least one reading assemblies is supplied at intervals with short low power sensing pulses, and in a second of which all of the reading assemblies in the apparatus are provided with pulses adjusted to the maximum reading speed and having relatively high power for carrying out the reading operation, the frequency of said low power sensing pulses being less than that of the relative high power pulses and being such that in relation to the speed of movement of the data carrier the system can be switched into the high power reading mode prior to the moment the data patterns have reached the reading assembly.

2. An apparatus as claimed in claim 1, wherein the amplitude of the reading pulses in the high power mode is substantially higher than the amplitude of pulses in the low power mode and is further higher than the maximum continuous power of the reading assemblies, the frequency of occurrence of the high power pulses being adjusted to the maximum reading speed.

3. An apparatus as claimed in Claim 1, comprising means for shutting down powerintensive circuit groups of the data processing means in the low power mode and for applying thereto clock pulses during reading operation whose length is a fraction of the length of the reading pulses.

4. An apparatus as claimed in Claim 1, wherein the switchover from standby operation to reading operation takes place automatically in dependence on the absence of a clock pulse at at least one of the reading assemblies.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1982. Published by the Patent Office. 25 Southampton Buildings, London. WC2A lAY, from which copies may be obtained.