GB2080642A - Battery charging system - Google Patents

Abstract

A traction battery charging system comprises a battery pack (10), a rectifier (12), a current regulator (18), a voltage detector (20) and a controller (16) for automatically performing each charging cycle. Each charging cycle comprises a first phase in which the battery is charged at 30A until the battery voltage reaches a predetermined value, a second phase in which the battery is charged at 20A until the battery voltage reaches a second predetermined value, and a third phase in which the battery is given an overcharge at 10A for a period which depends on the time spent in the first phase. The time spent in the first phase is indicative of the state of discharge at the commencement of charging and thus the value of the overcharge is determined in accordance with the state of discharge. At a predetermined time after the end of the third phase, the battery is given an equalising charge. <IMAGE>

Description

SPECIFICATION Battery charging system This invention relates to a battery charging system in which each charging cycle is controlled automatically and also to a method of charging a traction battery.

In our published United Kingdom PatentApplication No. 2028029 there is described an automatic charging system in which each charging cycle comprises a first charging phase which is terminated when the battery voltage exceeds a predetermined value, a second phase which is terminated when the battery voltage exceeds a predetermined value, and a third phase in which the battery is given a fixed over-charge. It has been found that this system suffers from the disadvantage that the fixed overcharge may be excessive when the system is used to charge a partially discharged battery.

It is an object of this invention to provide an automatic battery charging system and also a method of charging a battery in which the abovementioned disadvantage is overcome or at least reduced.

In accordance with one aspect of this invention, there is provided a battery charging system comprising a battery, means for supplying currenttothe battery, means for regulating the current supplied to the battery, means for detecting the battery voltage, and means for automatically controlling each charging cycle, each charging cycle comprising a first phase which is terminated when the battery voltage exceeds a predetermined value, a second phase which is terminated when the battery voltage exceeds a second predetermined value and a third phase in which the battery is given an over-charge the value of which is determined in accordance with the depth of discharge of the battery at the commencement of charging.

In one arrangement, the value of the over-charge supplied in the third phase is determined by varying the period of the third phase in accordance with the period spent in the first phase.

The control means may comprise a clock, a programme step counter driven by the clock, a first memory addressed by the counter and providing output signals to the current regulating means, a first latch responsive to the counter output arranged to be clocked at the end of the first phase, a second latch responsive to the voltage detector means, and a second memory addressed by the first and second latches and arranged to preset the counter at the commencement of at least the second and third phases.

In another arrangement the value of the overcharge is determined by varying the charging current at which the over-charge is supplied.

Conveniently, the first and second phases are each terminated at the end of a respective predetermined period if such period expires before the battery voltage reaches the respective predetermined value and where one or both such phases have been so terminated the third phase is omitted.

Each of the first, second and third phases may be performed at a constant current, the value of such current being stepwise reduced at the end of the first and second phases.

This invention will now be described in more detail by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram of a charging system embodying this invention; Figure 2 is a circuit diagram of the rectifying section and the battery pack forming part of the system of Figure 1; Figures 3, 3a and 4together form a circuit diagram of the voltage detection section; Figure 5 is a circuit diagram of the current regulator section; Figure 6 is a circuit diagram of the control section; Figure 7, 8 and 9 are circuit diagrams of the relay section, and Figures 10 and 11 are graphs for explaining the operation of the control section.

Referring now to Figure 1, there is shown the charging system, which in the present example is an offboard system, connected to a lead-acid traction battery pack 10 which is normally situated in an electric vehicle. The charging system comprises a rectifier 12 which is connected by a set of rails 13 to a relay section 14, by a set of rails 17 to a current regulator section 18, and by a set of rails 19 to a voltage detecting section 20. The relay section 14 is connected to a control section 16 by a set of rails 22 and to the current regulator section 18 by a set of rails 24. The control section 16 also receives an output signal from the voltage detecting section 20 via a rail 26.

Referring now to Figure 2 there is shown a circuit diagram for the battery pack 10 and the rectifying section 12. These two sections may be connected together by a plug 28 and socket 30 which respectively have co-operating terminals P1 to P8 and S1 to S8.

The battery pack 10 comprises a traction battery 32, the positive terminal of which is connected to the terminal S1 and the negative terminal of which is connected to the terminal S2. The pack 10 further includes an auxiliary battery 34 the positive terminal of which is connected to the terminal S3 and the negative terminal of which is connected to the terminal S4. The pack 10 also includes four pressure operated switches 36 to 39 which are connected in .

series between the positive terminal of the battery 34 and the terminal S7. Each of these pressure operated switches is positioned upstream of an orifice which restricts the flow of gas out of the traction battery 32 and these switches are arranged so that they are normally closed but open if excessive gassing occurs in the battery. The pack 10 also includes a ventilating fan 40 connected across the terminals S5 and S6. Finally, the pack 10 includes a probe 42 for measuring the temperature of the electrolyte of the traction battery 32. The probe 42 including a pair of transistors T1 and T2 housed in a glass tube positioned in the electrolyte and a variable resistor R1, a fixed resistor R2, and a variable resistor R3 connected in series between the terminal S8 and the terminal S2.The common point of resistors R2 and R3 is connected to the base of transistor T1,the collector of which is connected to the terminal 58 and the emitter of which is connected to the base of the transistor T2. The collector of transistor T2 is open circuit and the emitter is connected to the terminal S2 so the transistor T2 functions as a diode.

The rectifying section 12 comprises a mains transformerTX1 having a primary winding W1 and a main secondary winding W2 and an additional secondary winding W3. The primary winding W1 is connected to a pair of mains supply terminals L, N through a pair of contacts 44A and 44B operated by a relay coil 44, one end of which is connected to the terminal N and the other end of which is connected to a terminal M2. A lamp LA1 is connected across the winding W1.

One end of the secondary winding W2 is connected to the anode of a thyristor TH1 and to the cathode of a thyristor TH2. The cathode of thyristor TH1 is connected to the cathode of a diode D1 and the anode of the thyristor TH2 is connected to the anode of a diode D2, the anode of diode D1 and the cathode of diode D2 being connected together to the other end of winding W2. A surge suppressor in the form of a resistor R4, a capacitor C1 and a capacitor C2 connected in series is connected across the winding W2. The cathode of thyristor TH1 is connected through a smoothing inductor L1 to terminal P1 and terminal P2 is connected through a current measuring resistor R5 to the anode of thyristor TH2.

Terminal P4which during charging is connected to the negative terminal of the auxiliary battery 34 is connected to earth.

The circuit diagram of Figure 2 also shows a transformer TX3 having a secondary winding connected to terminals P5 and P6 and a primary winding, one end of which is connected to one end of a relay coil 46 bridged by a resistor R6 and this winding is also bridged by a lamp LA2. The terminal P7 is connected to contacts 46A which are operated by relay coil 46.

In operation with the terminals Land N connected to a mains power supply, charging current is applied to the traction battery 32 and the value of this current is determined by the firing of thyristors TH1 and TH2 and, as is described below, this firing is controlled by the current regulating section 18.

Referring now to Figures 3 and 3a there is shown the circuit diagram of the voltage detecting section 20. As will be described below, two phases of the charging cycle are terminated if the voltage of the traction battery 32 exceeds a predetermined value and the function of the voltage detection section is to compare the voltage of the battery 32 with a reference voltage and to provide an output signal when a predetermined voltage value is reached.

The voltage detection section 20 comprises a full wave rectifier 50 the input terminals of which are connected across the auxiliary winding W3 of Figure 2, the positive output terminal of which is connected through a diode D5 to a positive supply rail t2 and the negative terminal of which is connected to a negative supply rail 54. The rail 54 is connected to the terminal P2 of plug 28 shown in Figure 2. The rail 52 is connected to the cathode of a zener diode ZD1, the anode of which is connected through a resiStor R10 to the rail 54. The zener diode ZD1 and resistor R10 are bridged by a capacitor C5.The junction bf zener diode ZD1 and resistor R10 is connected to the base of a PNP transistor T5, the emitter of which is connected through a resistor R11 to the rail 52 and the collector of which is connected to the anode of a protection diode D3. The cathode of diode D3 is connected to the cathode of a zener diode ZD4, the anode of which is connected to the rail 54. The cathode of zener diode ZD4 is connected through a rail 56 to terminal P8 of plug 28 shown in Figure 2.

In use, the zener diode ZD1, resistors R10 an-d R11 and transistor T5 function as a constant current source and together with the probe 42 function to establish a reference voltage at the collector of transistor T5. As may be ap-preciated, if the temperature of the electrolyte rises, then the value of this reference voltage falls thereby compensating for the falling value of the internal resistance of battery 32 with rising electrolyte temperature.

The collector of transistor T5 is connected through a resistor R13 to the inverting input of an operational amplifier A1 and through a resistor R14to the non-inverting input of an operational amplifier A2.

Rail 52 is connected through a resistor R15, a capacitor C6 and a resistor R1 6 to rail 54 and the junction of capacitor C6 and resistor R16 is connected to the base of an NPN transistor T6 which is connected as a Darlington pair to a transistor T7, the emitter of which is connected to rail 54. The collector of transistor T6 is connected through a pair of resistors R17 and R18, connected in series, to the non-inverting input of amplifier Al. The junction of resistors R17 and R18 is connected through a resistor R19 S a resistor R20 which is bridged by relay contacts 180B, a variable resistor R21, a resistor R22, and resistor R23, all connected in series, to terminal P1 of plug 28.The junction of resistors R17 and R18 is also connected through a resistor R24to rail 54, resistor R24 being bridged by a capacitor C7. The output of amplifier Al is connected to its noninverting input through a resistor R25 and a capacitor C8, connected in parallel.

Resistors R19 to R24 function as a potential divider and thus, in use, the amplifier A1 compares a fraction of the traction battery voltage with the reference voltage, the output of amplifier going high when this fraction of the battery voltage exceeds the reference voltage. The fraction of the battery voltage which is applied to the amplifier Al may be varied by opening and closing relay contacts 180B thereby varying the battery voltage at which the output of amplifier Al goes high.

When power is initially supplied to the system, transistors T6 and T7 function to remove the traction battery voltage from the nonrinverting input of amplifier Al thereby providing time forth reference voltage to be established before it is compared with the traction battery voltage.

The inverting input of amplifier A2 is connected through a resistor R26 to the junction of a pair of resistors R27 and R28 connected in series-between rails 52 and- 54 so as to provid-e arofereneevoItag e to this input. The output of asrrpliflcrr i J 6fitjQcted td its non-inverting input through a resistor R29. The output of amplifier A2 is also connected through a resistor R30 and a capacitor C9, connected in series, to rail 54 and the junction of resistor R30 and capacitor C9 is connected to the emitter of a unijunction transistorT8. The first base of transistor T8 is connected to the rail 54 and the second base is connected through a resistor R31 to rail 52.The junction of capacitor C9 and resistor R30 is also connected through a resistor R32 to the base of an NPN transistor T9, the collector of which is connected to the rail 52 and the emitter of which is connected through a resistor R33 to rail 54. The emitter of transistor T9 is connected to the cathode of a zener diode ZD2, the anode of which is connected through capacitor C10 to rail 54 and also through a resistor R34 to the base of an NPN transistor T1 0. The output of amplifier Al is connected through a pair of resistors R35 and R36, connected in series, to rail 54 and the junction of these resistors is connected to the anode of zener diode ZD2.

The emitter of transistor T10 is connected to the anode of a light emitting diode D6, the cathode of which is connected to rail 54 and which forms one half of an optical coupler. The collector of transistor T10 is connected through a resistor R37 to rail 52 and also through a resistor R38 and a capacitor C11, connected in series, to rail 52. The junction of resistor R38 and capacitor C11 is connected to the base of a PN P transistor T1 1, the emitter of which is connected to rail 52 and the collector of which is connected through a resistor R39 to rail 54 and also through a resistor R40 and capacitor C12, connected in series, to rail 54. The junction of resistor R40 and capacitor C12 is connected to the base of an NPN transistor T12, the emitter of which is connected to rail 54 and the collector of which is connected through a resistor R41 to the junction of resistors R17 and R18.

In operation, whilst the fraction of the traction battery voltage applied to the non-invert input of amplifier Al is lower than the reference voltage, the output of amplifierAl will remain low. However, when the voltage applied to the non-invert input of amplifier Al exceeds the reference voltage the output of amplifier Al will go high thereby rendering transistor T10 conductive and energising photodiode D6 and also rendering transistors T11 and T12 conductive for a short period thereby removing the traction battery voltage from the non-inverting input of amplifier A1.

The output of amplifier A2 will normally be low but if for some reason the connection between the diode D3 and the probe 42 is interrupted the output of amplifier A2 will go high. When this happens, the capacitor C9 will be repeatedly charged until the intrinsic stand-off voltage of unijunction transistor T8 is reached and then rapidly discharged thereby supplying a series of positive pulses to the base of transistorT9. In consequence, a series of positive pulses will be supplied to the base of transistor T10 and so photo-diode D6 will be repeatedly energised and de-energised.

Referring now to Figure 3a there is shown a part of the voltage detecting section which detects an open circuit in rail 56 which connects the voltage detection section to the probe 42 and which also detects opening of one of the pressure operated switches 36 to 39.

In this part of the voltage detecting circuit rail 52 is connected through a resistor R200 to the anode of a light emitting diode D50, the cathode of which is connected to the anode of a thyristor The 0. The cathode of thyristorTH10 is connected through a resistor R201 to the rail 54. The gate of thyristor TH 10 is connected through a resistor R202 to the rail 54 and also through a pair of resistors R203 and R204, connected in series, to the rail 54. The junction of resistors R203 and R204 is connected to the anode of a zener diode ZD20, the cathode of which is connected to the rail 56.

The cathode ofthyristorTH10 is connected through a pair of resistors R205 and R206, arranged in series, to the rail 54 and the junction of these resistors is connected to the base of an NPN transistor T100. The emitter of transistor T100 is connected to the rail 54 and its collector is connected both to the collector of an NPN transistor T101 and to a rail 300. The emitter of transistor T101 is connected to the rail 54 and its base is connected through a resistor R207 to the rail 54 and also through a pair of resistors R208 and R209, arranged in series, to the rail 52. The junction of resistors R208 and R209 is connected to the collector of an NPN phototransistor T102 which forms an optical isolator together with a light emitting diode D51.The emitter of transistor T102 is connected to rail 54 and its base is connected to rail 54 through a resistor.R210.The cathode of diode D51 is connected to terminal P4Df plug 28 and its anode is connected through a resistor R211 and contacts 46A to terminal P7 of this plug.

In operation, providing all the switches 36 to 39 are closed transistor T102 is turned on and hence transistor T101 is turned off. However, if one of these switches opens due to excessive gassing then transistorT101 will turn on thereby causing rail 300 to go low.

Also, if an open circuit in rail 56 occurs this will cause thyristor TH 10 to fire thereby turning on transistor T100, causing rail 300 to go low, and energising diode D50.

As will be explained below, if rail 300 goes low thyristor TH1 and TH2 shown in Figure 2 will be prevented from firing thereby preventing current from being provided to the traction battery 32.

Referring now to Figure 4, there is shown a further part of the voltage detecting section and this comprises a pair of rails 60 and 62 which are connected respectively to terminals P3 and P4 of plug 28. Rail 60 is connected to the anode of a diode D7, the cathode of which is connected through a resistor R42 to the collector of a photo-transistor T13. The photo-transistor T13 forms the other part of the optical coupler previously described with reference to the light emitting diode D6. The emitter of transistor T13 is connected to its base through a resistor R43 and directly to the rail 62. The collector of transistor T13 is connected through a resistor R44 to the base of an NPN transistor T14, the emitter of which is connected to rail 62 and the collector of which is connected through a resistor R45 to the cathode of diode D7.The collector of transistor T1 4 is also connected through a resistor R46 to the cathode of a zener diode ZD3, the anode of which is connected to the rail 62.

The cathode of zener diode ZD3 is connected to the rail 26 which provides the output signal to the control section. In use, when the diode D6 is not energised, transistorT13 is non-conductive and consequently transistor T14 is conductive and the output signal is low. When the light emitting diode D6 is energised, then the transistor T13 is rendered conductive and so the output signal goes high.

The optical coupler comprising light emitting diode D6 and photo-transistorTi3 is provided so as to isolate the voltage detection section 12 from the control section 16.

There is also shown in Figure 4 the power supply for the various integrated circuits used in the system and this power supply comprises a resistor R47 connected between the cathode of diode D7 and the cathode of a zener diode ZD4, the anode of which is connected to the rail 62. The zener diode ZD4 is bridged by a pair of capacitors C13 and C14 and the cathode and anode of zener diode ZD4 are connected respectively to positive and negative supply rails Vdd,Vss.

Turning now to Figure 5, there is shown the detailed circuit diagram for the current regulator 18.

This comprises a full wave rectifier 70, the input terminals of which are connected across the auxiliary winding W3 shown in Figure 2, and the output terminals of which are connected to rails 72 and 74.

Rail 72 is connected through a capacitor C20 to rail 74 and also through a resistor R60 to the base of an NPN transistor T20, the collector of which is connected to the rail 72 and the emitter of which is connected to a rail 76. The base of transistor T20 is also connected to the cathode of a zener diode ZD7, the anode of which is connected to the rail 74. In use, a constant voltage will normally be present between rails 76 and 74.

The auxiliary winding W3 of Figure 1 is also connected to the input terminals of a full wave rectifier 78, the negative output terminal of which is connected to the rail 74 and the positive output terminal of which is connected through a resistor R61 to the cathode of a zener diode ZD8, the anode of which is connected to the rail 74. The cathode of zener diode ZD8 is connected through a capacitor C2i to rail 74 and through a resistor R62 to the base of an NPN transistor T2l,the base of which is also connected through a resistor R63 to the rail 74.

In operation, a clipped fully rectified wave form will be present at the junction of resistors R62 and R63.

The emitter of transistor T21 is connected to the rail 74 and its collector is connected to the junction of a pair of resistors R64 and R65 connected in series between rails 76 and 74. The collector of transistor T21 is also connected through a resistor R66 to the base of an NPN transistor T22, the emitter of which is connected through a resistor R78 to the rail 74 and the collector of which is connected through a capacitor C22 to the rail 74. The collector of transis tor T22 is also connected through a resistor R67 to the cathode of a diode D10, the anode of which is connected to the rail 76.The junction of resistor R67 and capacitor C22 is also connected to the non inverting input of an operational amplifier A5, the - - output of which is connected to its inverting input and also connected through a capacitor C23 to the cathode of diode D10.

In operation, a ramp shaped wave form will be present at the output of amplifier A5.

The output of amplifierA5 is connected through a resistor R68 to the inverting input of an operational amplifier A6, the output of which is connected to its non-inverting input through a resistor R69. The output of amplifier A6 is also connected through a capacitor C24 to the trigger input TR of a monostable 78 (which comprises a type NE555 timer connected as a monostable). The output Q of monostable 78 is connected through a pair of resistors R70 and R71, connected in series, to the rail 74 and the junction of these resistors is connected through a further resis tor R72 to the base of an NPN transistor T23, the emitter of which is connected to the rail 74. The base of transistor T23 is connected to rail 300 shown in Figure 3a.

The collector of transistor T23 is connected through the primary winding of a transformerTX3 and resistor R73 to the rail 76, the primary winding being bridged by a free-wheel diode D11. The transformer TX3 has a pair of secondarywindings W5 and W6. One end of the winding W5 is connected to the anode of a diode D12, the cathode of which is connected through a resistor R74to the gate of thyristorTH1 shown in Figure2 and the other end of winding W5 is connected to the cathode of this same thyristor. The winding W5 is bridged by a resistor R75.One end of winding W6 is connected to the anode of a diode D13, the cathode of which is connected through a resistor R76 to the gate of thyristor TH2 shown in Figure 2 and the other end of this winding is connected to the cathode of this same thyristor. The winding W6 is bridged by a resistor R77.

The current regulating section also includes a pair of resistors R79 and R80 which are connected across the current measuring resistor R5 shown in Figure 2.

The junction of resistor R79 and R80 is connected to the non-inverting input of an operatipnal amplifier A7 and the other end of the resistor R80 is connected through a resistor R81 to the inverting input of this amplifier. The output of amplifier A7 is connected to its inverting input through a resistor R82 and, in operation, the voltage appearing at the output of amplifier A7 is representative of the current being supplied to the traction battery 32.

The output of amplifier A7 is connected through resistor R83 to the non-inverting input of an opera tional amplifierAB, the output of which is connected through a resistor R84to its inverting input. The non-inverting input of amplifierA8 is connected through a resistor R85 to the rail 74.

Rail 76 is connected through a resistor RBS-to the cathode of a zener diode ZD9ttht rildge$'by a i capacitor C26 art whose anode -- - - -- d to the rail 74. The cathode of zener diode ZD9 is connected through one of a set of resistors, the value of which as will be described with reference to Figure 10 corresponds to the required charging current, and a variable resistor R87 to the rail 74. A tapping on resistor R87 is connected through a resistor R88 to the inverting input of amplifier A8.

Thus, in operation the amplifier A8 compares the actual charging current with the required charging current and its output provides an appropriate error signal.

The output of amplifier A8 is connected through a resistor R90 to the non-inverting input of an amplifier A9, the output of which is connected through a resistor R91 to its inverting input and the inverting input of which is connected to the rail 74 through a resistor R92. Connected in series between rails 76 and 74 are a resistor R93 and a variable resistor R94, and a tapping of resistor R94 is connected through a resistor R95 to the non-inverting input of amplifier A9. Also connected in series between rails 76 and 74 are a capacitor C27 and a resistor R96, and the junction of capacitor C27 and resistor R96 is connected to the anode of a diode D15, the cathode of which is connected through a resistor R97 to the non-inverting input of amplifier A9.

The output of amplifier A9 is connected through a resistor R98 and a capacitor C28, connected in series, to the rail 74 and the junction of resistor R98 and capacitor C28 is connected through a resistor R99 to the non-inverting input of amplifier A6.

In operation, during each half cycle of the mains power supply, the output of amplifier A6 will go low when the voltage supply to its inverting input exceeds that applied to its non-inverting input. When the output goes low, the monostable 78 will be triggered thereby rendering transistor T23 conductive and applying output pulses to the thyristors TH1 and TH2. Consequently, the thyristor which is forwardly biassed will be rendered conductive and so charging will proceed at the required charging current.

If the rail 300 shown in Figure 3a goes low, then output pulses will not be applied to the thyristors TH1 and TH2 and so charging will be prevented.

When the charger is first energised, a high voltage will initially be present at the junction of capacitor C27 and resistor R96 thereby ensuring that the initial charging current is low. Subsequently, this voltage will decay thereby allowing a gradual build-up of the charging current until it reaches the required level.

In Figure 6 there is shown a circuit diagram for the control section 16 of the charging section. This section includes a pair of INTERSILtype IM6654 programmable read only memories (PROM)90,92, a pair of RCA typ CD4516 presetable counters 94, 96 connected so as to form a single eight bit counter, a pair of RCA type CD4042 data latches 98, 100 connected so as to form a single eight bit latch, a clock pulse generator 102 formed from a type 555 timer, an RCA type CD4020 counter 104, six RCA type CD4098 monostables 105 to 110, and six RCA type CD4098JKflip-flops 115to 120.

The output 0 of the clock pulse generator 102 provides clock pulses at intervals of 54.93 ms to one input of a NAND gate 124. The other input of NAND gate 124 may be selectively connected through relay contact 1 26A to the negative supply rail Vss or to the positive supply rail Vdd. The output of NAND gate 124 is connected to the clock input C of counter 104, the Q14 output of which is connected to the clock inputs C of counters 94 and 96 so that in normal operation these counters will be clocked at intervals of 15 minutes. The Q4 output of counter 104 is connected to the negative trigger input -TR of monostable 107, the 0 output of which is connected to the control input E of PROM 92.

The cathode of zener diode ZD3 shown in Figure 4 is connected through a resistor R1 10 and a capacitor C40, connected in series, to the earth rail and the junction of resistor R110 and capacitor C40 is connected to both inputs of a Schmitt inverter 126.

The output of inverter 126 is connected to the two inputs of another Schmitt inverter 128, the output of which is connected to the earth rail through a resistor R111 and to the positive trigger input +TR of monostable 110. Thenoutput of monostable 110 is connected to one input of a NAND gate 130 and the O output of monostable 110 is connected to the clock inputC of each offlip-flops 115,116 and 118.TheJ input of flip-flop 115 is connected to rail Vdd and the K input is connected to rail Vss. The 0 output of flip-flop 115 is connected to the J input of flip-flop 116, to one input of a NAND gate 132, to one input of a NAND gate 134, and to the address input cif PROM 90.The K input of flip-flop 116 is connected to the rail Vss and its Q output is connected to the other input of NAND gate 134 and the address input A6 of PROM 90. The J input of flip-flop 117 is connected to rail Vdd, the K input is connected to rail Vss and the O output is connected to the address input A7 PROM 90. The J input of flip-flop 118 is connected to rail Vdd, the K input is connected to rail Vss and the Q output is connected to the clock input C of latches 98, 100. The output of NAND gate 134 is connected to the reset input R of monostable 110 and to the J input of flip-flop 119.

The positive rail Vdd is connected to earth through a resistor R112 and a capacitor C44, connected in series, and the junction of resistor R1 12 and capacitor C44 is connected to the positive trigger input +TR of monostable 109. The Q output of monostable 109 is connected to one input of a NAND gate 136, the other input of which is connected to the output of NAND gate 132. The Q output of monostable 109 is also connected to the reset inputs R of monostables 105, 106, 107 and 108. The Q output of monostable 109 is connected to the reset input R of each of flip-flops 115 to 120.

The output of NAND gate 136 is connected to the negative trigger input -TR of monostable 108, the Q output of which is connected to one of the inputs of NAND gate 130. The output of NAND gate 130 is connected to the positive trigger inputs +TR of monostables 105 and 106, the 0 output of monostable 105 is connected to the control input E of PROM 90 and the 0 output of monostable 106 is connected to the preset inputs PE of counters 94 and 96 and to the reset input R of counter 104.

As will be explained in more detail below, the counters 94 and 96 count the steps of each programme cycle. The Ol to Q4 outputs of counter 94 are connected to the address input A0 to A3 of PROM 92 and the Q1 to Q4 outputs of counter 96 are connected to the address inputs A4 to A7 of PROM 92. The data output DO of PROM 92 is connected to the input of a buffer 140, the output of which is connected through a resistor R120 and a capacitor C50, connected in series, to the earth rail, and the junction of resistor R120 and capacitor C50 is connected to the other input of NAND gate 132 and also to the clock input C of flip-flop 117. The data outputs D1 to D5 of PROM 92 are connected respectively to the inputs of buffers 142 to 146.As will be described in more detail below, the outputs of these buffers provide signals for controlling the current level in which charging proceeds. The data output D6 of PROM 92 is connected to the input of a buffer 147, at the output of which there is provided a signal for controlling energisation of the fan 40 shown in Figure 2. The data output D3 of PROM 92 is also connected through a resistor R121 and a capacitor CSl to the earth rail and the junction of resistor R121 and capacitor C51 is connected to the clock input C of flip-flop 119.The Q output of flip-flop 119 is connected to the input of a buffer 148, the output of which provides a signal indicating that a failure has taken place in the charging cycle. The O output of flip-flop 119 is connected to one input of an NAND gate 149, the other input of which is connected to the data output D7 of PROM 92. The output of NAND gate 149 is connected to the input of an inverter 150, the output of which there is provided a signal which enables charging to take place. The data output D6 of PROM 92 is also connected through a resistor R122 and a capacitor C52 to earth, and the junction of resistor R122 and capacitor C52 is connected to the two inputs of a NAND gate 152, the output of which is connected to the clock input C of flip-flop 120.The J input of flip-flop 120 is connected to thenoutput of flip-flop 119 and the 0 output of flip-flop 120 is connected to the input of a buffer 154, the output of which provides a signal indicating that the battery under charge has been charged and is ready for further use.

As will be explained in more detail below, PROM 92 is programmed to provide appropriate output signals for each step of the programme cycle.

The Q1 to Q4 outputs of counter 94 are also connected to the data inputs D1 to D4 of latch 98 and the Q1 output of counter 96 is connected to thepl input of latch 100. The Q1 to Q4 outputs of latch 98 are connected to the address inputs A0 to A3 of PROM 90 and the Q1 output of latch 100 is connected to the address input A4 of PROM 90. The data outputs DO to D7 of PROM 90 are connected respectively to the preset inputs P1 to P4 of counter 94 and to the preset inputs P1 to P4 of counter 96.

The function of latches 98 to 100 and of PROM 90 will be described in more detail below.

Referring now to Figures 7 to 9 there is shown the circuit diagram for the relay section 14. As shown in Figure 7, mains terminal L is connected through relay contacts 1 70A to one end of the primary winding of transformer TX3, shown in Figure 2, and mains terminal N is connected through relay contact 170B and through relay coil 46 to the other end of this winding. The mains terminals Land N are also connected by relay coil 126 which controls relay contacts 126Ashown in Figure 6.

Terminal P3 of plug 28 shown in Figure 2 is connected to a rail 172 and terminal P4 of plug 28 is connected to a rail 174. The output of buffer 147 of Figure 6 is connected through a resistor R130 to the base of an NPN transistor T30 and through a further resistor R31 to rail 174. The emitter of transistor T3O is connected to rail 174 and its collector is connected through a relay coil 170 to rail 172. Relay coil 170 which is bridged by a free-wheel diode D20 controls relay contacts 1 70A, 1 70B. Consequently, when the output of buffer 147 goes high, transistor T30 is rendered conductive thereby energising coil 170, closing contacts 170A, i70B and thereby energising the fan 40.

The output of inverter 150 shown in Figure 6 is connected through a resistor R1 32 to the base of an NPN transistorT31 and also through a resistor R133 to rail 174. The emitter of transistor T31 is connected to rail 174 and its collector is connected to tile emitter of a transistor T32. The collector of transistor T32 is connected through a relay coil 176 to a rail 178 which in turn is connected through relay contacts 46A, shown in Figure 2, to terminal P7 of plug 98.

The rail 178 is connected to the cathode of a zener diode ZD30, the anode of which is connected through a capacitor C41 and a resistor R230, connected in parallel, to the rail 174 and also directly to the base of transistor T32. Relay coil 176, which is bridged by a free-wheel diode D21,controls relay contacts 1 76A which connect the mains terminal L to the mains terminal N through relay coil 44 shown in Figure 2.

The outputs of buffers 142 to 146 of Figure 6 are connected respectively through resistors R135 to R1 39 to the bases of a set of NPN transistors T35 to T39. The bases of transistors T35 to T39 are also connected respectively through resistors R140 to R144 to rail 174 and their emitters are connected directly to this rail. The collectors of transistors T35 to T39 are connected respectively through relay coils 180 to 184 to rails 172 and these coils are bridged respectively by free-wheel diodes D25 to D29. The output of buffer 148 and the output of buffer 154 of Figure 6 are connected respectively through resistors R150 and R151 to the bases of NPN transistors T40 and T41.The bases of these transistors are also connected through resistors R152 and R153 to rail 174 and their emitters are connected directly to this rail. The collectors of these transistors are connected respectively through relay coils 190 and 191 to rail 172 and these relay coils are bridged by free-wheel) diodes D30, D31.

Turning now to Figure 8, normally closed relay contacts 180A to 184A which are controlled respec- tively by relay coils 180 to 184 are connected in series between the cathode of zener diode ZD9 and one end of resistor R87 shown in Figure 5. These relay contacts are also bridged respectively by preset resistors R1 60 to Rut64. Thus,when b?ieof the coils 180 to 184 is energised; ffie Eecgle one of the resistors R160 to R164 will be connected into the circuit shown in Figure 5.

Referring now to Figure 9 there is shown a transformer TX6, the primary winding of which is connected across mains terminals Land N and the secondary winding of which is connected to rails 200 and 202. Rail 200 is connected to the anode of a diode D35, the cathode of which is connected to a rail 204. The rail 202 is connected through a resistor R160 to a rail 206. The rail 204 is connected respectively through normally closed relay contacts 181B, 182B, 183B, 1848, 190B, l9iBto the anodes of a set of light emitting diodes D36 to D4l,the cathodes of which are connected to the rail 206.The light emitting diodes D36 to D39 indicate that charging is taking place at an associated current level, the light emitting diode D40 indicates that a failure has occurred in the charging cycle, and the light emitting diode D41 (ready lamp) indicates that charging has been completed.

Referring now especially to Figures 6 to 9, as mentioned above the data outputs D1 to D5 of PROM 92 correspond respectively to charging levels 11 to 15.

A high signal on one of these data outputs will cause a respective one of transistors T35 to T39 to be rendered conductive thereby energising a respective one of coils 180 to 184 and opening a respective one of relay contacts 180A to 184A. This will cause one of the resistors 160 to 164 to be inserted into the current regulating section as shown in Figure 5 and the charging current is then regulated in accordance with the value of the resistor so inserted. The resistors 160 to 164 are adjusted so that they correspond to charging current levels Il to 15. In this example, the charging current levels Il to 15 correspond respectively to charging currents of 30 amps, 20 amps, 10 amps, 10 amps and 10 amps.

Data output D6 of PROM 92 controls the operation of fan 40. When this data output goes high, transistor T30 is rendered conductive thereby energising coil 170, closing relay contacts 170A, 170B and thereby supplying powerto the fans 40. Providing fans 40 operate normally, relay coil 46 is energised thereby closing relay contacts 46A. Then, providing the switches 36 to 39 are closed indicating that there is no excessive gassing occurring in traction battery 32, power is supplied to rail 178.

Data output D7 of PROM 92 controls the supply of charging current. If this data output goes high with a high output also present at the8output of flip-flop 119, then transistor T31 is rendered conductive.

Then, providing rail 178 is art a sufficiently high voltage to turn on transistor T32, which will be the case unless the voltage of auxiliary battery 34 has fallen to an abnormally low value, coil 176 is energised and contacts 176A are closed thereby energising relay coil 44 and so closing mains contacts 44A, 44B. With the mains contacts 44A, 44B closed charging current is supplied to the traction battery 32. When one of the outputs of buffers 148 and 154 goes high, then a respective one of transistors T40, T41 is rendered conductive thereby closing a respective one of relay contacts 190B, 191B.

When charging is taking place at current level 11, relay contacts 180B shown in Figure 3 are closed thereby raising the fraction of the traction battery voltage applied to the non-inverting of amplifier Al and so lowering the battery voltage at which the output of this amplifier goes high.

A complete charging cycle will now be described firstly in general terms with reference to Figure 10 and thereafter in greater detail.

Referring now to Figure 10 there is shown the variation of charging current level with the steps of the programme, these steps being represented by the output of counters 94,96. The main part of recharging comprises three phases. The fi-rst of these three phases commences at step 0 and during this phase the battery is charged at current level 11.

This phase may continue for seven hours at which stage step 28 is reached. However, this phase is normally terminated when the traction battery voltage reaches a predetermined value and when so terminated a jump is made to step 28. The second phase commences at step 28 and at the commencement of this phase the charging current is reduced to current level 12 in order to reduce gassing. The second phase may continue for two hours at which stage the step 36 is reached. However, this phase is also normally voltage terminated.

At the termination of the second phase, the battery should be fully charged and the purpose of the third phase is to give it an overcharge. It has been found that the value of this overcharge should be reduced in the case of a traction battery which is only partially discharged at the commencement of recharging.

One indication of the state of discharge is the time spent in the first phase of charging and in the present system the time spent in the third phase is varied in accordance with-the time spent in the first phase in the manner shown in Figure 11. Thus, although the third phase may commence at step 36 and continue for four hours until step 52 is reached, in the case of a partially discharged battery a jump is made at the commencement of the third phase to a step intermediate steps 36 and 52. At the commencement of the third phase, the charging current is reduced to level 13 so as to reduce gassing.

In the event that the traction battery voltage does not reach the respective predetermined value in both the first phase and the second phase, this implies that a fault has occurred and the third phase is omitted.

From steps 52 to 69, charging is inhibited and from steps 69 to 71 the battery is given a topping up charge at current level 14. From steps 71 to 88 charging is again inhibited.

In the normal course of events, step 88 is reached at intervals which are less frequent than each charging cycle. Step 88 occurs nine hours after the termination of the main part of the charging cycle and, depending upon the time spent in the first, second and third phases, approximately twenty hours from the commencement of charging. Thus, a traction battery will normally have been disconnected from the charging system before step 88 is reached. For example, in the case of a traction battery installed in an electric vehicle which is used for commercial purposes, it will normally be connected to the charging system in the early evening after the vehicle has performed its daily round of duties and, providing the next day is a working day, it will be disconnected in the early morning of this day.When the next day is not a working day, for example the beginning of a weekend, then step 88 will be reached.

From steps 88 to 120 the battery is charged at current level 15. The purpose of this is to give the battery an equalising charge so as to bring the weaker cells of the battery into a fully charged condition. Although it is desirable to give a battery an equalising charge at periodic intervals, these should be less frequent than each recharging as the overcharging which occurs causes a small amount of damage to the battery. By arranging the charging cycle so that the equalising charge is only reached at intervals which are less frequent than each recharging, this is achieved.

From steps 120 to 137, charging is again inhibited and then from steps 137 to 139 a further topping-up charge is given. At step 144 the programme jumps back to step 128 and the programme then continues to operate between these two steps until the charging system is disconnected from the battery.

In the event of a malfunction, the programme jumps to step 146.

In the following description, binary "1" refers to a high signal and binary "0" refers to a low signal.

At the commencement of each charging cycle, which also corresponds to the commencement of the first phase, relay contacts 1 26A will connect the supply rail Vdd to one input of a NAND gate 124 so that pulses at fifteen minute intervals are supplied to the clock input of counter 96. A positive going voltage will also be supplied to the trigger input +TR of monostable 109 thereby resetting flip-flops 115 to 120 and also triggering monostable 108 thereby triggering monostables 105, 106. As a result of resetting the flip-flops, the binary number 000 will be supplied to the three most significant address inputs A7, A6, A5 of PROM 90. When so addressed PROM 90 is programmed so that the binary number 00000000 will always be present at its data outputs D7 to DO.As a result of triggering monostables 105, 106, the 04 to Q1 outputs of counters 96 and 94 will be preset to this binary number, which is equivalent to decimal 0, and represents step 0 of the charging cycle. It should be noted that counter 104 is also reset at this stage of the programme and that pulses at a relatively high frequency are supplied by monostable 107 to the control input of PROM 92.

With the address inputs A7 to A0 of PROM 92 set to a binary number from 00000000 (decimal 0)to binary 00011011 (decimal 27), PROM 92 is programmed to provide a high signal at its data outputs D1, D6 and D7, thus charging proceeds at current level Ii from steps 0 to 27.

If the voltage of the traction battery reaches its predetermined value during the first phase, then a high signal is supplied to the inputs of the Schmitt inverter 126 thereby triggering monostable 110 and setting flip-flops 115 and 118 and also triggering monostables 105, 106. Consequently, the binary number 001 will be supplied to the address inputs A7, A6, A5 of PROM 90 and when so addressed PROM 90 is programmed so that the decimal number 28 is present at its data outputs. As a result of triggering monostables 105, 106 the outputs of counters 96 and 94 are preset to this number and a jump occurs to step 28 which is the beginning of the second phase.

As a result of setting flip-flop 118, the number present at the Q1 output of counter 96 and Q4 to Q1 outputs of counter 94 is latched in latches 98, 100.

This number represents time spent in the first phase.

With the address inputs A7 to A0 of PROM 92 set to a binary number from 00011100 (decimal 28) to binary 00100011 (decimal 35), PROM 92 is programmed to provide a high signal at its data outputs D2, D6, and D7, and thus charging proceeds at current level 12 from steps 28 to 35.

If during the second phase the battery voltage reaches its predetermined value, which will be higher than the value in phase one as contacts 180iS are closed, then monostable 110 is again triggered and thereby setting flip-flop 116 and also triggering monostables 105, 106. Consequently the binary number 011 will be present at the address inputs A7,A6,A5 of PROM 90. When so addressed, it is programmed so that the number present at its data outputs depends upon the number supplied at its address inputs A4 to A0 in such a manner that the programme jumps to the appropriate step of the third phase so that the time spent during the third phase will be related to the time spent on the first - phase as shown in Figure 11 as discussed above.

PROM 92 is programmed so that with its address inputs A7 to A0 set to a value between decimal 36 and decimal 51 a high signal is present at its data outputs D3,D6,D7 so that charging proceeds a - current level 13 in the third phase.

At the commencement of the third phase, a high signal is supplied to the clock input C of flip-flop 119.

Providing both flip-flops 115, 116 are set as a result of the battery voltage reaching-its predetermined value in both first and second phases, a low signal will be present at the J input of flip-flop 119 and so its Q output will remain at a high value. However, if one or both of these flip-flops 115, 116 has not been set, then flip-flop 119 will be set thereby supplying a low signal at its Q output, and consequently a low signal will be present at the output of inverter 150 thereby inhibiting charging. Also, the high signal present at the 0 output of flip-flop 119 will cause the fail lamp to be energised.

At step 52, only the data output D6 of PROM 92 will be high and so the fans will be energised but charging will be inhibited.

From steps 53 to 68, all the data outputs DO to D7 of PROM 92 are low thereby inhibiting charging and de-energising the fans. When the data output D6 goes low, flipflop 120 will beset providing the 0 output of flipflop 119 is high with the result that the ready lamp will be energised.

For steps 69, 70 PROM 92 is programmed so that its data outputs D4,:D6 and D7 are high so that charging proceeds at current level 14 aMd for step 71 the data output D6 is high so that the fansr-ernain energised. From step 72 tow, also outputs ar-elow so that char*ino is inhibited ' From steps 88 to 119 the data outputs D5, D6, D7 of PROM 92 are high so that charging proceeds at current level IS and for step 120 the D6 output is high so that the fans only are energised. From steps 121 to 136 all outputs of PROM 92 are low so that charging is inhibited and the fans are de-energised.

For steps 137 and 138,thedata outputs D4,D6and D7 are high so that charging proceeds at current level 14 and for step 139 the data output D6 only is high so that the fans are energised. From steps 140 to 143 all outputs of PROM 92 are low.

At step 144 the data output DO goes high thereby setting flip-flop 117 and triggering monostables 105, 106. The binary number 111 will now be supplied to the address inputs A7, A6, A5 of PROM 90. When so addressed this PROM is programmed so that its data outputs will be set to decimal 128. Consequently a return is made to step 128 and the programme continues to operate between steps 128 and 144 until the charging system is disconnected from the battery.

If a fault occurs so that a binary number other than 001,011, 111 is supplied to the address inputs A7, A6, A5 of PROM 90, this PROM is programmed so that the decimal number 146 is present at its output thereby causing a jump to step 146. PROM 92 is programmed so that with its inputs set to decimal 146 all its outputs are low and further charging is inhibited.

In the charging system described above, the time spent in the first phase is used as an indication of the state of discharge. In a modification, gassing of the traction battery is monitored and the time which elapses before gassing reaches a preset level is used as an indication of the state of discharge for the purpose of determining the overcharge which is given to the battery in the third phase.

Also, in the charging system described above, the overcharge given to the battery in the third phase is determined by adjusting the time spent in the third phase. By way of modification the overcharge may be determined by adjusting the charging current used in the third phase or by adjusting both the charging current used in the third phase and the time spent in the third phase. Adjusting the charging current provides the advantage that the third phase is performed at lower currents for lower states of discharge and consequently at greater efficiency as the amount of gassing is reduced.

Claims (9)

1. A battery charging system comprising a battery, means for supplying current to the battery, means for regulating the current supplied to the battery, means for detecting the battery voltage, and means for automatically controlling each charging cycle, each charging cycle comprising a first phase which is terminated when the battery voltage exceeds a predetermined value, a second phase which is terminated when the battery voltage exceeds a second predetermined value, and a third phase in which the battery is given an over-charge the value of which is determined in accordance with the depth of discharge of the battery at the commencement of charging.

2. A battery charging system as claimed in Claim 1 in which the value of the overcharge supplied in the third phase is determined by varying the period of the third phase in accordance with the time spent in the first phase.

3. A battery charging system as claimed in Claim 2 in which the control means comprise a clock, a programme counter driven by the clock, a first memory addressed by the counter and providing signals to the current regulating means, a first latch responsive to the counter output arranged to be clocked at the end of the first phase, a second latch responsive to the voltage detector means, and a second memory addressed by the first and second latches and arranged to preset the counter at the commencement of at least the second and third phases.

4. A battery charging system as claimed in Claim 1 in which the value of the over-charge is determined by varying the charging current at which the overcharge is supplied.

5. A battery charging system as claimed in any one of the preceding claims in which the first and second phases are each terminated at the end of a respective predetermined period if such period expires before the battery voltage reaches the respective predetermined value and where one or both such phases has been so terminated the third phase is omitted.

6. A battery charging system as claimed in any one of the preceding claims in which each of the first, second and third phases is performed at a constant current, the value of such current being stepwise reduced at the end of the first and second phases.

7. A method of charging a battery in which the charging cycle includes a first phase which is terminated when the battery voltage reaches a predetermined value, a second phase which is terminated when the battery voltage reaches a second predetermined value, and a third phase in which the battery is given an over-charge the value of which is determined in accordance with the depth of discharge of the battery at the commencement of charging.

8. A battery charging system substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

9. A method of charging a battery substantially as hereinbefore described with reference to and as shown in the accompanying drawings.