GB2079093A - Infra-red sensor array - Google Patents

Abstract

Each sensor 1 of an array of infra-red sensors on a single chip is accompanied by a switch 2 whereby the sensor may be connected to an output lead. As described a shift register 3, also on the chip, sequentially opens the switches column-by-column, to cause the outputs from the associated sensors to be fed via row conductors to integrators 6 external to the chip. <IMAGE>

Description

SPECIFICATION Infra-red image sensing An infra-red image sensor may comprise an array of photo-voltaic detectors the signals from which are scanned to form a sequence of picture element signals. By way of example the detectors may comprise Cadmium Mercury Telluride (CMT) elements or Indium antimonide elements arrayed on a monolithic silicon wafer.

In order to achieve an acceptable signal-tonoise ratio from such a sensor, the charge carriers from the detectors have to be summed or integrated over a period of time.

However, the image to be sensed by the sensor will generally comprise a spatial distribution of relatively tiny temperature differences on top of a high "pedestal" of background radiation-this is particularly true of the 8-14 micron wavelength band with which the present invention is primarily, although not exclusively, concerned.

In view of the above problem, it has been proposed to provide capacitive signal storage in the form of heavily doped sites within the silicon wafer on which the detectors are arranged. Each detector is coupled to a respective one of these sites and, for each detector/ capacitor combination, there is also formed in sensor and to provide supplementary storage sites. However, the supplementation achieved is still very small, particularly for the 8-14 micron band. Because of this, information has to be read out of the device at a high rate, of the order of 1 to 5 MHz, and passed to a digital frame store wherein several successive signal samples originating from each detector are summed before being passed at the usual t.v. frame rate (50 Hz) to the destination apparatus e.g. a pattern recognition or coordinate indicating device.

In view of the above problem, it has been proposed to provide capacitive signal storate in the form of heavily doped sites within the silicon wafer on which the detectors are arranged. Each detector is coupled to a respective one of these sites and, for each detector/capacitor combination, there is also formed in the wafer a gate or barrier, i.e. a control element which may be represented on a circuit diagram as a field-effect transistor. A shaft register is arranged to lower columns of the barriers (or turn on the FETs in effect) in turn whereby the signals from the associated column of detector/capacitor combinations is fed out to a series of output terminals of the sensor. While each column is accessible to these output terminals, they are scanned by a multiplexing device to thereby build up the serial train of picture element signals.This proposal may be very much less affected by the problems associated with the first-mentioned proposal but there is a limit to the amount by which the charge storage capacity of silicon can be increased by doping. This limit is such that information still has to be read-out of the sensor at a faster rate than the eventual frame rate and additional integration by means of a frame store provided.

With both proposals, the sensor can be provided with what is called background suppression circuitry which, in effect, operates to allow only some of the charge developed in each detector to flow out therefrom and dumps the remainder. Such circuitry however seriously complicates the construction of the sensor and, in addition, there is a design problem in fitting it in to a tiny and already overcrowded chip.

According to one aspect of this invention, there is provided an infra-red image sensor comprising, on a semi-conductor wafer, an array of infra-red detector elements and, at sites within the wafer, a corresponding array of controllable barriers connected directly to respective ones of the detectors for passing the output signals from the detectors in sequence to output terminals of the sensor, the wafer not being provided with any augmented charge storage capacity other than that which may arise as a consequence of the formation of said barriers.

According to another aspect of this invention, there is provided, in combination, an infra-red image sensor comprising an array of infra-red detector elements and a corresponding array of controllable barriers connected between respective ones of the detectors and output terminals of the sensor and a plurality of discrete analogue integrators connected to said output terminals for receiving signals from the detectors via said barriers.

According to a third aspect of the invention, there is provided, in combination, an infra-red image sensor comprising an array of infra-red detector elements and a corresponding array of controllable barriers connected to respective ones of the detectors, a plurality of analogue integrators, and means for receiving signals from the integrators and analysing, at the end of a predetermined frame period, the pattern of signals originating from the detectors, the combination further including control means for determining said frame period and for controlling said barriers such that each detector is connected to an integrator only once during each said frame period.

The barriers may be controlled by a shaft register which is preferably formed in said silicon wafer if the latter is present.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawing, in which: Figure 1 is a simplified circuit diagram of an infra-red image sensor in combination with a series of discrete analogue integrators, and Figure 2 is a block diagram of an infra-red image sensing system.

The detector comprises a silicon wafer sup porting a layer of cadmium-mercury-telluride which has been diced to form an array of infra-red sensitive diodes 1 only some of which are shown in the drawing. By way of example, the array might comprise 32 rows and 32 columns making 1024 diodes in all.

Within the silicon wafer there are formed a series of field effect transistors 2, one for each diode 1, and a shift register 3 and, in addition, the detector is provided with an arrangement of conductor paths 4 and 5. For each row of diodes 1 there is a corresponding conductor path 4 and for each column of diodes there is also a corresponding conductor path 5. One end of each path 5 is conected to the output of a respective corresponding stage of the shift register 3 while each path 4 leads to a respective output terminal of the detector chip and, via this terminal, is connected to the input of a respective integrator 6. The diodes in each row thereof are connected via the source-drain paths of the corresponding fieldeffect transistors 2 to the corresponding conductor path 4.The gates of the field-effect transistors in each column thereof are connected to the corresponding path 5.

Each integrator 6 may be a simple active device comprising an operational amplifier with an input resistor and a feedback capacitor. In addition however, the integrators are provided with any suitable means for periodically discharging them. By way of example, such means could comprise, for each integrator, an electronic switch 7 connected in parallel with the feedback capacitor as shown in the drawing.

The outputs from the integrators 6 are fed to a multiplexer 8 as shown in Fig. 2 which is able to scan the outputs in sequence and feed the resultant series of signals to an analogue to digital converter 9. The output of the converter 9 is connected to a data processor 10.

In operation, the shift register is controlled so as to switch-on the columns of field effect transistors in turn. When the transistors of any column are switched on, the diodes 1 associated with that column become connected to corresponding ones of the paths 4 and hence to corresponding ones of the integrators 6.

The clocking rate of the shift register 3 is such that each column of diodes 1 is operable to feed current to the integrators 6 for a much longer penod than has hitherto been known.

By way of example, this period may be about 500 Secs. During each such period, the integratos 6 sum the outputs from the diodes and are then scanned by the multiplexer 8.

Then the switches 7 are closed to zeroise the integrators and the shift register is clocked so that the next column of diodes are conected to the integrators 6. This sequence continues so that the output of the analogue to digital converter 9 comprises a series of digital signals each representing a picture element as seen by one of the diodes 1. If each column is selected by shift-register 3 for 500 y Sec, the total frame time will be around 1/50 of sec. The shift register does not have to operate very quickly and so can be made by say a monolithic silicon technique. The data processor 10 may be a known pattern recognition device or a device which detects an increase in the radiation falling on a particular part of the sensor and gives the coordinates thereof in relation to the array.

As may be seen, the illustrated embodiment of the image sensor is not provided with any additional on-chip charge storage (other than that inherent in the diodes themselves). Instead, all the storage required to give an acceptable signal to noise ratio for the device is provided by the integrators 6. Further, because the use of the integrators 6 makes it unnecessary, the illustrated embodiment is not provided with any on-chip back ground suppression circuitry.

Each of the detectors 1 is connected to an integrator 6 once during each predetermined frame period associated with the data processor 10, i.e. no frame store is provided to receive and sum several signal samples from the same detector during any one frame period. Sunchronisation of the operation of the shift register comprised in the detector chip with the operation of zeroising switches 7, the multiplexer 8 and the processing device 10 may be achieved by suitable clock signal connections from the device 10 as shown in Fig. 2.

The detector elements 1 may be photovoltaic elements other than CMT ones, for example they may comprise the aforementioned Indium antimonide.

Claims (8)

1. An infra-red image sensor comprising, on a semiconductor wafer, an array of infrared detector elements and, at sites within the wafer, a corresponding array of controllable barriers connected directly to respective ones of the detectors for passing the output signals from the detectors in sequence to output terminals of the sensor, the wafer not being provided with any augmented charge storage capacity other than that which may arise asa consequence of the formation of said barriers.

2. A sensor according to claim 1, including a shift register operable for controlling said barriers.

3. A sensor according to claim 2, wherein' said shift register is formed in said wafer.

4. A combination of an infra-red image sensor comprising an array of infra-red detector elements and a corresponding array of controllable barriers connected between respective ones of the detectors and output terminals of the sensor and a plurality of discrete analogue integrators connected to said output terminals for receiving signals from the detectors via said barriers.

5. A combination of an infra-red image sensor comprising an array of infra-red detector elements and a corresponding array of controllable barriers connected to respective ones of the detectors, a plurality of analogue integrators, and means for receiving signals from the integrators and analysing, at the end of a predetermined frame period, the pattern of signals originating from the detectors, the combination further including control means for determining said frame period and for controlling said barriers such that each detector is connected to an integrator only once during each said frame period.

6. A combination according to claim 4 or 5, including a shift register operable for con trolling said barriers.

7. An infra-red image sensor substantially as hereinbefore described with reference to Fig. 1 of the accompanying drawing.

8. A combination including an infra-red image sensor and a plurality of analogue integrators, the combination being substan tially as hereinbefore described with reference to the accompanying drawing.

The drawings originally filed were informal: to the accompanying drawing.