GB2078030A

GB2078030A - Protected servomechanism

Info

Publication number: GB2078030A
Application number: GB8115851A
Authority: GB
Original assignee: Burroughs Corp
Current assignee: Unisys Corp
Priority date: 1980-06-14
Filing date: 1981-05-22
Publication date: 1981-12-23
Also published as: GB2078030B

Abstract

A head positioning servomechanism 12 for positioning a head in a data storage file is protected against uncontrolled acceleration by the provision of a saturation detector (14, 16 and 22) monitoring the output level of an inhibitable power amplifier (10) and providing, to a timer (23 and 26) an output indicative of saturation of the amplifier 10, the timer (23 and 26) responding to the detector output by providing an inhibiting input to the amplifier 10 in the event of saturation persisting continuously for longer than a predetermined period. <IMAGE>

Description

SPECIFICATION Protected servomechanism The present invention relates to a positioning servomechanism. More particularly, the present invention relates to a positioning servomechanism operating between endstops, where a high speed collision with the endstops would damage the servomechanism itself or the equipment being positioned. Still more particularly, the present invention relates to the style of servomechanism which is used to position a radially mobile transducer over data storage tracks in a disc file. In greatest particularly, the present invention relates to an externally controlled servomechanism in a disc file where provision is made to avoid damage in the event of the external controller, or the servomechanism itself, developing a fault condition.

The use of servomechanism to position radially mobile read/write heads over data storage tracks, on discs in disc files is a well known art. The head is moved between endstops representing the least and greatest radii of its range. The read/write head is generally fragile, and is mounted on flimsy flexures.

In the event of the servomechanism causing the head to collide violently with either of its endstop positions, the resultant short stopping distance, with attendantly high deceleration forces, may cause damage to the head, the head flexures, of the servomechanism actuator itself. In addition, there is usually provided a head unloading ramp, up which the head is parked when removed from the surface of the disc. Collision of the head with this ramp at high speed places the head in extreme risk of sustaining damage.

The trend towards higher performance disc files has resulted in the abandoning of relatively safe but slow stepping motor head positioning servomechanisms in favour of faster magnetic linear or rotary actuators, where a force proportional to current positions the head under the control of positional feedback information and externally applied demand and control signals. Should any fault develop in the servomechanism or the equipment providing demand and control signals, then there is a risk that the actuator will be accelerated uncontrolably towards one or other of its endstops. The relatively high cost of heads renders an original fault, most probably the result of a low cost failure, an unexpectedly costly fault to repair by necessitating the replacement of heads.

It is also the trend that microprocessors are used to command and control head positioning servomechanisms. Should malfunction or external influence disrupt the operation of the microprocessor, it is quite capable of entering a series of random, uncontrolled states in which commands may be sent to the servomechanism which, if obeyed, would result in damage and destruction.

It is an object of the present invention to provide a servomechanism with protecting apparatus whereby the drive signals resulting from a fault condition in either the servomechanism itself or the external controller thereto may be overridden in the event of their being likely to cause damage, and the action of the servomechanism rendered harmless.

The invention consists in a positioning servomechanism comprising: A power amplifier providing motive energy to a position-controlled load, An inhibitor for causing said amplifier to cease providing said motive energy in response to a control input.

A monitor having the output level of said amplifier coupled as its input, said monitor being operable to compare said output level against an upper limit and a lower limit, to provide an output indicative of said level having been outside said upper or lower limits for longer than a predetermined period, and to provide said output as said control input to said inhibitor, such that, upon receipt of said output from said monitor, said inhibitor causes said amplifier to cease providing said motive energy.

In a preferred embodiment of the present invention, a power amplifier, part of a positioning servomechanism, has its outputs monitored for positive and negative saturation levels, and if either of these levels persists for longer than a predetermined period, the power amplifier is disabled, and kept disabled until externally re-enabled.

The operation of the present invention, together with further aims and objectives thereon, will be further understood by consideration of the following description in conjunction with the appended drawing, in which: Figure 1 shows the system of a preferred embodiment of the present invention.

An inhibitable power amplifier 10, being part of a positioning servomechanism is provided with an inhibiting input on its inhibiting connector 28 which, when logically true, allows the amplifier 10 to function normally, but when logically false, disables and shuts down the amplifier 10 bringing and holding its output to zero.

The amplifier 10 delivers its output, within its function as part of a positioning servomechanism, to the coil of the servomechanism actuator 12. The servomechanism, shown here only in part, also includes a positional feedback transducer, and compensation and control elements, all well known in the art and constituting no part of the instant invention.

The output of the power ampligier 10 is also delivered as an input to a positive saturation comparator 14 and a negative saturation comparator 16.

The positive saturation comparator 14 is provided, on its inverting input 18 with a positive reference voltage, just a little less in magnitude than the output voltage of the power amplifier 10 when it is saturated in the positive direction. The output of the positive saturation comparator 14 is logically false if the output of the power amplifier 10 is less positive than the positive reference voltage, and logically true, indicatively of positive saturation, if the output of the power amplifier 10 is more positive than the positive reference voltage.

In a precisely similar manner, the output of the power amplifier 10 is monitored for negative satura tion by the negative saturation comparator 16. This comparator 16 is provided, on its non-invertin input 20, with a negative reference voltage which is a little less in magnitude than the output of the power amplifier 10 when it is saturated in the negative direction. The negative saturation comparator 16 provides an output, indicatively of negative saturation of the power amplifier 10, which is logically true if and only if the output of the power amplifier 10 is more negative than the negative reference voltage.

The outputs of the positive and negative saturation comparators 14 & 16 are coupled as simultaneous inputs to an OR gate 22, whose output is true if either of its inputs is logically true. The output of the OR gate 22 being logicall true is thus indicative of the output of the power amplifier 10 being in either positive or negative saturation.

The output of the OR gate 22 is coupled simultaneously as the triggering input and the resetting input to a positive edge triggered monostable timer 24, which is reset by a logically false level being presented at its resetting input 23. Whenever the output of the OR gate 22 is logically false, the monostable timer 24 is pre-emptively reset, so that its inverted output 25 assumes a true level. Whenever the output of the OR gate is logically true, the monostable timer 24 ceases to be reset, and is triggered into its timeout operation by the rising edge of the logically false to logically true transition of the output of the OR gate 22, presented at the triggering input 21. Whenever the timing cycle is in progress, the output 25 of the monostable 24 assumes a logically false condition.At the end of a timing period, the output 25 of the monostable 24 reverts to a logically true condition. A timing cycle is terminated by the act of resetting the monostable 24.

The output 25 of the monostable 24 is provided as the clocking input to a positive edge triggered, D-type flipflop 26 the output of the OR gate 22 is also provided as the data input to the D-type flipflop 26.

Whenever a logically false to logically true transition occurs on its clocking input, the D-type flipflop 26 provides and holds, as its output 27 the logical inverse of the signal provided at its data input at the instant of the clocking transition.

The output 27 of the D-type 26 is provided as the resetting input to a set/reset flipflop 32. An externally provided setting input connector 30 is coupled to the setting input of the set/reset flipflop 32. The output of the set/resetflipflop 32 assumes and retains a logically false value whenever its resetting input is taken logically false, and assumes and retains a logically true value whenever its setting input is taken logically false.

The output of the setlreset flipflop 32 is coupled to the inhibiting input of the power amplifier 10.

In the operation of the preferred embodiment, the output of the set/reset flipflop 32 is firstly made logically true by the application of a resetting signal on the external connector 30 in the logically false condition. This signal is thereafter returned to the logically true condition, the output of the set/reset flipflop 32 remaining in a logically true condition, thus enabling the operation of the power amplifier 10. At any time thereafter, should the output of the power amplifier 10 become more positive or negative than either of its limits, these being the positive and negative reference voltages, the monostable 24 is triggered into its timeout.

The output 25 of the monostable 24, in triggering, goes from logically true to logically false. Should the output of the OR gate 22 return to a false condition before the end of the timeout, the output 25 of the monostable 24 is instantly reset, going from logically false to logically true. The true to false transition triggers the D-type flipflop 26 which presents, as its output, the inverse of the output of the OR gate 22. - Since the output of the OR gate 22 is logically false, having just reset the monostable 24, the clocked output of the D-type flipflop 26 is logically true. The true level at the output 27 of the D-type flipflop 26 does not set the set/reset flipflop 32, and the action of the power amplifier is thus maintained if the power amplifier 10 comes out of saturation before the end of the timeout period.

The output 25 of the monostable 24 also goes automatically from logically false to logically true at the end of the timeout cycle. If the amplifier 10 remains in saturation for more than the timeout period, the output of the OR gate 22 is still logically true at the instant the output of the monostable changes. The D-type flipflop 26 is triggered by the change, and in clocking through the inverse of the output of the OR gate 22, provides a logically false output. The logically false output of the D-type flipflop 26 causes the set/reset flipflop 32 to be reset, and so provide and retain a logically false output.

The logically false output of the set/resetflipflop 32 disables the power amplifer 10 beginning and holding the power amplifier 10 output to zero, and thus removing all drive to the actuator 12. The power amplifier 10 remains thus shutdown until an external resetting signal of the logically false value is applied to the setting input of the set/reset flipflop 32.

The value of the timeout of the monostable 24 is selected to be longer than any period of saturation anticipated in the normal operation of the servomechanism, and is thus related to the unity gain frequency and damping factor of the servo mechanism.

It is to be appreciated that many variant embodiments exist. In particular the comparators 14 & 16 are replaceable by numerous other types of devices, and the voltage levels for comparison are selectable as being other than saturation levels. The externally provided setting signal may originate from a manual switch or some monitoring device. The logically false condition of the output of the set/reset flipflop 32 may be used to activate indication of a shutdown;.

The set/reset flipflop 32 may be omitted, and the output 27 of the D-type flipflop 26 taken directly to the inhibiting input of the amplifier. The D-type flipflop may be replaced by a sequential logic network.

Claims

1. A positioning servomechanism comprising: A power amplifier providing motive energy to a position-controlled load, An inhibitor for causing said amplifier to cease providing said motive energy in response to á control input.

A monitor having the output level of said amplifier coupled as its input, said monitor being operable to compare said output level against an upper limit and a lower limit, to provide an output indicative of said level having been outside said upper or lower limits for longer than a predetermined period, and to provide said output as said control input to said inhibitor, such that, upon receipt of said output from said monitor, said inhibitor causes said amplifier to cease provid ing said motive energy.

2. A servomechanism, as claimed in claim 1, wherein said monitor comprises, a first comparator, with said output of said ampli fier coupled to its comparison input, said upper limit coupled to its reference input, and providing output indicative of said output of said amplifier being greater than said upper limit, a second comparator, also with said output of said amplifier coupled to its comparison input, said lower limit coupled to its reference input, and providing output indicative of said output of said amplifier being less than said lower limit, a timer, to which said outputs of said comparators are coupled as inputs initiated by the provision of output by either of said comparators, reset by both comparators simultaneously providing no output, and providing an output indicate of predetermined time interval, after said initiation, neither having elapsed or been reset, and, a logic network, to which the outputs of said comparators and said timer are coupled as inputs, and which provides output in the event of the loss of said indication by said timer whilst either of said comparators is still providing output, said output of said logic network being provided as the output of said monitor.

3. A servomechanism, as claimed in claim 2, wherein said logic network includes, as its output element, a resettable latch, said latch being set on the first occurrence of said loss of said indication of said timer when either of said comparators is still provid ing output, said output of said latch being provided as the output of said logic network, and said latch being reset by an externally coupled resetting signal.

4. A servomechanism, as claimed in claim 1, wherein said monitor includes, as its output ele ment, a resettable latch, said latch being set on the first occurrence output of said amplifier having been outwith said limits for longer than said predeterined period, said output of said latch being provided as the output of said monitor, and said latch being reset by an externally coupled resetting signal.

5. A servomechanism, as claimed in claim 3 wherein said output of said latch is externalised from said servomechanism to provide activation for electrical, aural or visual indication of a shutdown condition being in progress on said amplifier.

6. A servomechanism, as claimed in claim 4, wherein said output of said latch is externalised from said servomechanism to provide activation for electrical, aural orvisual indication of a shutdown condition being in progress on said amplifier.

7. A servomechanism, as claimed in claim 5, wherein said external resetting signal is coupled via manually operable resetting means.

8. A servomechanism, as claimed in claim 6, wherein said external resetting signal is coupled via manually operable resetting means.

9. A servomechanism as claimed in claim 7, used to position a radially mobile transducer over rotating, memory storage media in a disc file.

10. A servomechanism, as claimed in claim 8, used to position a radially mobile transducer over rotating memory storage media in a disc file.

11. A servomechanism substantially as hereinbefore described with reference to, and as illustrated in, the accompanying diagrammatic drawings.

12. Any features of novelty, taken singly or in combination, of the servomechanism as hereinbefore described with reference to the accompanying diagrammatic drawings.