GB2075803A - Delay modulation coding system - Google Patents

Abstract

A delay modulation coding system is disclosed which transmits control information by converting each control signal (FB) to a control message which includes a predefined delay modulation code violation. Preferably a frame boundary control signal message includes a sequence of a logical '1' and a logical zero data bits followed by two "no-transition" data bits, these latter comprising the delay modulation code violation.

Description

SPECIFICATION Delay modulation coding system This invention relates to a delay modulation coding system.

Delay modulation is a self-clocking code (a code from which the data clock can be recovered) which is used to encode binary data using a two-level output signal. The encoding scheme is configured so that each bit cell (bit period) of the encoded data signal is divided into two segments and signal transitions occur at the midpoint of the cell if the data bit associated with that cell is a one. No transition occurs if the data bit for the cell is a zero unless this zero data bit is immediately following a previous zero data bit, then a transition will occur at the cell leading boundary. Thus, for any two delay modula tion encoded data bits there exist four half-cell intervals which yield 16 possible transition combina tions. However, the above-described delay modula tion coding law reduces these 16 possible combina tions to six actual valid code combinations.

As with all data transmission systems, a signifi cant aspect of encoding a signal is the generation of some sort of unique set of control signals, such as a framing signal which defines the boundaries of a block of data. Many prior art schemes have been employed to provide a framing signal and one of these is discussed in U.S. Patent No. 4,161,719 which teaches the employment of a framing pattern of six consecutive one bits to designate the end of a frame.

This use of such a predefined data signal to accom plish framing has the disadvantage that it limits the allowable sequences of data messages in order to obtain a unique framing pattern which minimizes the probability that this sequence of bits would repre sent a valid data message. Thus, the process of selecting the number of bits to be used to provide a control message represents a trade-off between the amount of data message space this control message occupies and the impact of a selected bit pattern on the set of allowable possible data messages. Thus, the framing system of the recited patent, in order to have a minimal impact on allowable data messages, suffers the disadvantages of occupying a significant portion of the data transmission with a control message which represents the framing pattern.

According to the present invention there is pro vided a delay modulation coding system for providing a control signal message for a delay modulated coded data message, in which the control signal message includes at least one delay modulation code violation.

The coding system of the present invention over comes the disadvantages of prior art data transmis sion systems by employing the inherent flexibility of the delay modulation coding scheme as well as other similar coding schemes such as Manchester coding to implement a control signal coding system.

In particular, since, as mentioned above, there are 16 possible transition combinations for two encoded data bits and the delay modulation coding law permits only six actual valid code combinations, there exist ten possible transition combinations (which are code violations) to convey control signals/information such as the framing signal.

The coding system of the present invention makes use of this inherent capability in the delay modulation coding law to produce a control signal coding scheme. In particular, control signal transmission is accomplished by generating a delay modulation encoded control message containing a predefined code violation and incorporating this control message into the data message. This control message is easily detectable and does not require a significant number of data bits to be realizable. A practical arrangement is disclosed hereinbelow which requires only four bit cells to guarantee an easily detectable and predefinable delay modulation code violation. The use of less than four bit cells for a control message is possible but the disclosed scheme is easily understood and also highly reliable.

Thus, both various length data messages as well as uniform length data messages can be transmitted without requiring a significant number of data bits to provide control signal transmission.

An exemplary embodiment of the invention will now be described, reference being made to the accompanying drawings, in which: Figure 1 is a block schematic diagram of a delay modulation coding system in accordance with the present invention; and Figure 2 illustrates a set of timing diagrams for the circuit disclosed in Figure 1.

In the delay modulation coding system disclosed in Figure 1, delay modulation coding apparatus 118 is used in transmitter 100 to delay modulation encode an incoming non-return-to-zero data signal (NRZ DATA). Included in transmitter 100 is control signal translation circuit 103 which, for example, encodes a framing signal (FB) into a delay modulation encoded control message. This control message is then incorporated into the data message in the appropriate location. The resultant encoded signal (DATA) is applied to a transmission medium 101 which carries the delay modulation encoded signals to their destination, such as a receiver circuit 102.

The delay modulation encoded signals (DATA) are decoded by receiver circuit 102 to non-return-to-zero format and the control information is detected in and removed from the received signal as will be discussed hereinbelow.

Transmitter 100 of Figure 1 performs two functions, the first being the conversion of an input signal consisting of non-return-to-zero data to a delay modulated encoded data message and the second being the conversion of control signals/ information, such as a framing signal, into a delay modulation encoded control message, and incorporating this control message into the data message to indicate, for example, when the end or beginning of a frame of data occurs. Receiver circuit 102 of Figure 1 performs the reciprocal functions of transmitter 100 in this scheme.

Figure 2 provides a series of signal waveforms which are indicative of the operation of this circuit. In particular, the first line of Figure 2 illustrates the system clock signal (waveform CLK) which is generated by the clock circuit (not shown) of transmitter 100. This clock signal is applied both to the input of Exclusive-OR gate 105 and to translation circuit 103 of transmitter 100. Translation circuit 103 remains inactive, having a low output on leads INSD and INHX, during the normal transmission of data and is operatively enabled by any one of a plurality of control signals to generate and insert a unique control message into the data stream at the appropriate time. Thus, OR gate 104 acts effectively as a conductor, passing on to its output terminal whatevear signal appears atthe one of its two inputterminals that is connected to buffer 119.Thus, the incoming non-return-to-zero data (NRZ DATA) which is applied to one ofthe input terminals of OR gate 104 by buffer 119 will betransmitted unchanged by OR gate 104to one of the input terminals of Exclusive-OR gate 105.

Similarly, OR gate 106 has one of its two input terminals connected to translation circuit 103 and acts effectively as a conductor as long as translation circuit 103 is inactive. Non-return-to-zero data such as that illustrated on line 12 of Figure 2 (waveform NRZ DATA) which is shown as a receiver waveform but is also applicable as a transmitter waveform which can be directly applied to the input terminal of OR gate 104 or, as shown in Figure 1,would be typically stored in buffer 119 and then applied to the inputterminal of OR gate 104. Gate 104 passes these signals unchanged to one input terminal of Exclusive-OR gate 105, whose other input terminal is connected to the clock circuit (not shown) of transmitter 100.Exclusive-OR gate 105 transmits the data to OR gate 106 where it is again passed unchanged to the clock input of D type flip-flop 107, which flip-flop is connected in a standard delay modulation coding configuration. The Q output of D type flip-flop 107 drives lead DATA with the delay modulation encoded signals.

Translation circuit 103 has a plurality of input terminals, (Pto FB) each of which typically would be connected to a different control lead in the circuitry (not shown) which is associated with transmitter 100 and which circuitry is forwarding the data to be transmitted. Translation circuit 103 functions both to convert a control signal appearing on one of its input terminals to a unique delay modulation encoded control message and this is incorporated into the data message being delay modulation coded by coding circuit 118 of transmitter 100. To illustrate the operation of this apparatus, assume that a frame boundary control signal is applied to the input terminal of translation circuit 103, which terminal is labeled FB on Figure 1.Translation circuit 103 is activated by the application of this enable pulse signal on lead FB and generates the required framing control signals which are delay modulation encoded by coding circuit 118 into a control message. For illustrative purposes, a framing control message comprising the following data bks. one, zero, no transition, no transition - is used to provide a unique framing control message as can be seen from line 6 of Figure 2 (wavefrom FRAMING). This control message has the interesting characteristic of providing a transition at the midpoint of the first bit cell, and thereafter no transitions occur for the duration of the control message. In this fashion, a guaranteed three and one-half bit cell period of no transitions is inserted into the data stream.The insertion of the two no transition bit cells is a direct violation ofthe delay modulation coding scheme and as such is easily detected. The selection of this unique bit pattern which is a delay modulation code violation was arbitrary and the leading one and zero data bits were selected for the ease of circuit design and control message detection. The use of two periods of no transition following the one and zero bits provides not only the code violation but also a double length period of constant signal, thereby minimizing the possibility of a noise pulse in the data stream duplicating the unique control message.

Returning to the description of Figure 1; when the frame boundary pulse signal is applied to the FB input terminal of translation circuit 103, the unique framing signal is generated and applied to the input terminals of OR gates 104 and 106 via leads INSD and INHX respectively to thereby insert the required framing information into the data stream. The use of D type flip-flops 120 to 123 accomplishes this as can be seen from the voltage waveforms appearing on lines 2,3,4 and 6 of Figure 2. The frame boundary signal (waveform FB) goes low during the last bit of the data message, and when the data message is complete, the low to high signal transition on lead FB toggles D type flip-flop 120. The output of D type flip-flop 120 appears on lead INSD and serves to generate a 1 output pulse signal on lead DATA via gates 104to 106 and D type flip-flop 107.This is accomplished by the high signal pulse on lead INSD being transmitted unchanged by OR gate 104 to one input terminal of Exclusive-OR gate 105. This pulse signal, in conjunction with the clock signal appearing on lead CLK, causes Exclusive-OR gate 105 to generate a high output pulse signal, which signal is transmitted by OR gate 106 to D type flip-flop 107.

This pulse signal causes D type flip-flop 107 to toggle at the midpoint of the CLK cycle, producing the delay modulation encoded 1 output as indicated by the waveform on line 6 of Figure 2 which waveform is labeled FRAMING. The pulse signal appearing on lead INSD is applied to D type flip-flops 121 to 123 in the succeeding three clock cycles, causing OR gate 124 to produce the waveform appearing on line 4 of Figure 2, which waveform is labeled INHX to indicate the lead on which this signal appears. This two clock period (or bit cell) duration pulse serves to disable OR gate 106 for all three clock periods, thereby producing an output signal (via D type flip-flop 107) on lead DATA as indicated by the waveform on line 6 of Figure 2, which waveform is labeled FRAMING. At the completion of this control message (framing signal), translation circuit 103 becomes inactive and coding circuit 118 resumes coding the input signals (NRZ DATA) into delay modulation encoded output signals (DATA). The combined signals of data message plus framing control message are illustrated by the waveform on line 7 of Figure 2, which waveform is labeled DATA+FRAMING, and it is this signal that is carried by transmission medium 101 to receiver circuit 102.

Transmission medium 101 can be any apparatus interconnecting transmitter 100 and receiver 102 and, for the present purposes, can be considered to be a single wire. Thus, the data signal carried by transmission medium 101 is applied to the D input of D type flip-flop 109 and also to the reference input (REF) of phase locked loop 108 of receiver circuit 102.

Phase locked loop 108 is a well-known clock detection circuit and functions to generate an output clock signal (2F CLK) which drives the remaining circuitry of receiver 102. Flip-flop 109 is a D type flip-flop and is used to remove signal degradation inherent in the transmission medium. Thus, D type flip-flop 109 removes edge jitter and regenerates a two level binary waveform, which activates pulse forming circuitry which is comprised of gates 110 through 112. This pulse forming circuitry is a well-known configuration and, in response to a change at the input of gate 110, generates a pulse signal at the output of gate 112 equal in duration to the cumulative switching times of inverters 110 and 111.This is illustrated in line 10 of Figure 2 where it can be seen that a pulse is formed on lead EDGE as the transition occurs in the data signal (DATA) applied to the input of receiver 102. These pulses appearing on lead edge are applied to the reset input of four-bit binary counter 113, which counter is driven bythe clock signal 2F CLK generated by phase locked loop 108.

Four-bit binary counter 113 is part of decoder 125, which circuit functions to detect control messages appearing on lead DATA. Four bit binary counter 113 detects a frame boundary signal by simply counting to determine when a sufficient length of time has elapsed wherein no transitions have occurred in the incoming data stream. Since each time a pulse appears on lead EDGE, the four-bit binary counter 113 will be reset, the counter never reaches the full eight count unless a framing control message is present in the data stream.Thus, when a bit pattern of "one, zero, no transition, no transition" appears on lead DATA at the input of receiver 102, no EDGE pulses are generated for three and one-half bit cell intervals and four-bit binary counter 113 (as can be seen from Figure 2), is enabled to count to the full limit of eight counts and an output signal is generated on the 8 output of the counter (lead FB), which output indicates the frame boundary of the data message. Once this output signal is generated, the counter will be reset and the frame boundary signal removed from lead FB as soon as a transition occurs in the data and, as can be seen from Figure 2, all outputs of the four-bit binary counter 113 return to zero as soon as a pulse is generated on lead EDGE.

While the frame boundary determination circuitry is monitoring lead EDGE, additional circuitry comprised offlip-flops 114,116,117 and AND gate 115 decode the signals appearing on lead EDGE and convert the resultant information to non-return-tozero data which is the output of receiver 102 (lead NRZ DATA); In particular, flip-flop 114 halves the frequency of the clock signal generated by phase locked loop 108 and applies this signal to one input terminal of AND gate 115, the other input terminal of which is connected to lead EDGE. AND gate 115 is activated each time a pulse appears on lead EDGE and the output of AND gate 115 drives flip-flop 116 to produce a signal for lead DCOUT, which signal is shown on Figure 2 on line 11 (waveform DCOUT).

The bit timing relationship between the pulses appearing on lead EDGE and the clock signal is such that flip-flop 1.16 generates an output pulse only when a pulse appears on lead EDGE in the middle of the clock interval. Since, in delay modulation coding, only a one data bit produces a transition in the middle of the clock interval, this circuit arrangement produces a signal on lead DCOUT only when a one data bit has been received and at all other times no output is supplied. Flip-flop 117 is a D type flip-flop which converts the pulses appearing on lead DCOUT to non-return-to-zero data format in well known fashion.

Thus, the circuitry illustrated in Figure 1 has been particularly designed and works with the particular control message scheme that has been selected for framing. The use of the above-described framing pattern generates a three and one-half bit cell interval of no transitions which enables a simple four-bit binary counterto be used to detectthe framing control message. The circuit described illustrates the principle of the present invention, but it should be appreciated that other designs could be used both with this and with different control message bit patterns. In particular, a two bit cell control message of two periods of no transitions could be used and would also be easily detectable although other detection circuitry would have to be designed to detect this particular this particular delay modulation code violation. No matter what delay modulation code violations are selected, they will be easily detectable due to the unique nature of the delay modulation coding scheme wherein certain stringent rules must be followed to generate a valid data signal. Thus, the general philisophy of using a code violation in delay modulation coding to provide a framing signal or any other control signal is a scheme of inherent great flexibility and can be adapted to many applications without imposing great limitations on the designer.

While a specific embodiment of the invention has been disclosed, variations in structural detail are possible.

Claims (8)

1. A delay modulation coding system for providing a control signal message for a delay modulated coded data message, in which the control signal message includes at least one delay modulation code violation.

2. A coding system as claimed in claim 1, comprising transmission means for transmitting delay modulated coded data, said data comprising said delay modulated coded data message and said control signal message.

3. ' A coding system as claimed in claim 2, comprising receiver means responsive to the transmitted delay modulated coded data, said receiver means including detector means responsive to said control signal message for affording a control signal indicative thereof.

4. A coding system as claimed in any preceding claim, comprising means for generating the control signal message in response to an applied control signal.

5. A coding system as claimed in claim 4, in which the control signal is a frame boundary control signal and the control signal message is a frame boundary control signal message.

6. A coding system as claimed in claim 5, in which the frame boundary control signal message includes a sequence of a logical 'one' data bit, a logical 'zero' data bit, a no-transition data bit and a no-transition data bit, the no-transition data bits constituting the delay modulation code violation.

7. A coding system as claimed in claim 4,5 or6, in which the means for generating the control signal message is responsive to any one of a plurality of applied control signals for generating a corresponding one of a plurality of control signal messages, each of said control signal messages including at least one delay modulation code violation.

8. - A coding system substantially as hereinbefore described with reference to the accompanying drawings.