GB2075802A

GB2075802A - Network access device

Info

Publication number: GB2075802A
Application number: GB8109010A
Authority: GB
Original assignee: Control Data Corp
Current assignee: Control Data Corp
Priority date: 1980-05-12
Filing date: 1981-03-23
Publication date: 1981-11-18
Also published as: AU538148B2; DE3118847A1; JPS578841A; AU6935081A; SE8102937L; FR2482391A1; GB2075802B; CA1170739A; SE451165B

Abstract

A network access device comprises: a data set (14,18,20,22) adapted to be connected to a data network; a trunk control unit (16,24,26,28) adapted to be connected to said data set for bidirectional communication into and out of said network and for transmitting command messages and for receiving response messages; a trunk control interface (30) adapted to be connected to said trunk control unit and for buffering of data; a network access device internal bus (32) adapted to be connected to said trunk control interface; a network access device processor (34) connected with said internal bus for controlling said trunk control interface and trunk control unit; an internal network access device memory (36) connected with said internal bus; and a device interface (40) connected with said internal bus for communication through said trunk control interface to said trunk control unit and to said data network through said data set and having an output device channel (42) adapted for connection to a computer device. <IMAGE>

Description

SPECIFICATION Network access device This invention relates to network access devices.

High performance computer systems operating at modern, high-speed data rates must provide for complex communication protocols when connected in a network pattern. This invention relates to a device which provide for connection between a computer device of some sort and a network system.

The type of computer device which may be connected through a network access device according to the present invention may consist of a computer mainframe, a computer main memory, or any accessory or peripheral device conventionally used with a computer system.

Typical prior art communication devices for interconnecting computer devices with network systems primarily provide for sending messages, receiving messages and acknowledging receipt of the message. The present invention provides for a higher level of logic beyond that of acknowledgement of messages. The present invention provides for a message response protocol which indicates the type of activity or action taken upon receipt of a message.

According to one aspect of the present invention there is provided a network access device comprising: a data set adapted to be connected to a data network; a trunk control unit adapted to be connected to said data set for bi-directional communication into and out of said network and for transmitting command messages and for receiving response messages; a trunk control interface adapted to be connected to said trunk control unit and for buffering of data; a network access device internal bus adapted to be connected to said trunk control interface; a network access device processor connected with said internal bus for controlling said trunk control interface and trunk control unit; an internal network access device memory connected with said internal bus; and a device interface connected with said internal bus for communication through said trunk control interface to said trunk control unit and to said data network through said data set and having an output device channel adapted for connection to a computer device.

According to another aspect of the present invention there is provided a network access device comprising: data set means for connection with a data network; interface means for connection with a computer device; network access device processor having stored the programme sequences for controlling hardware functions within said network access device; trunk control unit means for connection between said interface means and said data set means wherein said trunk control unit means is comprised-of bi-directional data transmission means, said trunk control unit including means for converting serial data input streams to parallel bytes to form data words on receipt of incoming messages and to convert outgoing data words into parallel bytes and serial data on outgoing messages and buffer means for interconnection with said interface device.

According to a further aspect of the present invention there is provided a network access device comprising; a data set adapted to be connected to a data network; trunk control unit means adapted to be connected to said data set for bi-directional communication into and out of said network for transmitting command messages and for receiving response messages, so that for each command message received the response message provides status information about the receiving network access device; a trunk control interface adapted to be connected to said trunk control unit and for buffering of data, said trunk control interface including a control latch for receiving status information from said trunk control unit with respect to the mode of operation of said trunk control unit; a network access device internal bus adapted to be connected to said trunk control interface; a network access device processor connected with said internal bus for controlling said trunk control interface and trunk control unit; an internal network access device memory connected with said internal bus; and a device interface connected with said internal bus for communication through said trunk control interface to said trunk control. unit and to said data network through said data set and having an output device channel adapted for connection to a computer device.

The following is a brief discussion to explain the present invention recited in the preceding paragraphs, but the invention is not limited thereto.

Both the trunk control unit and the trunk control interface depend on microprocessor control for various functions and a control-ware memory for providing instructions to the microprocessor.

The trunk control interface coordinates, transmits and receives operations between trunk control units and an internal buffer memory.

The trunk control interface enables the selected trunk control~ unit to deliver incoming messages to the buffer memory and issues commands to a selected trunk control unit to transmit a message on the data trunk.

The trunk control interface responds to microprocessor commands by returning status and interrupt signals which signify the passage of messages between the buffer memory and the trunk control unit. A trunk control unit is enabled for message receiving by the trunk control interface and a received message may be passed to the buffer memory by way of the trunk control interface. A trunk control unit in the transmitting enabled condition may transmit a message coming from memory.

A trunk control interface may be enabled in the transmit and receive mode simultaneously and if a contention situation occurs, the receive mode pre vails.

The trunk control unit interfaces a bit serial trunk data set or modem (modulator - demodulator) to the bit parallel trunk control interface. The trunk control unit performs data trunk level protocol functions and ensures that a response message is always returned to a correctly received.command message. The trunk control unit is always synchronized to the data trunk for transmitting command messages. A trunk con trol unit is enabled to receive messages by the trunk control interface and will pass the received messages to the trunk control interface and (1) if a response message, release the data trunk and (2) if a command message, wait for a micropressorsignal by way of the trunk control interface to send a response message.If a signal to send a response message is not forthcoming, the trunk control unit will generate and send an error response message.

The data network operates on a time slot system.

A trunk control unit when it is enabled to transmit a command message must wait for its particular time slot on the data trunk before it can transmit. If a command message for the particular access device appears on the trunk before the transmit slot time, or appears on another trunk enabled for receive, it is accepted by the trunk control interface and the transmit command is discarded. The network access device microprocessor then must resubmit the transmit message if it is still appropriate.

Command messages are accepted from the data trunk by the trunk control unit and passed to memory through the trunk control interface. After transferring the message into memory, the trunk control interface interrupts the microprocessor control. The trunk control unit and trunk control interface wait for the microprocessor to provide a send response signal. The trunk control unit holds the data trunk active while waiting for this signal. The microprocessor control determines the proper response message and signals the trunk control interface to send that response.

The trunk control unit will always return a response message to a command message correctly received and addressed to it. The response message normally originates in microprocessor memory, but can originate within the trunk control unit when the trunk control unit is not enabled for reception by the trunk control interface, when the trunk control unit is enabled butthe trunk control interface is busy, and when the interval timer times out without a send response signal from the microprocessor.

The response status message indicates which of these conditions exist. A command message can be sent from a trunk control unit only during the transmit time slot. If however, a command message arrives before the transmit time, on any of the enabled receive trunks, then the hardware will perform the receive and discard the transmit message.

There are three different modes of communication between pairs of network access devices. Each mode is tailored to a specific work function to effectively use the data trunk and network access device resources. Each command message and response message always occur in pairs.

The first mode of operation consists of one command-response message pair. A control message is directed to the device and has a meaning or function defined by a higher level protocol or a flow control message is directed to the network access device processor.

The second mode is a two command-response message set used fortransmission of data. The first command identifies the data path and the buffer size required. The receiving network access device re turns to acknowledged signal and enters the data streaming mode if the data transfer is permissible.

The sending network access device then immediate ly transmits the data and a closing acknowledgment is returned at which time both network access devices exit the data streaming mode. If the receiv ing network access device cannot accept data, it will return a negative signal and remain in a non-data streaming mode. The data trunk is captured by the pair of network access devices until the final acknow ledgmentsignal is returned.

The third mode is a special form of data transfer in which data trunk multiplexing is eliminated by capturing the data trunk in a streaming mode for the entire duration of a large data transfer. Consequent ly, total trunk bandwidth is allocated to the path capturing the trunk. Two useful results are obtained. First, the data path transfer rate is max imum since trunk loading has been eliminated and protocol usage of the trunk which is a form of operating overhead is minimised. Secondly, all other network access devices on the data trunk have been suspended momentarily from use of the trunk.

Each message contains several blocks of information in coded fields. Each message includes a header which will be explained in detail later.

Each message contains information defining the function of the message and a message sequence number which is incremented for each message sent. The body of the message is dependent upon the type of command message being sent. For example response messages have no body contents to the message.

A negative response message is generated by the microprocessor. Such a message can be a response to any command message. A negative response informs the sending unit of the command message that the resources necessary to process the com mand are not available. The sending unit must not attempt another transmission of the same type until notified that it is allowed to do so. A NAK response message instructs the sending network access device to discontinue sending traffic destined for this particular unit. A WAITNAK response instructs the sending network access device to hold all traffic destined for the receiving network access device until a status change message is sent indicating that buffer resources are available so that the rejected transmission may be retried. The status change message is unique in one respect. The status change message can be rejected the same way as any other command message but the sender of the status change message must wait a predetermined time priod to retry the same mess#age and not wait for its -own status change message before retransmitting.

Due to the nature of this message the retry sequence is infinite.

A message transmission retry must occur when there is a message transmission abnormality. A transmission abnormality occurs when no response is forthcoming to the command message sent. The main reasons for a no response are: (1) a nonexistent network access device is addressed, (2) the command message is garbled on the data trunk causing the destination field to address a nonexistent network access device or there is a check sum error at the receiving unit in which case no answer back is sent or (3) the command message is received correctly and a response message is transmitted but is garbled on the data trunk. When a transmission abnormality occurs, the command message is retransmitted using the same message sequence number up to a predetermined number of times until a response message is received.If a response message is never received after a number of retries, a fatal error has occurred in the system.

What occurs in response to a fatal error depends on the type of command message sent. During the retry process, the microprocessor control will not attempt to send any other command message to the particular receiving unit. However, the particular sending unit will accept incoming command messages.

Every response message includes a status indication of the responding network access device. One of these status bits may be a trunk control interface busy bit. This bit signals that, although the command message was received by the destination trunk control unit correctly, it could not be passed onto the buffer memory. Hence the response returned is likewise not from a microprocessor control but is generated internally to the trunk control unit.

Since the network access device processor at the destination did not receive the command, the command must be retransmitted. Assuming that the remainder of the response status is correct, the command message would be queued for retry by the sending unit. The retransmissions will occur until accepted by the destination network access device or until a fatal error occurs. Other command messages may be sent during the interval between transmission retries.

A destination fatal error signal may be transmitted indicating, for example, that the associated computer device is not operating or other similar fatal errors at a destination location. A command message is not retransmitted when a fatal error message is returned as the response message.

A A fatal message error is one which is caused by a hardware error during the transmission of a trunk command response pair. These errors can be caused by network access device failures including the trunk control interface or the trunk control unit, data set failures or of complete failure of the network access device. These are error conditions which can be reported by the trunk control interface and trunk control unit hardware by status or interrupt messages. The fatal message errors are considered fatal after the retry sequence occurs unsuccessfully a number of times.

If fatal error occurs while transmitting a user control message, the message is returned to the device via the control message queue. A status bit within the message header indicates the message could not be delivered. A fatal error while transmitting data on an established data path causes the path to be terminated. All resources allocated to that data path are released and the device is notified of the fatal error.

Each message includes a header frame check sequence (FCS) immediately following the length of message field. The frame check sequence field serves to detect errors induced by the transmission data link and to validate the transmission accuracy.

The frame check sequence results from a mathema tical computation on the digital value of all binary bits in the frame following the frames synchronization sequence. The process is known as cyclic redundancy checking using a particular generator polynomial. The remainder value in the transmitter for the polynomial is initialised to all ones before a frame is transmitted. The binary value of the transmission is premultiplied by a predetermined factor and then divided by the generator polynomial.

Integer quotient values are ignored in the transmitter since the complement of the resulting remainder value, high order bit first, is sent as the frame check sequence field. At the receiver the initial remainder is preset to all ones and the same process is applied to the serial incoming bits. In the absence of transmission errors, the final remainder is a predetermined value. The receiver will discard a message not having that predetermined remainder value.

Subsequent retransmission of the discarded message is under the control of error recovery procedures.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 is a block diagram of a network access device according to the present invention; Figure 2 is a block diagram showing the use of a network access device according to the present invention together with various computer devices in a data network.

Figures 3A, 3B, 3C and 3D represent a schematic block diagram of a trunk control unit of a network access device according to the present invention for Figures 3A, 3B and 3C are arranged in left to right order with Figure 3D beneath 3B; Figures 3Eand 3Fschematically show a command and response message structure, respectively, of a network access device according to the present invention; Figures 4A and 4B are details of the block diagrams of Figures 3Ato 3D.

Figures 5A and 5B are detailed schematic diagrams of a portion of the device shown in Figures 3A to 3D and are to be seen in left to right order with Figures 5A on the left; Figures 6A and 6B show details of the network access device in Figures 3A to 3D and to be taken in left to right order with Figure 6A on the left; Figures 7A, 7B, 7C and 7D also show details of the network access device shown in Figures 3A to 3D and are to be taken with Figures 7A and 7B in left to right order on the top and Figure 7C and 7D in left to right order beneath Figures 7A and 7B; Figures 8A and 8B show further details of the network access device shown in Figures 3A to 3D with Figure 8A to be taken to the left of Figure 8B; ; Figure 8C is a detail of a portion of the network access device shown in Figures 3A to 3D.

Figures 9A, 9B, 9C and 9D again# show details of the portion of the network access device shown in Figures 3A to 3D and are to be taken with Figures 9A and 9B on the top in left to right order with Figures 9C and 9D in left to right order beneath Figures 9A and 9B.

Figures IOA, 10B, 10C and 700 show yet further details of portions of the device shown in Figures 3A to 3D and are to be taken with Figures 10A and 10B in left to right order and Figures 108 and 10C in left to right order beneath Figures 10A and 1 OB; Figures 11A, 11B and 11C show details of a portion of the device shown in Figures 3Ato 3D with Figures 1 1A and 11 B to be seen in leftto right order with Figure 11C placed below Figures 11A; and Figures 12A, 12B, 12C, 12D and 12E represent a schematic block diagram of a trunk control interface device of the network access device shown in Figure 1 and are to be seen with Figures 12A and 12B in left to right order with Figure 1 2C below Figure 1 2A and Figure 12D below Figure 12C, and Figure 12E to the right of 12C and below 128.

Referring now to Figure 1, a network access device 10 according to the present invention is shown connected with a data trunk 12. The network access device consists of at least one data set 14 connected between the data trunk 12 and at least one trunk control unit 16. Other data sets 18, 20, 22 may be provided connected to the same or other datatrunks.

Each of data sets 18, 20, 22 would be connected with its own trunk control unit 24, 26, 28 respectively. The trunk control unit 16 is connected to a trunk control interface 30 as would be any othertrunk control units in the same network access device. The trunk control interface 30 is connected to an internal data bus 32 which is connected to a network access device microprocessor 34, a buffer memory 36, a maintenance interface 38 for diagnostic maintenance routines and a device interface 40. The device interface 40 provides a data channel 42 to be connected to a computer mainframe, a computer memory or any peripheral or auxillarysequipment to be associated with a computer system.

Referring to Figure 2, a plurality of network access devices according to the present invention are shown in various situations to illustrate their use in a computer communication network system. A computer mainframe 50, which may illustratively be a Control Data Corporation CYBER 176 computer, may have several device channels 42 connected with a plurality of network access devices 52a, 52b, 52c, 52d and 52e. Each of network access devices 52a to 52d has at least two data sets and trunk control units. The network access device 52e is shown to have only one trunk control unit and one data set. Five data trunks 60, 62, 64, 66 and 68 are provided. Thus, the network access devices 52a to 52d are connected to a pair of data trunks as shown in Figure 2.All of the network access devices 52a to 52e are connected to the data trunk 60, for example, while only the network access device 52a has a connection to the data trunk 68.

A A network access device 70 having two trunk control units is shown connected to the data trunks 60, 68 and connected with a mass memory disk storage system by means of a device interface 72 with disk storage units 74, 76, 78, 80. Similarly a network access device 82 is connected with data trunks 60,66 and to a second device interface 84 for the same mass memory disk storage system.consist ing of disk storage units-74, 76, 78,.80.

To represent a similar, but separate, combination, network access devices 86, 88 are connected respec tively with interfaces 90,92 and with a mass memory disk storage system consisting of disk storage units 94, 96, 97, 98. Finally, a network access device 99 may be connected with a special purpose station 95 which may have any predetermined described func tion. Thus, the various network access devices according to the present invention can facilitate a variety of intercommunications between the various devices shown connected to the data network and to other devices which may be located elsewhere but not shown on the data network.It is possible for example for the disk storage unit 94 to communicate through the interface 90, the network access device 86 through the data trunk 64 to the network access device 52c and to the computer mainframe 50.

However, the same network access device 86 may also set up a communication link with the computer mainframe 50 by means of the data trunk 60 and the network access device 52e. The possibilities are obviously too numerous to be described but should become apparent by inspection of Figure 2.

Referring generally now to Figures 3A, 38, 3C and 3D, a block schematic diagram of the trunk control unit of a network access device according to the present invention is shown. Referring now to Figure 3B, a data communications trunk 100 (trunk 12 in Figure 1), is connected to a modem or data set 101.

The data set 101 supplies serial data on a data trunk 102 to the serial to a parallel interface logic unit 103.

Clock data is provided from the data set to the logic unit 103 on a bus 104.

Control signals are provided on buses 105,106 from the data set 101 to the logic unit 103. The bus 106 conveys a channel active signal indicating that there is activity on the data channel and a Data Ready signal is provided on the bus 105 to indicate that data is to be conveyed into the logic unit 103.

The logic unit 103 takes serial clock data provided on the bus 104 and generates various clock signals provided to further logic units in the trunk control unit as described later. The logic unit 103 assembles serial data in 8 bit bytes for transmission to further elements of the trunk control unit as will be de scribed further.

A FCS clock 107 is used to run a FSC register 120 (Figure 3C) for both generating and checking. The FCS clock is also used for clocking data bits into a trunk control unit data memory input buffer 121. The byte clock on a bus 108 is used to control a byte input holding register 123 which assembles for the first time the serial data bits into the 8 bit bytes.

A PROM clock 109 and a test clock 115 are the two clocks that run a trunk control unit sequencer 124 (Figure 3A). A channel active signal 111, from the logic unit 103, a Data Ready signal 113, the byte clock 708 and a clear to send signal 114 are ali connected as inputs to a test multiplex switch 130. The output of the switch 130 is connected by a bus 131 as an input to the PROM 124. The logic unit 103 produces the channel active signal 111 which is sent through the multiplex switch 130 to the trunk control unit microcode. The microcode then realises that a message is to be received off the data trunk and the logic unit 103 causes the clock to the sequencer 124 to be stopped until the first zero of a sync byte character is detected by logic unit 103.

Once the first zero of the sync byte character is detected by the logic unit 103, the sequencer 124 in Figure 3A is provided clock signals again which causes the sequencer to be in bit sync with the data coming off the trunk. As the sync byte character comes into logic unit 103, it is then put into byte form at the holding register 123.

From the holding register 123 the data goes to an input bus 140. On this input bus a logical unit decoder 141 determines whether the proper sync character is on the line at that moment. The output 142 of the decoder 141 is fed into the multiplex switch 130 for the trunk control unit microcode to test. The trunk control unit microcode then tests the output of that decoder and if the valid sync character has been detected, microcode will allow the trunk control unit to begin looking at the rest of the message which is coming from the data trunk. As the data is converted into 8 bit bytes at the register 123, the bytes are placed on the bus 140 which also feeds a parity generator 146 through a bus 145. The parity generator generates odd parity for each 8 bit byte.

The output of the parity generator runs to both the input buffer 121 and also to an upper byte parity register 147. The clock which stores each byte of data into the memory 121 comes from an AND gate 148.

The input buffer 121 is also used to assemble 8 bit bytes into 16 bit words. First the upper 8 bits of a word are written into the input buffer and then the lower 8 bits and the two parity bits for each byte are written into the register 123. This necessitates the upper byte parity register 147 which holds the parity of the upper byte until the lower 8 bits are written into register 123. The clock from the AND gate 148 on a bus 149 is used to increment an input counter 150 which is the address of the input buffer memory location which the data word is to be written into.

The bus 149 is also used to increment a word counter 151 which is used to tell how many words have been put into the input buffer. The bus 140 also drives a set of drivers 143. These drivers then drive a large bus 144 which connects to various decoding and logic units. The first byte following the sync character which has previously been discussed is the destination address. The destination address is compared in a logic compare unit 160 against trunk control unit address switches 161. If the output of the compare unit 160 is brought into the multiplex switch 130 on a line 162 and if the trunk control unit address does compare, then this signifies that the message being received off the data trunk is for this designated trunk control unit and thus the rest of the message will be received.

If the output of the compare unit 160 indicates that the message was not to this trunk control unit, the trunk control unit will receive the rest of the header portion of the message to pick up the resync parameters which will be described later on. This is necessary for the trunk contention scheme which is used.

The next byte of data which comes onto the input bus from the drivers 143 is the function code. This function code is loaded by the trunk control unit sequencer into a function register 170. The outputs of the register 170 are then decoded by a decoder 171 into the 8 possible function decodes. The sequencer 124 looks not at each of the function codes individually, it looks at them in groups determined by whether data or an information field is to follow this header field or not.

The next two bytes following the function code are access code bytes. They again come through the drivers 143 and come into a compare network 181 on a bus 180. The function of the access decoder is to match access code switches 182,183,184,185 against the two access code bytes which are received from the trunk.

The access code switches 182, 183 are connected through a tri-state buffer 186 to be used to compare against the first access code which is received.

Access code switches 184,185 go through buffer 187 to the compare unit 181 to compare against the lower or second access code which is received from the trunk. If either of these compares of the two bytes are negative, the trunk control unit will not consider this message to be for it.

The next byte to be received off the trunk is the resync parameter which is loaded by the trunk control unit sequencer 124 into a resync parameter register 145'. It is held there until the trunk control unit has received the complete header portion of the message. If the header has been received with no errors, the output of the register on a line 190 is then loaded by the trunk control unit sequencer into a contention counter 191.

The next byte is the source address. The source address is loaded by the trunk control unit sequencer into what is called a FROM register 192. This specifies the address of the trunk control unit which has sent this message. A multiplexer (MUX) 193 which is connected to the input bus during this receive operation has been connecting each byte of the received data on a bus 194 into the FCS register 120.

Following the source address, the next two bytes of data received in the message are the length count of the information field. The length count is specified as the number of 16 bit words which is contained in the information field following this header field. The input bus which now contains the length bytes connects through the multiplexer 193 into the bus 194 and finally into a length counter. The first byte of the length count is the upper length byte and this goes into a counter 195 while the second byte of the length of count is loaded into a counter 196. Both of these counters are controlled and loaded by the trunk control unit microcode. The output of the length counters is brought into a comparator 197 which determines whether the-length counter is at zero.An output 198 of comparator is brought into the multiplex switch 13D and is used by the trunk control unit microcode to determine if an information field is to follqw this header field because a length field of zero is permitted.

The final two bytes within the header field are the FCS bytes for the header. As these bytes come in on the bus 144 and go through the multiplexer 193 and on to the bus 194, they enter the FCS register 120.

After both FCS bytes have been clocked into the FCS checker, the output of the FCS register is brought into the multiplex switch 130. The output of FCS register 120 is on a line 199. If the output of the FCS register indicates that the header has been received correctly, the trunk control unit microcode will then load the register 145' into the contention counter 191 as previously stated. It will also go on to accept any data field which may follow the header message.

If the trunk control unit, upon receiving a message, detects that the function code indicates that data is to be sent to the memory of the network access device, the trunk control unit will request to connect up to the trunk control interface. Afterthis connection is made, data from the input buffer is fed through tri-state drivers 205 to a bi-directional data bus 206 to the trunk control interface. The bus 206 is an 18 bit path, 16 bits of data with two odd parity bits.

The purpose of the added sync bytes is to allow the receiving trunk control unit time to reset the FCS register 120 and also to allow microcode control time for housekeeping. The two sync bytes are not put into the buffer memory of the trunk control unit.

Following the sync bytes -which are stripped out by the receiving trunk control unit, the data field which follows is enabled into the input buffer 121 and the information also flows through the multiplexer 193 on to the bus 194 and into the FCS register 120. Thus, as the data is input into the input buffer 121, it is also being checked on the FCS register 120.

The trunk control unit sequencer monitors the output 198 of the length counter to determine when all of the data in the information field is received. The sequencer 124 is also monitoring any error conditions which may be connected with the data transfer, it will abort the data transfer anytime any of these abnormal conditions are found. Error lines are lines 200, 201. As the data information field is received in the input buffer 121, the sequencer is monitoring each byte and decrements the length counters through an AND gate 202 which drives a line 203 for each 16 bits of information field which are received.

For each 16 bits of data transferred to the trunk control interface on a bus 206, an output counter 207 is decremented and produces an output on a line 208. Thus the input counter 150, output counter 207 and word counter 151 are used to control the input buffer 121 in a circular manner.

After the length counter has counted down to zero indicating all of the data has been received, the trunk control unit then must check the FCS characters for the received data field. This is done in a similar manner as checking the header FSC. Thus the two bytes following the data field come through the multiplexer 193 onto the bus 194 and into the FCS register 120. After those two bytes are clocked into the FCS register 120, the output on the line 199 indicates to the trunk control unit microcode whether the data field has been received correctly.If during any portion of receivingthe message the trunk control unit has found an error condition, the trunk control unit will terminate the transfer at that point and will transmit a hardware response message back to the sending trunk control unit to indicate the status of the transfer and to convey as much information about the error as possible.

Assuming that the message has been received properly and the data has flowed from the input buffer 121 out through the bus 206 through the trunk control interface and then stored into the network access device memory, the processor then interrogates the received message and will send back a response to the message received. Thus, this text will now describe how a message is transmitted back onto the-data trunk.

Data comes from the memory of the network access device through the bus 206 and into an output buffer 210. This again is an 18 bit word, 16 bits of data with two odd parity bits. The trunk control unit sequencer handles setting up the transfer to the trunk control unit which sent the original command message. The trunk control unit se- quencer brings up a send request signal 211 telling the data set to send a preamble onto the data trunk The logic unit 103 is used to send all ones to the data set which is a marking condition on the trunk. When the data set 101 has sent this preamble, a clearto send signal 212 is returned. The clear to send signal 212 informs the sequencer 124 that it may begin sending the message. The first byte of data to be sent out is the sync byte character. This byte originates out of a PROM register 220.The output of the register 220 is put on an output bus 221 and is fed into the logic unit 103. This logic is also used as the parallel to serial logic and thus the sync byte which is loaded into the register is shifted out in serial fashion to provide a send data signal 213 to the data set 101. Along with the send data signal 213 a return clock signal 214 is sent to the data set. This clock is generated in the trunk control unit and is used by the data set 101 to determine the bit times of the-data being sent.

The information which follows would now typically come from the network access device memory assuming this is a processor generated response.

The data which has come from the trunk control interface on the bus 206 and which was loaded into the output buffer 210 is now broken into eight bit bytes by tri-state drivers 225. Tri-state drivers 225 cause the upper 8 bits of the word from memory to be put on the output bus 221 while output drivers 226 enable the lower 8 bits of the word from memory to be enabled onto the output bus 221. The first byte following the sync byte comes from the FROM register 192. The output of the FROM register is connected to the output bus 221 and goes into the logic unit 103 and is sent serially to the data set 101.

The output bus 221 is also connected through the multiplexer 193 and onto the bus 194 and into the FCS register 120. This logic is now being used to generate the FCS for the header field which is being sent.

The next byte of data following the destination address which has come from the FROM register 192 is the response function byte. This response function byte comes from the PROM register 220 and goes onto the output bus 221 and again to the logic unit 103 and out to the data set 101 as well as going to the FCS register 120.

The next bytes to go out are the three status bytes, parameter 1, parameter 2, and parameter 3. These three status bytes are sent out as part of a response message.

The next byte of data following parameter 3 is the source address. This comes from the address switches 161 and is enabled onto the output bus 221 and out to the data set.

Following the source address is the length field for the information field which is to be transmitted with this response message. A response message in which there is no data field will be discussed first.

This is also called a hardware response which the trunk control unit can generate independent of the rest of the network access device hardware. If the hardware response is to be sent, the length field is set to zero. The zeros for the two bytes of length field come from the PROM memory 220 and are enabled to the output bus 221 through the logic unit 103 and out to the data set. Following the length field is the FCS for the header field. The two bytes of FCS are enabled from lines 230, 231 onto the output bus 221 and through the logic unit 103 and out to the data set 101.

Following the FCS, assuming this was a hardware response, there will be no data field but the trunk control unit will send two sync bytes following the header FCS characters. This is to allow the receiving trunk control unit logic time to process the information before the control signals from the data set terminate the transfer. These two sync characters are enabled out of the PROM memory 220 and onto the output bus 221 and are sent to the data set.

Now assuming the case of a response coming from the processor, the header field will be sent as described previously from the first sync byte through the source address. However, the length field will now come from the network access device memory through the trunk control interface onto the bus 206 and into the output buffer 210. The upper byte of the length field is enabled through the tri-state drivers 225 to the output bus 221 and is loaded into the logic unit 203 to be sent to the data set 101. The lower length byte is enabled through the drivers 226 to the output bus 221 and is sent through the logic unit 203 to the data set. These two bytes of length field also are enabled through the multiplexer 193 to the length counters 195, 196 and to the FCS register 120.

Following the length field the trunk control unit again enables the header FCS characters from the FCS register 120, lines 230, 231 onto the output bus 221 to send these header FCS characters to the data set. Following the FCS characters the trunk control unit again sends two sync characters which originate from the PROM memory 220 onto the output bus 221 and onto the data set.

Following that the information field is transferred.

Prior to that transfer the FCS register 120-is reset to all ones in order to generate the FCS forthe data field. Data will now come from the trunk control interface onto the bus 206 into the output buffer 210.

The upper bytes will then be enabled onto the output bus 221 bythe tri-state drivers 225 while the lower byte will be enabled onto the output bus 221 by the drivers 226. As each 8 bit byte of data is enabled onto the output bus 221, it is strobed into the logic unit 103 and sent to the data set 101. This data also goes through the multiplexer 193 and into the FCS register 120 to generate the FCS for the data. In addition, the length counters 195, 196 are decremented for each 16 bits of data which are sent out. The trunk control unit microcode monitors the output 198 of the comparator 197 to determine when the proper amount of data has been completely transferred. When all of the data has been transferred, the trunk control unit sequencer will enable the data FCS characters from the FCS register 120 onto the lines 230 and 231 to the output bus 221.These bytes will be sent to the data set through the logic unit 103 As data is put onto the output bus 221 from the tri-state drivers 225 and the drivers 226, the parity bits from the output buffer are also enabled onto the output bus 221. A parity checker 240 thus is checking the odd parity for each of the 8-bit bytes which come from the network access device memory. The output of the parity check 240 is supplied to an AND gate 241 which allows the trunk control unit microcode to check only those bytes coming from the network access device memory itself. Eight-bit bytes of data which come internal to the trunk control unit do not have parity appended to them and thus there is no parity on the output bus 221 at those times. Also the AND gate 241 has an input which allows the disabling of the parity check for diagnostic purposes.

The output of the AND gate 241 is then clocked at a register 242 and the clock of the register 242 is the same as the clock which loads the serial to parallel register in the logic unit 103. Thus if there is a parity error on the output bus for the data which is loaded into the serial parallel register, then the register 242 will indicate a parity error on the line 200. This line 200 then feeds back into the multiplexer switch 130.

If an error is detected during the data transfer the transfer will be immediately terminated by the trunk control unit sequencer.

The next kind of message to be discussed is a command message to be transmitted onto the data trunk. This involves using some logic which previously has not been described. In this kind of message most of the data to be sent is coming from the network address device memory. Thus the data comes from the trunk control interface onto the bus 206 and through the output buffer 210 and through the tri-state drivers 225 and the drivers 226. The first word which comes from the trunk control interface will contain the destination address and the function field to be sent through the data set 101.

The next 16-bit word of data which comes into the output buffer 210 will also be transferred to a bus 229 into an access code generator 243. The access code generator 243 is also connected via a bus 188 to the tri-state drivers 186, 187. These tri-state drivers enable the access code switches 182, 183 onto the bus 188 when the upper access code is to be generated and enables switches 184, 185 onto the bus 188 when the lower or second byte of the access code is to be generated. The output of the access code generator 243 is then enabled to the output bus 221 which is then sent out through the logic unit 103 to the data set 101. As before, all information which is put on the output bus 221 is also sent through the multiplexer 193 and into the FCS register 120.

Following the two access code bytes the trunk control unit supplies the resync parameter and the source address. The resync parameter on a line 248 is taken from the trunk control unit parameter or priority switches 246 and is enabled through tri-state drivers 244 onto the output bus 221. The contention counter 191 also receives an input from a trunk content switch 247. The source address comes from the address register 161 and is enabled onto a bus 249 and through a buffer or tri-state drivers 245 to the output bus 221. This indicates which trunk control unit has sent out this message. The information field length are the next two bytes and they will come from the network access device memory through the bus 206, the output buffer 210, the tri-state drivers 225 and the drivers 226 and out to the output bus 221.When the length field of the header is on the output bus 221 being loaded into the logic unit 103, it also goes through the multiplexer 193 onto the bus 194 and is loaded into the length counters 195,196.

Following the length field which specifies how many 16-bit words will be sent following this header, are the FCS characters for the header. These two bytes are enabled as discussed before out of the FCS register 120 and through lines 230, 231 onto the output bus 221. Also following the header FCS will be two sync bytes which come from the PROM register 220. Following the two sync bytes, the information field comes from the trunk control interface through the output buffer 210 and onto the output bus 221. As the information is put on the output bus 221 and loaded into the logic unit 103, it also goes to the FCS register 120 to generate the FCS code for the data field. As the information-ffeld is being transferred, the length counter is decremented one time for every 16 bits of data being sent out.

Thus, when the output 198, which indicates length counter has reached zero, is detected by the trunk control unit sequencer, it signals that the end of the information field has been detected. The trunk control unit will then enable the data FCS bytes from the FCS register 120 onto the output bus 221.

Following the FCS data bytes, there are two sync bytes which originate from the PROM memory 220 onto the output bus 221. These bytes conclude the data command message transfer.

The sequencer 124 is made up of 48 bits from a PROM memory and each of the first 40 of the bits out of the PROM memory are strobed into a holding register 250. The output of this holding register holds one instruction. The output is, in part, used to address the next instruction which is to be executed.

These bits are used to generate controls for which hardware signal is to be tested to make hardware decisions. The output is also used, to generate strobes to clock various registers and to generate enables to enable various registers to the output bus, for example.

One additional input to the tri-state drivers 225, the drivers 226 is a line 251. This line comes from a decode of the holding register 250. It is used to select when data from memory is to be enabled onto the - output bus 221.

Figure 4B relates to the AND gate 141 and is a detailed drawing of the valid sync bit detected gate.

Figure 4A relates to Figure 3B and is a detailed drawing of the input holding register 123 and the drivers 143. Figure 4A also relates to Figure 3C which is the parity generator 146 of Figure 3C. The output pins shown in Figure 4A constitute the bus 144 shown on Figures 3B and 3C. An AND gate 260 shown in Figure 4A, is the gate (not shown on Figure 3C) but'is used to disable passing the parity bit to the input buffer 121 for diagnostic purposes.

The inputs to the input holding register 123, shown in the detailed drawing 4A, are from the logic unit 103. The clock inputs to the input holding register also come from that logic and are clocked by the byte clock. The input holding register 123 converts the data from serial into parallel. The output of this register is input to the AND gate 141 in Figure 4B, which is a valid sync detected gate. This AND gate determines if the first byte in the message received is a valid beginning of a message. Parity is generated at the parity generator 146 to be put on the input bus 140. The drivers 143 drive the input bus.

Figures 5A and 5B describe part of the logic contained within the logic unit 103. Figure 5A shows a register 300 in which Data Ready, one of the signals from the data set 101, indicates that data is being received from the trunk. This register delays the Data Ready signal a various number of clock times at the outputs to provide control signals. One of the outputs goes into an AND/OR gate 306 via a signal path 305. When Data Ready has been de tected, the path 305 will go low causing the gate 306 to output a one which causes a ring counter composed of flip-flops 309,310,311,312 to be cleared.

The flip-flops 309,310,311,312 comprise a ring counter which is used to develop a timing chain from which all of the clocks for the trunk control unit are developed. As described before, when Data Ready comes into the register 300, the path 305 goes low which causes a line 308 to go high which also causes an OR gate 313 to output a low. This causes the ring counterto clear causing all of the Q sides of the flip-flops to become logical ones. AND gates 315, 316 are used to insure that the ring counters are properly set during start up in power up sequences.

The output of the flip-flop 312 is fed back around to the AND/OR gate 306 on a line 317. This line 317 is what is used to complete the ring of the ring counter.

When Data Ready is detected, a one signal is started to shift through a register 301.

An AND gate 304 has as its inputs line 318, which is a Data Ready signal, and the output of an inverter 302 which is a delayed Data Ready signal. The output of the AND gate 304 causes a clear signal to be generated to all of the flip-flops in the ring counter thus insuring that upon Data ready being detected the ring counter is cleared. An output line 320 from the register 301 finally becomes a one after seven clock periods. This enables an upper AND gate 306A of the AND/OR gate 306 to be enabled. This stops the ring counter and it waits for the signal labelled "delayed first zero" to come in from another section of the logic unit 103. The "delayed first zero" signal starts the clock which causes the sequencer 124 to be in byte sync with the data coming in from the trunk.This is necessary because the sequencer tests and manipulates the data from the trunk on a real time basis.

Once the "delayed first zero" signal is detected, the AND gate 306A is made forcing the line 308 to be a zero forcing a line 314 to be a one. This causes the ring counter to start operating once more. As a Q output line 325 of the flip-flop 309 goes to a one, this signal goes to an AND/OR gate 326. This positive going edge is fed back around and comes into the clock input of a flip-flop 328. This sets the pulse width of the clock which is going to be generated out of inverters 330, 331, 332. This clock also becomes one of the inputs to an AND gate 333. Its output runs into a flip-flop 334 whose Q 335 passes through an inverter 336 and is used to determine the pulse width of the Q output of the flip-flop 334.Thus, after the rising pulse edge from the flip-flop 309, a line 324 causes all of the necessary clocks to be generated for the trunk control unit sequencer. Likewise, the rising edge on pin 6 of the flip-flop 309 on a line 340 causes a similar sequence of events to happen. Therefore all the clocks for the sequencer 124 are generated from the pulse edges of the flip-flop 309.

The ring counter is operated by a 50 megahertz clock and is fed into the clock inputs via a line 341.

This causes an 80 nanosecond up and an 80 nanosecond down clockto appear on the output of the flip-flop 312 on a line 342. An OR gate 338 is used to generate a memory clock which is used to write data into the input buffer 121 of Figures 3C. An inverter 337 is used to strobe the test inputs from the multiplexer switch 330 to determine the time when the test is taken.

A flip-flop 350 is used at the en-d of the receive sequence. After the data message has been received, the data set stops sending serial clock and sends only crystal clock. The flip-flop 350 is used to force the ring counter into a reset state and to allow time for the switching to occur before continuing to generate clocks which run the trunk control unit sequencer.

Figures 6A and 6B show, in detail, the function register 170 shown on Figure 3B. A register 370 is loaded from a trunk control unit microcode signal line 371. The inputs to the register 370 come from a trunk control unit input bus 372 which is the same as the bus 144 on Figure 3b. The outputs of the register 370 go to a decoder 375. The decoder 375 decodes bits in the function code which relate to diagnostic functions. These allow various parity generators to be disabled so that parity checkers within the trunk control unit input bus line may be checked.

An output line 391 is the upper bit of the registe-r 370 and is used to determine whether the message is a command message or a response message. If the line 391 is a command message, its level should be zero to enable decoding of a function code. The function field on a response message should contain only this upper bit and no function code should be decoded for a response message. This is done by pin five of a decoder 384 and pin four of decoders 385, 375 being connected to the line 391. The decoder 384 is used to decode functions which control the workings of the network access device processor and the decoder 385 is used to decode functions which transfer data or control the trunk control unit and trunk control interface.

To prevent accidental or unauthorised control of the network access device processor, a line 396, not enabled, going into pin four of the decoder 384 is connected to a switch which is under lock and key which disables the decoder if it is not intended for the trunk control unit to manipulate the network access device processor.

The decoder 385 is used to determine what sort of function the trunk control unit is to perform. An output line.397 is a function which the trunk control unit handles on its own and is a function which can be used to obtain status from the trunk control unit which has been addressed.

A function line 398 is a master clear function which is used to master clear the network access device processor. However this signal must go through an AND gate 389 which again is connected with the enable switch.

Lines 399, along with line 401 from the output of an AND gate 387 form inputs of an AND gate 390 whose output tells the sequenc#er 124 that the message received is going to contain an information field following the header. In this case, the trunk control unit must connect up to the trunk control interface in order to input that data into the network access device memory. An AND gate 386 is used to disable the not Data Ready condition at times when a lost data condition on the trunk is not checked. An AND gate 383 is used to disable the trunk control unit input bus parity bit. This allows checking of the parity checker on the inputtothetrunkcontrol unit memory and thus this is a diagnostic feature which can be. used to verify that the data path is functioning correctly.

AND gates at 380,# 381,382 perform a similar function to the AND gate 383 which was just explained. These gates are used to disable various parity bits in the input bus networks to ensure that the input bus from the trunk control unit all the way through to the network access device memory is functioning correctly and it is to be used with diagnosticfunctions to verify its correct operation.

Figures 7A, B, C and D relate back to the input buffer 121 and the tri-state drivers 205 of the bi-directional data bus lines 206 of Figure 3C. The trunk control unit input bus 140 in drawing 3B comes into Figure 7A in the upper left-hand corner and goes into a parity checker 410. This provides a parity check on the data between the point where it was formed into an 8-bit byte and where it is put into the memory. !f a parity error is detected, an AND gate 436 will clock a flip-flop 438 causing the latter to set indicating a trunk control unit input bus parity error.

This will also turn on a light emitting diode (LED) 439 to give a visual indication.

The trunk control unit input bus goes on from the parity checker 410 to become inputs to the trunk control unit input bufferwhich are RAM memory chips 412,414,416, 418 and 420. The upper byte of a 16-bit word is contained in chips 412,414 whereas the lower byte of a word is contained in chips 416, 418.The two parity bits, one for the upper and one for the lower bit, are contained in the chip 420. Since both parity bits are contained in the same memory, the parity for the upper byte is held in a flip-flop 434 until the lower byte is written. The 8-bit input bus comes into these chips and memory is used to assemble 8-bit bytes into 16-bit words. The output of memory comes out to tri-state drivers 422,424,426.

These tri-state drivers are turned on by the trunk control unit when the trunk control unit is sending to the trunk control interface. These tri-state drivers correspond to tri-state drivers 205 in Figure 3C. The line 206 on Figures 3C corresponds to the outputs of the tri-state drivers 422,424,426. The outputs of the tri-state drivers 422,424, 426 go through two parity checkers, an upper parity checker 428 and a lower parity checker 420. The outputs of these parity checkers go through an OR gate 432. The output of the OR gate 432 becomes an input to a flip-flop 440.

If when the trunk control unit is sending data to the trunk control interface, a parity error is detected on the 16-bit bi-directional bus, then the flip-flop 440 will be set indicating a parity error condition. The tri-state driver 426 sends the upper byte and lower byte parity bits to the trunk control interface as well as the control signal indicating to the trunk control interface when the data is valid on a line 450 in Figure 7D.

Figures 8A and 8B show the controls for the input buffer 121. A flip-flop 500 is used to control the bi-directional data bus 206 between the trunk control unit and trunk control interface. This flip-flop is controlled by the clear to send signal from the data set. This signal is used such that when data is being received, the tri-state drivers 205 is enabled to send data to the trunk control interface. When a message is sent out, the clear to send line will be active and will cause the Q output of the flip-flop 500 to be a zero. If the flip-flop 500 is reset, the tri-state drivers 205 are disabled and the trunk control interface is engaged to send data on the bi-directional data bus 206 to the trunk control unit.

An AND gate 504 has the memory clock as well as an enable line 505 from the sequencer 124 as inputs.

The AND gate 504 allows the trunk control unit sequencer to control what data bytes to put into memory. As stated before, there are two sync bytes between the header and the data field which are not used. The line 505 causes the sequencer to delete - these two characters from the message as it is stored in network access device memory.

The output of the AND gate 504 on a line 532 goes to a flip-flop 526, an AND gate 530 and flip-flop 520.

The line 532 is a clock pulse signal and the flip-flop 526 is a simple divide by two flip-flop which selects either writing to the upper 8-bits of the input buffer or writing to the lower 8-bits of the input buffer. AND gates 528,530 are used along with the outputs of the flip-flop 526 to develop the write signals for the upper and lower parts of the buffer memory. As words are written into the buffer memory, an input control counter 514 is incremented. The input control counter 514 and an output control counter 512 respectively, go through a multiplexer 522 and become the address lines for the trunk control unit input buffer RAM memory chips. The'multiplexer 512 operates on an 80 nanosecond period clock and thus the address is switched from the input counter to the output counter and back again every 80 nanoseconds.This allows a write into the buffer memory and a read out of the buffer memory all within a 160 nanosecond time period which is one byte time on the data trunk. For each word written, the input control counter 514 is incremented and a word counter 516 is also incremented. The memory chips used in the input buffer are 16 words deep.

Therefore the carry input of the word counter 516 goes to the flip-flop 520 and if 16 words of data are written into the buffer, then the flip-flop 520 will be set which will cause a buffer overflow condition to be noted and a light emitting diode (LED) 521 will light as well as sending out a signs indicating this error condition has occurred.

Typical operation would be that as data is put into the memory from the trunk control unit, the trunk control interface would be taking data out of the memory and thus the word counter would never increment up to 16 because the work counter will be decremented each time a 16-bit word is taken out of the buffer. An OR gate 518 simply detects whether the word counter has reached zero. When the word counter is equal to zero it means that no data is left in the trunk control unit input buffer. Trunk control unit diagnostic functions are enabled only on the data portion of a transfer.If the trunk control unit diagnostic functions consist of disabling the various parity generators along the trunk control unit input bus on the header portion of the received message, the message would most likely be disregarded because of these induced errors, and thus a flip-flop 506 along with an AND gate 510 and an inverter 508 are used to disable the decoding of the diagnostic portion until the data field part of the received message has been encountered.

Figures 9A, 9B, 9C and 9D all relate back to Figure 3A. These four figures comprise one part of the trunk control unit sequencer 124. Instruction memory PROMs 124a are shown in Figures 9A and 9C. The output of an instruction memory 124a shown in Figure 9A hold the next address portion of the instruction. Every instruction in the trunk control unit microcode has a next address field and every instruction within the microcode is a jump instruction. Each jump is a decision jump based on the output of the multiplexer switch 130 shown in Figures 9B and 9D. The multiplexer switch 130 shown on those-two figures have hardware bits as inputs. The multiplexer switch is controlled from the instruction memory 124a shown in Figure 9C.The outputs of the FROM memory control which one of the many hardware input bits will be selected to be tested within any one instruction.

An output line 550 of the multiplexer switch 130 is fed to the data input of a flip-flop 551. The clock into the flip-flop 551 is a test clock which is generated from the logic unit 103. This clock determines the time at which the bit to be tested will be strobed. The output of the flip-flop 551 becomes the low order address bit of the next instruction. The decision making capability of this particular sequencer is determined by running the test bit as the lower order address bit and thus either the next address as specified by the outputs of the holding register 250 will have either a low order bit of 0 or 1 depending on the output of the multiplexer switch 130.

The output of the holding- register 250 goes to a parity check network 552 and this checks parity on the 8 bits of the next address field. The microcode is set up such that every 8 bits of instruction has-an odd parity bit associated with it. In Figure 9C, the instruction memory 124a also connects to a register 555. The outputs of the register 555 feed a parity check unit 556. This same scheme is repeated throughout the rest of the trunk control unit sequencer logic.

Every instruction in the trunk control unit microcode is a jump instruction. However, in order to simply sequence through memory, the lower bit of the current instruction address is brought out from the instruction memory 124a into an inverter 560. A line 561 brings that lower bit into the multiplexer switch 130. The instruction memory which selects the multiplexer switch may now test the lowest order bit of the current instruction and the assembler puts the proper bit in that instruction so that the next sequential instruction will be executed. The assembler takes care of putting# in the proper next address in the instruction memory 124a as shown in Figure 9A.

By using the low order bit, sequential operation through memory occurs, although the logic the microcode is actually testing the low order bit.

Lines 565, 566, 567, 568 in Figure 9C and line 580 in Figure 1 OA go to enable one of the five test multiplexers of the multiplexer switch 130. Lines 570, 571, 572 are then used to select which one of the eight input signals to the selected test multiplexer will become the output of the multiplexer switch.

One signal out of all of the input signals to the multiplexer switch becomes the in put to the flip-flop 551.

Referring nowto Figures 10A, 10B, 10Cand 10D, the instruction memories 124A shown on Figures 1 OA and 10C have their outputs connected to the holding register 250. The outputs ofthe holding register is fed to two parity checkers 600, 601. A parity bit is associated with each of these two 8-bit bytes. From the outputs of the holding register, the bits go to decoders 604 to 609 shown in Figures 1 OB and 1 or. The decoders are used to select various registers within the trunk control unit logic and to provide various clock and strobe processes to other registers. All of these decoders provide the interface between the microcode and the hardware.In-Figure 1 0B a flip-flop 610 is used to enable the length counters 195, 106 to count after they have been loaded. A line 615 from a decoder 604 is used to clear the FCS register 120 shown in Figure 3C. The FCS register needs to be set to one before any information is run through the register. A signal line 616 from the decoder 604 is connected to the trunk control interface and is used to provide the interrupt number which the trunk control unit sends to the trunk control interface at the end of an operation. A signal line 617 loads a status register from the trunk control unit into the trunk control interface. A line 618 loads the FROM register 192 shown in Figure3C.

A signal line 619 is used to load the register 145' shown in Figure 3B. A line 620 loads the resync counter and is shown in Figure 3C. A signal line 621 is used to reset the input and output word counters 150,207, 151 in Figure 3C. A signal line 622 is not used. A signal line 623 loads the upper length counter 195 shown in Figure 3c. A signal line 624 loads the lower byte in the length counter 196. A signal line 625 enables the trunk control unit address switches 1.61 onto the output bus 221. A signal line 626 enables the access code onto the output bus 221.

A signal line 627 enables the resync parameter switches 246 ontothe output bus 221. A signal line 628 enables the PROM memory onto the output bus.

A signal line 629 enables the upper or first 8 bits of the FCS onto the output bus 221, and this is shown in Figure 3C as an input to FCS register 120. A signal line 630 is an. input to the FCS register block 120 which enables the second or lower byte of the FCS onto the output bus 221. A signal line 640 enables 8 bits of status information onto the output bus ?21 to be sent to the data trunk. A signal line 641 enables the trunk control unit address register to be enabled onto the output bus 221 to be sent to the data trunk.

A signal line 643 also enables an 8 bit byte of status onto the output bus to be sent to the trunk.

A signal line 649 from the decoder 607 is used to decrement the length counters 195,196 shown in Figure 3C. A signal line 650 is used to clear a latch register which holds various hardware bits which control transmitting and receiving of data. The latch bits will be explained later on in more detail.

A signal line 651 is used in conjunction with the error address register as a clock signal to load the trunk control unit microcode address which has detected an abnormal condition into the error address register. The error address register contains the microcode address which has detected the abnormal condition. This provides a trace mechanism in tracing errors.

A signal line 652.is a clock signal which resets a timer mechanism which the trunk control unit microcode uses to timeout various events. The timer operates from a reset condition. The timer has four time interval lines which the trunk control unit microcode sample to determine when a certain amount of time has elapsed from the time the timer was reset.

A signal line 653 loads the function register 170 shown in Figure 3B. Signal-lines 654, 655,660 are used to convey status information from the trunk control unit to the trunk control interface. Signal lines 673, 672, 671 are used-to control the PROM register 220 shown in Figure 3D. These lines are used to select one of three different bytes which can be selected from the memory register onto the output bus 221. A signal line 674 is the output used to select which of the switches to be gated onto the bus 188 to be used for either comparing access codes or for generating access codes. A line 674 is shown on Figure 3B and is an input to buffer 186.

A signal line 675 is used to enable the output bus 221 to the trunk control interface in order to send status information to the trunk control interface.

Thus, this signal is used along with signal lines 654, 655, 660 to convey status to the trunk control interface. A signal line 676 is used to enable the tri-state drivers 225, 226 to put data onto the output bus 221.

Signal lines 644 to 648,661 to 666 and 667 are not used.

Figures 11A, 11B and 11C detail the sequencer 124 more specifically, the instruction memory, the holding register and an addressable latch. The instruction memory again is shown as 124a on Figures 11A and 11 C. The outputs of the instruction memory are held in a holding register 250. The output lines of the holding register from Figure 1 1A goes to Figure 1 1B where these outputs are used to control the setting and clearing of the addressable latch shown in 118.

The addressable latch has two sections 700 and 701.

The outputs of this addressable latch are control signals to other logic in the trunk control unit which the trunk control unit microcode cannot control at every instruction cycle so these bits are stored in the latch.

The first bit out of the addressable latch section 700 which is on a signal line 702 is the send request.

This is a signal sent to the data set telling the data set that the trunk control unit is requesting to send a message and asking the data set to send a preamble of ones onto the data trunk. In response, the data set sends a clear to send signal.

A A signal line 703 is a transmit request signal sent to the trunk control interface requesting that the trunk control interface connect to the trunk control unit in order to do a transmit. This signal is brought up in response to the trunk control unit detecting a signal from the trunk control interface saying that the trunk control interface has a message to transmit to this trunk control unit trunk. A signal line 704 is also used during a transmit and enables a write timing chain in the trunk control unit hardware which sends out an 8-bit byte which loads every 160 nanoseconds into the parallel to serial register. The timing chain provides all the timing to correctly load the bytes as needed. A flag signal line 705 is an internal signal used by the trunk control unit microcode.The trunk control unit microcode can set this bit and then test it. This is a substitute for subroutining capabilities so that the microcode can decide which of two paths the microcode should take when coming out of a common routine. It is also used to indicate certain error conditions within the microcode. A signal line 706 is the not received request and is similar to the signal line 703 in that it is sent to the trunk control interface. This signal requests the trunk control interface to connect to it because this trunk control unit is receiving a message from the trunk and wants to send forward that received message to the network access device memory.

A signal line 707 is used by the trunk control unit microcode to enable the message being received to be recorded into the trunk control unit input buffer 121. This line 707 goes into the AND gate 148 on Figure 3C, and it is also used to control the clock going into the FCS register 120, also shown on Figure 3C. A signal line 708 is used to enable a master clear function to the trunk control interface when a master clear function is the function command received in a message. A signal line 709 is a status bit which is set when an illegal function command has been detected in a received message.

Thus, status gets sent back as part of the response message indicating to the sender that the function to be executed cannot be executed. Signal lines 710, 711 are controlled by microcode during diagnostic functions. They are used to enable data to be looped back from the output bus to the input bus and back into the trunk control interface. A signal line 712 is a status bit indicating that the trunk control unit microcode has determined that the received message has an FCS error in it. A signal line 713 is another internal flag signal or indicator signal to the microcode which tells the microcode whether it is doing a transmit sequence or whether it is doing a receive sequence. The line 713 is used to decide which path to take once a microcode instruction comes out of a common routine and this acts as a substitute for subroutine functions.

Signal lines 714,715 are used to control the transmitting of data from the trunk control unit output buffer to the output bus 221. A light emitting diode (LED) 740 connected to the latch section 701 is used as an idle indicator. When the LED is on, the microcode is in its idle loop. The trunk control unit microcode will shut the LED off whenever the microcode leaves that loop.

An inverter 741 and AND gates 742,743 are used to write information into either the latch section 700 or the latch section 701. There is a clock input into the gates 742, 743. The other two inputs to gates 742, 743 control which of the latch sections will be written into. Lines 747,748,749,750 control which of the 8 bits will be written and whether the bit will be set or cleared in the addressable latch. The holding register shown in Figure 1 1C simply holds all of the parity bitsforthe instruction memory 124a. All of the parity bits for the instruction memory are held in that holding register.

A flip-flop 760 is used when a 1K instruction memory is used. The trunk control unitwill either accept a 512 instruction or a 1K instruction memory.

If a 1K instruction memory is used, this flip-flop will provide the needed extra address bit to utilise the 1K capability for that particular PROM.

In Figure 1 lathe sections 1,2 and 3 of the instruction memory are used to delay the address which is addressing the instruction memory. The outputs of address register section 2 go to the inputs of the trunk control unit error address register. If an error is detected, the microcode will load the microcode address which detected the abnormal condition.

Referring now to Figures 12A, 12B, 12C, 12D and 12E the trunk control interface is shown on the first four mentioned figures while a universal device interface corresponding to the device interface 40 in Figure 1 is shown on Figure 12E. In each of the figures reference numeral 32 is used to denote the internal network access device data trunk as shown in Figure 1. Rx refers to receive data while Tx refers to transmit data.

Referring now particularly to Figure 12A, Rx data buffer 1 800 receives information from a trunk control unit trunk control interface bus 801. This mechanism synchronizes the connected trunk control unit and network access device memory using buffer registers and the control logic for these buffers or the microcode instruction loop. Rx data buffer 2 802 serves as-a control package mechanism to interlock the Tx and Rx commands. The trunk control interface request word is controlled by the microprocessor Rx programme. The Tx enabled bit, bit 12 and this word, interlock the Tx request word.

The trunk control interface microcode forms the interlock. The processor programme rules are that the Rx programme only changes the request bits in the trunk control interface request word and the Tx programme only changes the request bits in the Tx request word. the Rx parameter and the Tx parameter are therefore also controlled exclusively by the appropriate processor programme.

Referring now to Figures 12B, a memory data register 803 is a hardware mechanism interlocking the control package trunk control unit Rx and Tx enables. The hardware locks out any Tx enables to trunk control units not enabled to receive. This eliminates the problem where two network devices want to transmit to each other and do not want to or forget to permit a receive command. This relates to the rule of the network access device that you must establish a listening return path if transmission is desired. The mechanism of allowing or requesting more than one trunk control unit to transmit the message means that the first trunk control unit that gets a data trunk will transmit the message. Redundant data trunks or do not care which trunk or which user and other commands will allow the work to be accepted and accomplished.A multiplex switch 804 provides one input to the register 803. This-multiplex switch forms a mechanism to hold up orto have the trunkcontrol unit wait for the microprocessorto generate a response for another message. This mechanism also allows the trunk control interface to generate response such as for autodump and diagnostic loop back functions.

Referring again to Figure 12A, the buffers 800,802, respectively, receive data from the trunk control unit on the bus 801. The buffer 800 receives data which is passed through the buffer 802 in a resynchronization process. Thus, the register 802 receives data from the trunk control unit through the buffer 800. The contents of the buffer 800 are immediately loaded into the buffer 802 for transfer to memory.

Referring now to Figure 12B, the-register 803 holds data to be written into the network access device memory 36 as shown in Figure 1. The multiplexer switch 804 provides one input to the register 803; - This multiplexer switch passes the parity bits re ceived from the buffer 802 to the register 803 or in the case of trunk control interface data ge#nerated internally, the multiplexer switch 804 connects the parity bits generated by a parity check and generate logic unit 805 to the register 803.

Referring again to Figure 12A, a Tx data buffer 806 holds data to be transferred to the trunk control unit for transmission. This register performs part of the resyncand buffering functions between the network access device memory and the trunk control unit transmit operation. The output of the buffer 806 is connected through to the bus 801.

Referring again to Figure 12B, a read data register 807 catches and holds data received from the network access device memory for internal use in the trunk control interface or for transfer to the buffer 806 for a trunk control unit data transmit operation.

A multiplexer 808 passes on the parity bits from the register 807 to the register 806, or in the case of trunk control interface internally generated data, it connects the parity generate check logic unit 805 to the register 806 in order to attach proper parity bits to the trunk control interface generated data.

The parity check and generate logic unit 805 checks parity on data received from the trunk control unit or read from network access device memory. In the case of the trunk control interface sending status information or data to the network access device memory or to the trunk control unit, this logic generates the proper parity bits for the data or status information to be sent.

A multiplexer 81.0 connects the parity bits from the buffer 802 or the register 807 to the input of the parity check and generate logic unit 805 in order to perform the proper parity checks. The multiplexer 810 also conditions the parity check and generate logic unit to enable it to generate the proper parity bits for trunk control interface internally generated data. Registers 812,814,816 are status registers which are loaded by the connected trunk control unit in order to, pass on the status information generated by the trunk control unit to network access device memory.A control flag register 818 performs the resynchronization and latch function required by the -trunk control interface to present stable data to the parity check and generate logic unit 805 and to the universal device interface microsequencer test logic.

Trunk control interface status logic 820 is a tri-state bus driver to connect the trunk control interface internal status information to the control flag regis ter 818 input.

A trunk control unit interrupt register 822 is loaded by the connected trunk control unit in order to inform the trunk control interface of the results of the operation which was performed. The code loaded into this register is atso stored into the network access device memory as status information. A trunk control interface test unit 824 is a tri-state bus driver to connect the internal operating status for the trunk and control interface to the control flag register 818.

A trunk control unit latch 830 is a mechanism by which the trunk control interface passes on control and sta#tus information on a bus 831 to the connected trunk control unit on a trunk control unit status bus 832 shown in Figure 12A. A Rx enable and write request logic unit 834 shown in Figure 12B perform the maskfunction of allowing only the receive enabled trunk control unit to be requested to output data to a trunk. This logic unit also latches and holds the request until a trunk control unit connects to the trunk control interface.

Trunk control unit priority and connect logic unit 836 performs contention resolution on a request by two or more trunk control units to connect at the same time to the trunk control interface. The logic to mask out unselected trunk control units or trunk control units not enabled is also performed in this unit. The buffers 800, 802, 806 perform certain logic functions in connection with the data transfer sequence used by the trunk control interface. A waiting flip-flop (not shown) disables the low clock to the device interface register.When the clock is disabled, the data transfer instruction does nothing because the low clock signal is blocked to inhibit the generation of clock signals for the network access device memory request, the length counter and address counters thus preventing the data transfer to orfrorh a trunk control unit Tx or Rx data buffer.

Referring now to Figure 12E which contains the universal device interface or device interface 40 as shown in Figure 1, the tri-state transmitters on a network access device address bus 850 are shown connected to bus 32. The address counter function for the network address device memory addressing is performed by an address counter 852. Similarly, a length counter 854 counts the length of the data message sent. A multiplexer 856 is selected to allow the address or length counter 852 or 854, respectively, to be connected to the bus 32.

An assemble/disassemble register 860 is used by the trunk control interface for testing of bits, tempor ary storage etc. It is not used for the purpose of assembling and disassembling but this type of register is required for this function.

The length counter 854 is used to decrement from a predetermined starting number to determine the length of a data transmit operation or the buffer size limit on an input or receive operation. A shift network 862 permits a shift of 0, 4,8 or 12 places on data passing through it. A bit set/clear flip-flop 864 is used to allow the setting or clearing of bits 8 to 15 from transferring data into a register.

A tri-state transmitter 866 is used to connect a file register 868 to the bus 32. The file register may be a 16 word by 16 bit file register to store operating parameters and status information. A test multiplexer 870 is used to permit the testing of the contents of the register which is then currently enabled into the bus 32.

A PROM transmitter 872 is used by the trunk control interface to force bits 0 to 7 on the bus 32 to zeros or ones when PROM data is selected to the bits 8 to 15 on the bus 32. This is to avoid interference on the bus. Thus, the other section of the transmitter 872 relating to bits 8 to 15 connects PROM data from a PROM 874 to the bus 32.

A microsequencer 876 generates addresses, and contains a data stack for fabricating microcode subroutines and also functions as a test mechanism for performing conditional branches. The PROM 874 is a programmable read only memory for storing control programmes.

An address latch 878 is an addressable latch for use as required by the programming. The go, stop and master clear functions are permanently assigned to the address latch 878. The remainder of the latch is not used by-the trunk control interface. A clock logic unit 880 is a register clock to determine which register data on the bus 32 is to be loaded into. A clock unit 882 generates address and length counter clock signals and permits parallel operation with other register clock signals. A bus select logic unit 884 determines which register or data is to be enabled into the bus 32. A clock unit 886 is a register clock source.

This completes the specific description of hardware elements of the illustrated network access device. The operation of a network access device according to the present invention will now be described.

The bus 32 in Figure 1 is an interconnect link between the various elements of the network access device. Attachments to the bus 32 include the trunk control interface 30, the processor 34, the device interface 40, the memory 36 and the maintenance interface 38. Use of the bus 32 is divided equally among the three active elements: the trunk control interface, the processor 34 and the device interface 40. Bus access is-by time division multiplex with equal access guaranteed for all elements. By way of example, a system according to the present invention may operate on a 320 nanosecond time frame with 106.6 nanosecond apportioned to each device.

Thus within its access time slot, the appropriate active element can access any bus address.

Referring now to the figures, the following symbols are used on various signal lines to denote the following functions. The minus M/C signal indicates that a master clear function was received by a trunk control unit which is enabled to control the network access device or the trunk control interface generated a master clear to the trunk control unit. The minus Rx Data Ready signal loads data from the connected trunk control unit input data buffer into the first trunk control interface input data buffer. The minus trunk control unit Tx Buffer Empty signal informs the trunk control interface that the connected trunk control unit output data buffer can receive data. The Interrupt/Status Enable signal specifies the interrupt sent to the trunk control interface as follows: interrupt zero is an abnormal end Rx command, interrupt one is an abnormal end Rx sequence, interrupt two is an abnormal end Tx sequence, interrupt three is an end of Rx command, interrupt four is an end of Rx sequence, interrupt five is an end of Tx sequence and interrupt six is a stream mode time out warning.

The minus load INT signal latches the three trunk control unit encoded interrupt lines into the trunk control interface interrupt register. The minus status CLK0 signal latches trunk control unit status information into the upper 8 bits of the trunk control interface status one register. The minus status CLK1 signal latches the trunk control unit error address into the lower 8 bits of the trunk control interface status one register. The minus status CLK2 signal latches trunk control unit status information into the trunk control interface status two register.

The minus disable data bus Tx register parity check signal, when active, disables checking parity on data the trunk control interface received from the connected trunk control unit. The minus trunk control unit Rx request signal indicates the requesting trunk control unit has received a header message containing the proper TO address and access code fields and is requesting to be connected to the trunk control interface. The minus trunk control unit Tx request signal indicates that the trunk control unit time slot has come up while the trunk control interface Tx request line was active and the trunk control unit data set has captured the data trunk. The trunk control unit length or word count not equal to zero signal provides the trunk control interface with a a live status of the connected trunk control unit input buffer condition.The minus trunk control interface Tx request signal indicates that the trunk control interface wants to transmit a message to the trunk or perform a processor initiated diagnostic on the trunk control unit receiving the signal. The minus trunk control unit connected signal indicates that this trunk control unit is logically connected to the trunk control interface. Only one trunk control unit may be connected at a time to a trunk control interface. The minus trunk control interface Rx Buffer Empty signal tells the trunk control unit that the trunk control interface first input buffer can receive data. The minus Tx Data Ready signal loads the trunk control unit output buffer with data.

Referring now to Figures 3E and 3F the message field definitions will be discussed in detail. The TO address field is the first 8 bit byte following the synchronization character in the header field. This field defines the logical trunk control unit on the trunk to which the message is directed. Each trunk control unit on the trunk receiving a message compares this field with its own 8 bit logical address.

If they match, the trunk control unit will process the remainder of the header field. If the fields do not match, the trunk control unit does not process the remainder of the header field except to input it to its frame checking (FCS) logic. After receiving the complete header field, the trunk control unit tests the results of the FCS logic to determine if the message was received error free. If no errors occurred, and the message was a command message, the trunk control unit will load the received resync parameter into its resync counter. If an error was detected the message is ignored.

The function field is the second byte following the sync character. The function field has four subfields: response command frame, enable trunk control unit diagnostics, trunk diagnostic functions and command functions. In all cases the TO address and the header frame check test must be correct before any part of the function field is executed.

The command functions are used by the trunk control unit/trunk control interface to control the data link. The command codes are: 0 is resync, 1 is ; master clear, 2 is data command;3-is enable trunk control interface trunk diagnostic command, 4 is autoload, 5 is autodump, 6 is go and 7 is step. The length parameters must equal 0 for command codes 0, 1, 6, and 7. Any data sent with these commands will be lost The trunk control unit must be enabled by the network address device control switch to process commands 1,4,5,6 and 7.

The resync command code is 0. This command is basically a NOP function which can be used to get the hardware status of the trunk control unit/network address device on the data trunk The resync parameter field value is inserted by the transmitting trunk control unit hardware. The only action taken by the trunk control unit in response to this command is to load the received resync parameter into its resync counter and to transmit a hardware status response message.

The master clear command code is 1. When this command is received, the trunk control unit tests the enable network access device control signal which is switch selectable. If the trunk control unit is not enabled to control the network access device, the trunk control unit will perform a resynccommand and will return illegal function status in the hardware response. If the trunk control unit is enabled to control the network access device, and the header FCS has been verified, the trunk control unit will activate the M/C (master clear) line to the trunk control interface for two instruction cycles. The M/C is bi-directional, connecting all four trunk control units and the trunk control interface. This line may be activated by the trunk control interface or any of the trunk control units in order to initiate a master clear function.Each trunk control unit receiving the M/C signal compares with the master clear command decode. This is to prevent the trunk control unit which initiated a master clear command to a trunk from. master clearing itself and being unable to generate a response message to the command. The response message to a master clear command is transmitted after the trunk control unit sends the master clear signal to the trunk control interface. If the trunk control interface is connected at that time, a processor response will be sent or otherwise the trunk control unit will send a hardware response.

When a trunk control unit detects the master clear signal, it will execute its master clear microcode sequence andwill then wait for a predetermined time to receive a command message with which to resync itself with normal trunk operations. If no message is received in this predetermined time, the trunk control unit will send out a trunk resync message and return to its normal idle loop function.

After a master clear, the trunk control interface will accept only the GO, autoload or autodump commands from the connected trunk control unit.

When multiple trunk control units in a network access device are enabled to control the network access device processor, the last trunk control unit which sent a master clear to the trunk control interface will be the only trunk control unit through which the GO, autoload and autodump commands will be accepted. Sending, simultaneously, master clear commands to multiple trunk control units on a network access device is an illegal system function which must be avoided. If one trunk control unit sends a master clear and starts an autoload sequence, there is no way to prevent another trunk control unit from master clearing the first The first autoload sequence being halted will be retryed and then halt the second autoload sequence, etc.

The data command code is 2. The trunk control unit will request to connect to the trunk control interface after the TO address and access code have been received and checked. If the header FCS characters indicatethatthe header field contained an error, the trunk control unit will withdraw its connect request to the trunk control interface and will ignore the message. If the trunk control interface is already connected to the trunk control unit, the trunk control unit will send status to the trunk control interface containing the FCS error status followed by an abnormal end of Rx command interrupt. The trunk control unit will wait for the data set to drop the channel active signal before returning to its idle mode.

If a trunk control unit successfully connects to the trunk control interface and the header is okay, the header and data fields including all FCS characters will be stored into the network access device mem ory starting at the address assigned by the processor. After the trunk control unit has received all the data from the trunk, it will capture the trunk and wait for a predetermined period of time if not in the data streaming mode for the processortrunk control interface to provide a response message. The trunk control unit will send a hardware response if the processor does not provide one.

Any of the following conditions will terminate a data transfer resulting in data following the error being lost: 1. Trunk control unit connected signal drops out, 2. Modem Data Ready signal drops out before trunk control unit data length counter equals 0, 3. Trunk control unit input bus parity error, 4. Trunk control unit/trunk control interface bus Rx parity error, 5. Trunk control interface bus parity error, 6. Trunk control interface detected errnr,'or 7. Trunk control unit input buffer overflow.

If the trunk control unit is unable to connect to the trunk control interface, it will perform a resync function and the trunk control interface not connected status will be sent in the hardware response.

The command codeforthe enabletrunkcontrol interface trunk diagnostics command is 3. The receiving trunk control unit need not be enabled to control the network access device in order to execute this command. The header length parameter may be O 0 only if the diagnostic requires no data to be transferred to the trunk control interface. All of the remaining trunk control unit processing steps for this command are the same as for the GO command.

When the trunk control interface decodes this command, it will then decode the trunk control interface trunk diagnostic function field and determine the diagnostic action to be performed. This is a microp rocessorfunction and will not be described in detail.

The command codeforthe autoload command is 4. If the receiving trunk control unit is not enabled to control the network access device, the trunk control unitwill perform a resyncfunction and will return illegal function status in the hardware response.

The trunk control unit should already be enabled to connect to the trunk control interface due to a master clear command which must precede this command. The trunk control interface then loads the network access device memory starting at 0 with the contents of the information field in this command message. The trunk control interface discards the header and FCS fields. The number of 16 bit words loaded into memory is specified by the length parameters in the header field received for this command. A processor response is sent by the trunk control unit after the trunk control interface inactivates the wait processor response signal. If another autoload command is received, the data is loaded following the last word of the data from the previous autoload command. The GO command or a processor running status signal will terminate the autoload sequence and disallow autoload commands.

The command code for the autodump command is 5. If the receiving trunk control unit is not enabled to control the network address device, the trunk control unit will perform a resync command and will return an illegal function status in the hardware response. If the trunk control unit is enabled to control the network access device, the trunk control unit will request to be connected to the trunk control interface after the header FSC is verified. The trunk control interface will send wait for processor response to the trunk control unit, to prevent it from sending a hardware response message immediately and will connect to the trunk control unit. Once connected the trunk control interface will input the header. The trunk control interface sets up the data transfer from the network access device memory and will clear the wait for response signal.The trunk control unit then transmits a processor response followed by a data field. This response data field is the contents of the network access device memory starting atthe address specified in the second word of the data field. The number of 16 bit words transferred is specified by the first word of the data field of this command. The second word of the data defines the starting address. The trunk control unit will generate and send the FCS characters for the information field.

The GO command code is 6. If the trunk control unit is not enabled to control the network access device, the trunk control unit will perform a resync command and will return illegal function status in the hardware response. If the trunk control unit is enabled to control the network access device, the trunk control unit will request to connect to the trunk control interface after the header FCS is verified. The trunk control interface will pick the function field out of the headerfield being transferred and will decode the command code field. Upon decoding a GO command the trunk control interface will issue a go signal to the processor. The trunk control unit will transmit a processor response message after the trunk controls interface inactivates the wait processor response signal. The trunk control interface will decode and execute this command at any time.If the trunk control unit is unable to connect to the trunk control interface, the trunk control unit will perform a resync function and will transmit a hardware response message with the trunk control interface not connected status set.

The command code for the step command is 7.

This is the same as the GO command except the trunk control interface issues step and GO commands to the processor which cause the processor to execute a single instruction.

The access code field is 16 bits long and is contained in the third and'fourth bytes of the header field. This field is processed as tour independent 4 bit groups. The trunk control unit hardware modifies the access code when a command message is being transmitted. In general terms, the access code is a concatenation of switch selectable hardware bits and of processor generated software bits, although an all hardware or all software access code system is possible.

To generate the access code, each 4 bit group is processed as follows. If any of the hardware bits associated with a specific 4 bit group are non-0, the hardware bits will be sent as that 4 bit group of the access code. If all the hardware bits for a group equal 0, the software bits will be sent as that 4 bit group of the access code. The trunk control unit hardware compares the received access code field with its own switch selectable hardware access code bits only on a a command message.

In response messages, the access code field bits in the header are used to send status information back with the response. When the trunk control unit hardware checks the access code field, each 4 bit group is processed independently as follows. If any of the hardware bits in a 4 bit group of the receiving trunk control unit are non-0, the corresponding 4 bit group of the received access code must match the hardware bits. If all the hardware bits of a group equal 0, the corresponding group in the received access code is a software access code which is not compared with the hardware bits. It is up to the network access device processor to verify these software access codes.

The resync parameter field is the fifth byte of the headerfield. This field is inserted by the transmitting trunk control unit hardware. The resync parameter is contained in the lower 5 bits of this field while the upper 3 bits are always zeros. After a trunk control unit receives a command message and verifies the header FCS, the trunk control unit will load the resync counter with the 5 bit resync parameter received. The resync parameter is a switch select able value for each trunk control unit. Each trunk control unit on a data trunk must have a unique resync parameter whose value must not be greater than the number of trunk control units on the trunk.

This relates to the contention scheme used in this device. This field is valid only for command messages. In a response message this portion in the header is used to transfer status information with the response.

The FROM address field is the sixth byte of the header field. The FROM address specifies the logical trunk control unit which sent the message. For all - messages the sending trunk control unit logical address switch setting is the FROM address trans mitted. When a command headerfield is received, the FROM address is stored in a register. The contents of this register is then sent as the TO address parameter in the response message The length field is the seventh and eighth bytes of the header field. This field defines the number of 16 bit words which are to be transferred in the information field. The data FCS word is not included in this count. The seventh byte of the header contains the high orderlength count while the eighth byte contains the low order l'ength count.

The header FCS field is the ninth and tenth bytes of the header. These bytes define the end of header field and are used to validate the correct reception of this field. The FCS used is a cyclic redundancy checking algorithm using the CCITT recommendation V.41 generator polynomial of x to the 16th plus to the 12th plus x to the 5 pl us 1.A trunk control unit has its FCS remainder register initialized to all ones before a message is transmitted or received. Each byte transmitted is premultiplied byxtothe 16th and divided by the generator polynomial' to obtain a remainder. The trunk control unit transmits the complement of the final remainder. If the message is received without errors, the final FCS remainder in the receiving trunk control unit is a predetermined number.

The data field is made up of two parts, the information field and the information FCS.

The information (I) field is only present if the length field in the header is non-0. It contains the data which is transferred between higher level processes that exist in units attached to the trunk.

Since the data length control is all contained in the header field, the I field consists of a variable number of bytes which are code and character independent.

The length of the I field must be an even number of 8 bit bytes and a length of O is specifically permitted.

The information frame check sequence field is present only if the length field in the header is non-0.

This field consists of 16 bits of frame checking which are generated from the contents of the I field in the same manner in which the header FCS field is generated.

The trunk control unit automatically inserts and deletes two sync character bytes between the last bit 'of the header FCS and the first bit of the information field. This is to allow the trunk control unit time to reset its FCS registers to all ones before processing the information field. These bytes are referred to as the trunk fill bytes. The trunk control unit automatically sends two bytes at the end of each message to act as trunk fill bytes. This is required to allow the receiving trunk control unit adequate time to receive the last byte of the message before the trunk ready signal goes inactive.

The trunk contention mechanism functions to eliminate trunk contention situations by assigning to each trunk control unit a specific time interval when transmitting onto the trunk is perrhitted: Each trunk control unit on the tru'nk is assigned a time interval by means of a hardware scanner which is divided into slots and subslots. There must be at least one slot for each trunk control unit but additional slots are permitted. One slot time must be greater than twice the total transmission line propagation delay.

A trunk control unit according to the present invention can be designed with a time slot which readily allows a 2,000 to 3,000 long coaxial cable for the data network. Each trunk control unit on a trunk is assigned a unique resync síot number and has its own resync counter which keeps the trunk control unit approximately synchronized with all other trunk control units. When a trunk control unit detects a command message on the trunk, it stops clocking the resync counter and processes the header field. If the message was received correctly and the header FCS was correct, the trunk control unit sets its resync counter to the resync number of the trunk control unit which sent the message. The sender resync number is the resync parameter received in the command header field.The trunk control unit receiv ing the message waits for the Data Ready signal from the data set to drop out while the other trunk control units are waiting for the channel active signal from the data set to drop out. The Data Ready signal drops after the last bit of data while the data set has an internal wait for a predetermined time after the last data bit before dropping the channel active signal. When the Data Ready signal drops, the trunk control unit which accepted the message will send data bits of all ones down the data trunk until it can transmit the response message.This keeps the channel active signal high for all the trunk control units and prevents them from incrementing their resyne counters. The channel active signal to the trunk control units will drop out a predetermined time after the response message is sent, enabling the trunk control unit resync counters to count. From this point each trunk control unit will increment its resync counter once every predetermined time interval for as long as there is no message transmitted onto the data trunk. Since the clock of each trunk control unit is not synchronized to all the other clocks, the trunk control units would drift out of synchronism with one another if there was no message traffic on the data trunk for a period of time.

To prevent this, each trunk control unit also has a contention counter. This counter is incremented each time the trunk control unit reaches its slot time on the data trunk. This counter is reset whenever a transmission is detected on the trunk. When the counter reaches a predetermined count, the trunk control unit sends a trunk resync message down the trunk to keep all the trunk control units in synchronism.

A trunk control unit may begin transmitting a command message only in the first predetermined small time interval portion of the trunk slot time. This predetermined small time interval may be approxi mately 10 percent of the entire slot time. Thus, all trunk control units on the data trunk will see the trunk go active during the transmitting trunk control units slot time. This will inhibit any trunk control unit from incrementing a resync counter within the transmitting trunk control unit slot time due to physical locations on the data trunk table.

This hardware scanner technique provides access to the data trunk for the trunk control units on a rotating priority basis. This prevents any trunk control unit from being locked out of the trunk. A -contention channel system consistent with the preceding description is explained in detail in U.S.

Patent Specification No. 4 199 661.

The hardware response status field is the status of the trunk control unit, trunk control interface and processor which is returned in each response message transmitted. The hardware response status consists of three 8 bit bytes which represent three parameters which are sent as the third, fourth and fifth bytes of the response header field.

The first parameter of the hardware response status field has 8 bits which are represented as follows. The first bit is set when a command message is received in which the function field either has bit one set to enable trunk control unit diagnostics or the command function is to enable the trunk control interface diagnostics.

The second bit is set when a parity error is detected on data being written into the trunk control unit input buffer. This status is cleared by master clear or when the data set channel active signal is low. The third bit is set when a parity error is detected on the trunk control unit/trunk control interface bus by the trunk control unit. This status is cleared by master clear or when the data set channel active signal is low.

The third bit is set when a parity error is detected on data loaded into the trunk control unit parallel to serial register. This bit is cleared by master clear or when the data set channel active signal is low.

The fifth bit is set if the trunk control unit output buffer was empty when data was loaded into the parallel to serial register and the length count was not zero.

The sixth bit is set if the trunk control unit input buffer word counter equals 15 when a word is written into the input buffer.

The seventh bit is set whenever the trunk control unit detects an FCS on either the header or information fields.

The eighth bit is set to zero if an abnormal condition is found by the trunk control unit.

The second parameter of the hardware response data field has 8 bits which are defined as follows.

The first bit is set when a trunk control unit is unable to connect to the trunk control interface.

The second bit is set by the trunk control interface to indicate it has detected an abnormal condition and represents an error signal. Such conditions may include those where a data transfer is completed but the data buffer is either still full or not empty.

The third bit is set when the processor has stopped.

The fourth bit is set when the processor has detected a memory parity error or when the processor is master cleared.

The fifth bit is set when the network access device control function is attempted through a trunk control unit which is not enabled to execute a network access device control function or when the length field for a command function is incorrect or if the response bit of the function field is set in a command message received from the data trunk.

The sixth bit is set when the trunk control unit data length counter or Rx word counter is not equal to zero.

The seventh bit is set by the trunk control interface when it detects a parity error on the trunk control interface bus or data from the trunk control unit during a Rx or on data from the NAD memory during a Rx sequence.

The eighth bit is set if the trunk control interface processor fails to provide a response message within a predetermined time of receiving a Rx command interrupt or if in the data streaming mode no response command message is-provided within a predetermined time of receiving a Rx command/Tx sequence interrupt signal.

The third parameter of the hardware response status field is used if the trunk control unit detects an abnormal condition. This 8 bit byte shows the 8 bits of the trunk control unit sequencer address which detected the abnormal condition. The most significant bit of the trunk control unit error address is in bit 7 of the parameter 1 status. If no abnormal condition has been found, this byte will be all Os.

There are six interrupt conditions which the trunk control unit may send to the trunk control interface to indicate that the trunk control unit has completed an operation. The interrupts are defined as follows: abnormal end of Rx command - this interrupt indicates that the trunk control unit detected an abnormal condition while receiving a command message. Abnormal end of Rx sequence -this interrupt indicates the trunk control unit detected an abnormal condition while transmitting- a response message. Abnormal end of Tx sequence - this interrupt indicates that the trunk control unit detected in abnormal condition while transmitting a command message or receiving a response message. End of Rx command - this interrupt indicates that the trunk control unit has completed receiving an error free command message.End of Rx sequence - this interrupt indicates the trunk control unit has completed transmitting an error free response message. End of Tx sequence - this interrupt indicates the trunk control unit has completed transmitting an error free command message and received an error free response message. Stream mode time out warning - this interrupt indicates the processor must provide a response message or Tx command within a predetermined time interval to prevent the trunk control unit from sending a hardware response message or terminating the Tx command stream mode sequence.

The trunk resync message is initiated by the trunk control unit hardware in order to keep all of the trunk control units on a trunk synchronized. Since this message is directed to all trunk control units on the trunk, the trunk control unit which transmits this message puts its own logical address into the TO address parameter field. This prevents all of the trunk control units receiving this message from generating a response message.

The stream mode is initiated by higher levelprotocols within the network access-device microp rocessors to transfer large blocks of data; The stream mode is the only trunk operation in which the trunk is not available to other trunk control units between command response message frames. The trunk is dedicated to the two trunk control units in stream mode until operation is completed or until an error is detected by either of the network access devices.

When receiving a command message the trunk control unit interrogates the trunk control interface stream mode line only after sending the trunk control interface end of Rx command interrupt. If the stream mode line is active, the trunk control unit will capture the trunk by setting the send request and sending binary ones continuously down the data trunk. If the processor does not supply a response message within a predetermined time interval of when the interrupt was sent, the trunk control unit will send a stream mode time out warning interrupt to the trunk control interface. If no response is received-within a predetermined time interval of this interrupt, the trunk control unit will send a hardware response to the originating trunk control unit.

The originating trunk control unit network access device processor should drop that trunk control unit out of stream mode on receipt of the message. A processor stream mode error status and abnormal end of Rx sequence interrupt are sent to the processor which will terminate stream mode in the receiving trunk control, unit.

When receiving a response message the trunk control unit interrogates the stream mode line only after sending a Tx sequerice interrupt to the trunk control interface. If-the stream mode line is active, the trunk control unit will capture the trunk and wait a predetermined time interval for a new Tx message from the processor. A stream mode time out warning interrupt is sent to the trunk control interface if a Tx message is not received within this predetermined time interval.If a Tx message is not received within a predetermined time interval ofthis interrupt mes sage, the trunk control unitwill release the trunk, that is drop the send request signal, and will send a processor stream mode error status and-abnormal end of Tx sequence interrupt to the trunk control interface which will terminate-stream mode in the originating trunk control unit Releasing the trunk will cause the remote trunk control unit to drop out of stream mode.

Since every microcode instruction is actually a jump instruction, a next address field is specified' with each instruction. Sequential memory referenc ing is provided by using the current address as the hardware condition being tested. The sequencer has a unique diagnosticfeature called an error address register.

Thetrunk control unit Microcode Sequencer per forms four basic functions.

1. It provides timed pulses to clock various hardware registers.

2. It provides signals to transfer data onto the internal hardware bus from various source registers.

3. It provides a latch mechanism to store prog ramme flags.

4. It provides mechanism to perform condition al microcode jumps dependent on the condition of the specific hardware condition being tested.

The sequencer has no data manipulation or prog ramme subroutine capabilities. The sequencer is constructed such that the least significant address bit (LSB) for the next address is dependent on the hardware condition being tested. If the hardware condition being tested is true, the LSB of the next address is forced to a logical one, if the condition being tested is false, the LSB of the next address is forced to a logical zero. Since every instruction is actually a jump instruction, a next address field is specified with each instruction. Sequential memory referencing is provided by using the LSB of the current address as the hardware condition being tested. The sequencer has a unique diagnostic feature called an error address register. This register is loaded by a field decoded from the microinstruc tion. The data loaded into this register is the 10 bits of the address of the instruction preceding the instruction containing the load command. This pro vides a unique and very informative pointer to each abnormal condition detected by the sequencer while using a common error handling routine.

Claims

1. A network access device comprising: a data set adapted to be connected to a data network; a trunk control unit adapted to be connected to said data set for bi-directional communication into and out of said network and for transmitting command messages and for receiving response messages; a trunk control interface adapted to be connected to said trunk control unit and for buffering of data; a network access device internal bus adapted to be connected to said trunk control interface; a network access device processor connected with said internal bus for controlling said trunk control interface and trunk control unit; an internal network access device memory connected with said internal bus; and a device interface connected with said internal bus for communication through said trunk control interface to said trunk control unit and to said data network through said data set and having an output device channel adapted for connection to a computer device.

2. A network access device coinprising: data set means for connection with a data network; interface means for connection with a computer device; network access device processor having stored the programme sequence for controlling hardware func tions within said network access device; trunk control unit means for connection between said interface means and said data set means wherein said trunk control unit means is comprised of bi-directional data transmission means, said trunk control unit including means for converting serial data input streams to parallel bytes to form data words on receipt of incoming messages and to convert outgoing data words into parallel bytes and serial data on outgoing messages and buffer means for interconnection with said interface device.

3. A network access device comprising: a data set adapted to be connected to a data network; trunk control unit means adapted to be connected to said data set for bi-directional communication into and out of said network and for transmitting command messages and for receiving response messages, so that for each command message received the response message provides status information about the receiving network access device; a trunk control interface adapted to be connected to said trunk control unit and for buffering of data, said trunk control interface including a control latch for receiving status information from said trunk control unit with respect to the mode of operation of said trunk control unit; a network access device internal bus adapted to be connected to said trunk control interface; a network access device processor connected with said internal bus for controlling said trunk control interface and trunk control unit; an internal network access device memory connected with said internal bus; and a device interface connected with said internal bus for communication through said trunk control interface to said trunk control unit and to said data network through said data set and having an output device channel adapted for connection to a computer device.

4. A network access device as claimed in any preceding claim in which said control interface is connected with a plurality of trunk control units each of which has a respective data set for connection to a data network.

5. A network access device as claimed in claim 4 in which all of said trunk control units are connected with said one trunk control interface.

6. A network access device as claimed in any preceding claim arranged so that, in operation, for each command message received in the or each trunk'control unit, the response message provides information about the status and the activity occurring in the network access device in responseto the command message.

7. A network'access device as claimed in any preceding claim in which said device interface includes a message counter and an address counter which compares the message length and address used with header information received on a command message to use in determining that the data message has been correctly received.

8. A network access device as claimed in any preceding claim in which said trunk control unit includes at least one instruction holding register and latch means for holding microcode instructions received prior to the time of execution and which are latched until the time of execution.

9. A network access as claimed in any preceding claim in which said data set provides data in a serial mode to said trunk control unit and wherein said trunk control unit includes a serial to parallel interface logic unit and an input holding register wherein data is received in bit serial form an output in byte parallel form.

10. A network access device as claimed in any preceding claim in which said trunk control unit includes a trunk control unit input bus which is accessed by a number of tri-state' drivers each of which, in operation, is controlled by a microcode sequence logic and clocks to control access to said trunk control unit input bus at predetermined times according to said sequence code.

11. A network access device as claimed in any of claims 1 to 5 in which said trunk control unit includes a trunk control unit input bus connecting an input holding register to an input buffer, a plurality of tri-state drivers connected to said input buffer to drive an output bi-directional data bus connected with said trunk control interface, an input word counter connected with said input buffer, an output word counter connected with said input buffer wherein said counters are controlled by an input header portion of a command message and decrement to zero as said message is supplied to said input buffer and out of said input buffer to said trunk control interface.

12. A network access device as claimed in any preceding claim in which said trunk control unit is arranged to operate on words formed of upper and lower bytes and in that an upper address length counter and a lower address length counter, in operation, compare input command messages with input messages as part of the process for determining that the message has been correctly received.

13. A network access device as claimed in any preceding claim in which said trunk control unit is comprised of synchronization detection registers to produce output synchronization control signals in response to synchronization bits and received messages at a predetermined time and synchronization within an internal clock signal.

14. A network access device as claimed in any preceding claim in which said trunk control unit is, in operation, enabled to send a command message only at predetermined times when a logic means provides an output signal indicating that the data network is not active at a time allotted to that trunk control unit.

15. A network access device as claimed in any preceding claim in which said trunk control unit is comprised of decoder logic means responsive to said network access device processor, internally generated clock signals, and bits received in command messages to determine one of a predetermined possible number of functions to perform.

16. A network access device as claimed in any preceding claim in which said trunk control unit is comprised of internal latches responsive to said processor to receive and store instructions prior to a time when used and responsive to internally generated clock signals to generate a sequencing function to perform certain functions in a predetermined sequence, including means for providing FCS checking of both a header portion and a data portion of received messages in a predetermined sequence.

17. A network access device as claimed in claim 16 in which said trunk control unit includes logic means for disabling said trunk control unit if the FCS generator checker provides a not valid output for either the header portion or the data portion of a message.

18. A network access device as claimed in claim 17 in which said trunk control unit is comprised of logic means for producing internally generated FCS check characters to be sent in response messages in both a header portion and a data portion of said message in response to microcode latch instructions in sequence in response to clock signals.

19. A network access device as claimed in any preceding claim in which said trunk control interface includes a trunk control unit control latch for receiving status information from said trunk control unit with respect to the mode of operation of said trunk control unit.

20. A network access device as claimed in any preceding claim in which the data network may operate in a streaming unit mode wherein each network access device becomes disabled on the network except, for a pair of units which are sending a data stream from one to the other.

21. A network access device as claimed in any preceding claim in which said network access device includes logic means for controlling said network access device when a streaming mode command signal is not addressed to it so that it waits for the streaming mode operation to be completed on the network.

22. A network access device as claimed in any preceding claim in which said network access device is comprised of a trunk control unit which, in operation, becomes enabled in the streaming mode of operation in response to a streaming mode command signal so that data may flow continuously in response to data on said data network until an end of message signal is recei.ved.

23. A network access device as claimed in any preceding claim in which said trunk control unit is comprised of a function register, an internal trunk control unit input bus connected to said function register, a decoder for receiving the contents of said function register and producing an output control signal, said function register and decoder being responsive to clocking signals to only sample data from said bus at a predetermined time in a sequence of timed operations.

24. A network access device as claimed in any preceding claim in which said trunk control unit is comprised of a trunk control unit input bus contention channel means including a contention counter, a predetermined sequence of timed functions occurring at predetermined times and response to said network access device processor so that said contention channel means is only enabled at a predetermined time in said predetermined sequence of events.

25. A network access device as claimed in any preceding claim in which said trunk control unit includes an input buffer, an input buffer counter and means responsive to said counter tq indicate when said buffer is either full or empty and further comprising logic means for sending an error signal in response to said trunk control unit buffer being full.

26. A network access device as claimed in any preceding claim in which said trunk control unit includes logic means for responding to a command message with a response message indicating an error or a diagnostic within a predetermined time in the absence of a response message control by said processor.

27. A network access device as claimed in any preceding claim in which said trunk control unit has an instruction address holding register for holding each instruction address in a received message during execution so that it is not lost; an error detection logic means for detecting an error status in the trunk controluniti and means for sending a response message indicating an error status in response to a signal from said error detection logic means, said message containing a portion which consists of the instruction address received from said instruction address holding register which resulted in the error status.

28. A network access device as claimed in any preceding claim in which said trunk control unit includes means for resynchronization with the data network including response functions to microcode instructions as part of a predetermined microcode sequence of operations.

29. A network access device as claimed in claim 3 in which said trunk control unit includes a trunk control unit input bus which is accessed by number of tri-state drivers each of which is controlled by microcode sequence logic-and clocks to control access to said trunk control unit input bus at predetermined times according to said sequence code, said trunk control unit including at least one instruction holding register and latch means for holding microcode instructions from said processor received prior to the time of execution and which are latched until the time of execution according to said sequence.

30. A network access device as claimed'in claim 3 in which said trunk control unit is comprised of internal latches responsive to said microcode control processor to receive and store microcode instruc tions prior to a time when used and responsive to internally generated clock signals to generate a sequencing function to perform certain functions in a predetermined sequence, and further including a function register, an internal trunk control unit input bus connected to said function register, a decoder receiving the contents of said function register and producing an output control signal, said function register and decoder being response to clocking signals to only sample data from said bus at a predetermined time in a sequence of timed operations.

31. A network access device as claimed in claim 3 in which said trunk control unit is comprised of a contention channel means including a contention counter, and said contention channel means being, in operation, only enabled at a predetermined time in said predetermined sequence of events.

32. A network access device substantially as herein described with reference to and as shown in the accompanying drawings.