GB2074400A - DC to AC inverter - Google Patents

Abstract

The inverter is used in synthesising a sine wave and comprises two transformers, a major transformer and a minor transformer operated in effect as two separate inverters whose primary windings 10A, 12A work in parallel from the same DC source. The secondary windings 10B, 12B of the two transformers are connected in series. Switches S1-S4 connected to the primary windings are controlled in such a way as to produce bidirectional pulse trains at the transformers' respective secondary windings. Short circuit clamps are connected across either the primary windings or secondary windings or tertiary windings to short circuit said windings when the associated primary winding is disconnected from the DC source by the switches. <IMAGE>

Description

SPECIFICATION DC to AC inverters This invention relates to inverters, and is particularly concerned with sine wave power inverters which provide a sine wave AC output from a DC source using semiconductors as the power switching elements.

Such power inverters are used to power a wide range of types of equipment designed to run from the AC mains supply, especially when it is necessary to provide an uninterrupted power supply, or when no AC mains supply is available.

It is common practice nowadays to use all-electronic inverters, in contrast to the older electromechanical systems. One known technique for inverting a DC voltage is to use switching elements in combination with a transformer, but the AC output which is obtained with this basic method has a square waveform. In order to provide an AC output with a waveform which is as close as possible to the AC mains supply, it is desirable to provide a sinusoidal AC waveform which contains as little harmonic distortion as possible, and which is closely regulated in amplitude. It is further desirable that there is efficient transmission of the AC power to the load.

Existing static power inverters which generate a sine wave output from a DC input voltage usually employ either a constant voltage transformer or a linear amplification method of inversion. However, the constant voltage transformer is inefficient at partial loads, it does not provide very good voltage stability, it draws a large no-load current, it requires special laminations and other parts for its construction, and is very heavy. The known linear amplification methods of inversion are characterised by particularly low efficiency in the transmission of power to the load. As the power source for a static inverter is usually a battery, it is very important to be able to achieve maximum efficiency at all loads up to full load. It is also important to be able to operate the inverter with a low standby, i.e. no-load, current input.

It is an object of the present invention to provide a DC to AC inverter which produces a stabilised, closely regulated, low distortion sine wave output from a DC input, the inverter being highly efficient at all loads, having a small no-load current drain and being relatively light in weight. The inverter of the present invention can be constructed using standard low-cost transformer electronic components.

Broadly in accordance with one aspect of the present invention there is provided an inverter comprising two transformers, the primary winding of each being powered from a DC voltage supply and with their secondary windings connected in series, and switch means associated with each transformer's primary winding and operative in response to control means to produce from the transformers a pulse width modulated synthesised waveform.

Preferably, the primary winding of each transformer is connected by a centre tap to the positive side of the DC supply and the switch means are connected to the other side of the DC supply, and to the ends of the primary windings, the switch means and the respective transformers thus constituting two separate inverters each working in what is known as the parallel mode.

Preferably, the ratios of the output voltages of the two transformer secondary windings are

and the primary windings of the transformers are driven so that the transformer producing the higher secondary voltage produces a positive output pulse for a predetermind length of time during each of the periods sir/6 to or/3, sir/3 to 7r/2, 1r/2 to 2sir/3, and 2n/3 to 5sir/6 and the other transformer produces a positive output pulse for a predetermined length of time during each of the periods 0 to 7r/6, 7r/3 to 7r/2, so/2 to 27r/3, and 5so/6 to m, where the periods refer to the fundamental of the wave-form across the secondary windings and the period 0 to 7r represents the positive half cycle of the output, both transformers producing corresponding negative output pulses during the succeeding half cycle.

The present invention has another equally important aspect and broadly in accordance therewith there is provided an inverter comprising two transformers each with centre-tapped primary windings working in the parallel mode and powered from a DC voltage source and with secondary windings connected in series, each transformer producing a train of output pulses, and switch means associated with each transformer and controlled so that each switch shortcircuits the respective transformer whenever it is not producing output pulses.

This short-circuit means, hereinafter referred to as a clamp, is preferably connected across each primary winding. In the inverter the clamps form part of two individually controllable circuits. The provision of such clamps across the respective transformers means that the pulses of the respective pulse trains return to zero, thus maintaining the conditions necessary to ensure a low distortion sine wave output to the load.

According to a preferred embodiment of the invention, the clamps each comprise a diode bridge with a switching element, for example a transistor, connected between the common positive and negative junctions of the bridge.

Various other forms of clamp may alternatively be used, as will be described in more detail later.

In order that the invention may be more fully understood a preferred embodiment of inverter in accordance therewith, together with various modified forms, will now be described by way of example and with reference to the accompanying drawings, in which: Figure 1 diagrammatically illustrates the basic synthesised waveform produced by the inverter of the present invention, the waveform being shown at maximum pulse width and before filtering; Figure 2 diagrammatically illustrates the basic synthesised waveform produced by the inverter of the present invention with pulse width modulation applied to the waveform to produce six pulses in each positive and each negative half cycle of the waveform; Figure 3 shows a first pulse train, being the output from the major transformer of the circuit shown in Fig. 7, and which constitutes one part of the synthesised waveform shown in Fig. 2;; Figure 4 shows a second pulse train, being the output from the minor transformer of the circuit shown in Fig. 7, and constituting a second part of the synthesised waveform shown in Fig. 2; Figure 5 is a timing diagram illustrating the timing of the operation of a clamp switch associated with the major transformer of the circuit of Fig. 7; Figure 6 is a timing diagram illustrating the operation of a clamp switch associated with the minor transformer of the circuit shown in Fig. 7; -Figure 7 is a schematic circuit diagram of the inverter of the present invention; Figure 8 is a circuit diagram of a portion of.the- inverter shown in Fig. 7, illustrating one embodiment of clamp appropriate for use with the transformers; and, Figures 9 to 13 are detail views illustrating alternative embodiments of clamp for use in association with the transformers of the inverter.

Fig. 1 illustrates the form of unfiltered synthesised waveform which is produced by the inverter of the present invention. A complete cycle of this waveform is represented as the interval 0 to 2m along the abscissa. The maximum amplitude of the waveform is A. The amplitude of the waveform during the intervals 0 to n/6 and 5?T/6 to a its 1/2 + o/3 (approximately equal to + 0.268) of the maximum amplitude A. The amplitude of the waveform during the intervals sir/6 to 7r/3 and 2sir/3 to 5so/6 is 2A/1 + o/3 (approximately equal to + 0.732A.During the intervals n/3 to ire/2 and sir/2 to 27r/3 the amplitude of the waveform is equal to A. Corresponding negative amplitudes occur during the negative half cycle during the time interval from er to 27r.

It will be seen that the sum of 0.268 and 0.732 is 1.000. Thus the amplitude of the waveform over the periods "/3 to 7r/2 and m/2 to 2m/3 may be obtained simply by adding the amplitudes 0.268A and 0.732A. As will be described in detail hereinafter, the inverter of the present invention produces two separate pulse trains, as shown in Figs. 3 and 4, which, by summation, produce the composite waveform shown in Fig. 2. This composite waveform can then be filtered to produce a final AC output which closely approximates a sine wave.

Fig. 7 shows the power inverter to the present invention in schematic form. The inverter comprises two transformers, hereinafter referred to as a major transformer and a minor transformer. The major transformer primary winding is indicated at 1 OA, the major transformer secondary winding is indicated at 1 OB, the minor transformer primary winding is indicated at 1 2A and the minor transformer secondary winding is indicated at 1 2B. A centre tap on each of the transformer primary windings 1 0A and 1 2A is connected to a common positive DC input line 14 constituting one side of a DC supply. The two transformer secondary windings 1 OB and 1 2B are connected in series as shown.The major transformer primary winding 1 0A is connected to the other DC input supply line 16 by way of two switches S1 and S2, and the minor transformer primary winding 1 2A is similarly connected to the line 1 6 by way of two switches S3 and S4. These switches and their respective transformers thus constitute two separate inverters, each working in the parallel mode. In use, the switches S1 and S2 on the one hand and the switches S3 and S4 on the other hand are independently controlled so that the major and minor transformers 10 and 1 2 will produce in their secondary windings lOB and 1 2B pulses corresponding to amplitudes of 0.732A and 0.268A respectively of either polarity.

The output of the transformer secondary windings 1 OB and 1 2B is fed to an LC filter and thence to the AC output terminals which are connected to the load. A sensing circuit 1 8 is connected across the AC output terminals to sample the output sine wave. Informaton regarding the amplitude of the output sine wave is fed back from the sensing circuit 1 8 to a control circuit 20. The control circuit 20 is connected to the four switches S1 to S4, and also controls a pair of short-circuiting clamps CL1 and CL2 which are connected respectively across the transformer primary windings 1 0A and 1 2A and which will be described in greater detail later. The control circuit 20 controls the widths of the pulses produced by the transformers and also controls the action of the clamps CLi and CL2.The control circuit ensures that all the pulse widths are of equal time duration and applies pulse width modulation in accordance with the information from the sensing cicuit 1 8. The closed loop control system containing the sensing circuit 1 8 and the control circuit 20 provides close regulation of the final sine wave amplitude by modulation of the pulse width. The proportion of the time during any sir/6 interval that a given pulse is produced may be varied by the control circuit 20 in order to obtain, in association with the clamps, the major and minor secondary waveforms shown in Figs. 3 and 4 respectively and which when summed produce the composite waveform shown in Fig. 2 which is applied to the LC filter.

The peak amplitude of the sine wave which is synthesised in this way can be varied from zero to a maximum of approximatly 1.023A (when the pulse width is at its maximum.) Moreover, if all the pulse widths are the same, then the composite synthesised waveform of Fig. 2 will include no harmonics lower than the 1 itch for any pulse width from 0 to sot/6. This synthesised waveform is therefore easily filtered to produce a high quality sine wave output with very low total harmonic distortion. In practice, it has been found that a sine wave output with a total harmonic distortion of 3% to 5% can readily be obtained at any unity power factor load.

As mentioned above, an important feature of the present invention is the provision of the short-circuiting clamps CLi and CL2 across the transformer primary windings 1 0A and 1 2A.

The function of these clamps is to short-circuit the respective transformers whenever they are not producing output pulses, i.e. during the times that either S1 and S2 on the one hand or S3 and S4 on the other hand are open. These short-circuiting clamps enable current to continue to flow through one or both transformers, as the case may be, while still not causing the prefiltered output waveform to depart from the waveform shape shown in Fig. 2. In this way one can maintain the conditions necessary to ensure a low distortion sine wave output to the load.

Without the presence of the clamps CLi and CL2 the reactance of the LC filter, any reactance of the load, and the magnetic flux in the transformers, would all tend to make the waveform depart from that shown in Fig. 2 to a considerable degree, thereby resulting in high distortion of the output waveform to the load.

The two clamps, referred to as the major clamp and the minor clamp, are individually controlled by the control circuit 20. Figs. 5 and 6 are timing diagrams illustrating when these respective clamps are "on" and "off", the indication "on" denoting that the short-circuit is applied to the respective transformer. At certain times, the two clamps are "on" together.

Fig. 8 illustrates one embodiment of the short-circuiting clamps CLi and CL2. It will be seen that the major clamp CLi contains a diode bridge of diodes D1 to D4, and that the minor clamp CL2 contains a diode bridge of diodes D5 to D8. N-PN transistors Q1 and Q2 are connected between the common positive and negative junctions of the respective diode bridges. Each group of four diodes and their associated transistor comprises the basic clamp. The four switches S1, S2, S3 and S4, which are shown in Fig. 8, may conveniently be NPN transistors of the same type as the clamp transistors Q1 and Q2.The bases of clamp transistors Ol and Q2 are supplied with current by way of PNP transistors Q3 and Q4 respectively, and as will be seen later from a point which is more positive and the main DC input line 14. Transistors Q3 and Q4 have their emitters connected through respective resistors R1 and R2 to a point B which is maintained at a higher mean DC voltage than that of the main DC supply. Resistors R1 and R2 thus provide base current to Q1 and Q2 respectively. Diodes D9 and D10 respectively are connected between this point B and the common positive junctions of the diode bridges which are connected to the collectors of the clamp transistors Q1 and Q2.A capacitor C1 is connected between point B and the DC positive supply line 14, or alternatively between point B and the DC negative line 1 6. Point B is kept at its voltage, higher than the main DC supply voltage, by the repeated switching action of both the major and minor inverter sub-systems, which provide positive pulses via D1, D2, D9 and D5, D6, D10 to the capacitor C1. This is an extension of a well-known technique which also provides spike voltage suppression to protect the switches S1 to S4, and Q1 and Q2. The resistors R1 and R2 also serve to discharge the capacitor C1 to some extent, thus maintaining point B at approximately twice the main DC voltage.Alternatively, separate diodes may be used instead of diodes D1, D2, D9 and D5, D6, D10, the separate diodes being connected to points on the primary winding(s) and charging the capacitor C1. Also, two capacitors may be used in place of C1, the capacitors being discharged by R1 and R2 respectively. Resistors R1 and R2 may alternatively be supplied from any auxiliary DC supply which is at a more positive voltage than the DC positive line 14.

The bases of the current-supply transistors Q3 and Q4 are connected by way of respective resistors R3 and R4 and NPN transistors Os and Q6 to the DC negative rail 16. Transistors 03 and 04 are controlled via Q5, R3 and 06, R4 respectively. Individual control of the major and minor clamps is achieved by controlling the bases of transistors Q5 and 06 whose emitters are conveniently at DC negative potential. The control circuit 20 provides the drive to the bases of both the switches S1 to S4 and also the transistors Q5 and Q6 at the-appropriate times to generate the output wave shown in Fig. 2.The use of diode bridge clamps results in the peak currents in the clamp transistors being only one half of the peak currents in the associated main switching elements S1, S2 and S3, S4.

Fig. 9 shows an alternative form of clamp which can be used with each of the two transformer primary windings. Here the clamp comprises a PNP transistor Q7, connected in the diode bridge in a similar manner to transistor 01, but having its emitter connected to the diode bridge common positive point, and having its base connected to and controlled by an NPN transistor Q8 which has its emitter connected to the DC negative rail 1 6. As a further alternative, the transistor Q7 may be a compound arrangement of an NPN power transistor and a PNP driver transistor to produce an effective PNP power transistor.

In an alternative embodiment of clamp shown in Fig. 10 the diode bridge is connected to tappings on the transformer primary winding 1 0A which are closer to the centre tap than the tap connections to the main switches S1 and S2. Alternatively, as indicated by the broken lines, the diode bridge may be connected to extensions of the primary winding which are more remote from the centre tap than the tap connections to the main switches S1 and S2. The former arrangement reduces the voltage capability required of the clamp transistors and associated driving transistors, and is of particular value when a high voltage DC input is used. The latter arrangement increases the voltage across the clamp and its driver, but enables a lower current rating to be employed for the diode bridges and clamp transistors.Each of these alternative circuits uses the auto-transformer property of the transformer primary winding 1 OA.

Fig. 11 shows an arrangement in which two clamp devices CL3 and CL4, i.e. switching devices, (optionally with series blocking diodes), are connected in inverse parallel relationship across the primary winding 1 or, each switching device being separately controllable. Alternatively a single, bidirectional clamp may be used across the winding. Fig. 1 2 shows a centretapped clamp comprising two diodes and a single clamp device CL5, i.e. switching element, connected between the junction of the two diodes and the centre tap of the winding 1 or. The diodes may alternatively be connected in the reverse sense to that shown with appropriate reversal of the clamp device if necessary.

Fig. 1 3 shows an arrangement of two clamp transistors Q9 and Q10 in series across the transformer winding 1 OA with emitters connected together and diodes across each transistor in the inverse sense, so that the diodes' anodes are connected to each other and to the junction of the two emitters. Q9 and Q10 may be controlled in a similar manner to that shown in Fig. 8 if they are NPN transistors, or in a similar manner to that shown in Fig. 9 if they are PNP transistors. The advantages of the circuit are that a single driving circuit may be used as the two emitters are at the same potential, and that transistors with inverse diodes incorporated may be used, so obviating the need to use separate, external, diodes.

Any of the circuits shown may be used on different primary winding tappings as in the arrangement shown in Fig. 10. In other words, each clamp network is connected to opposite halves of the transformer primary winding to points on the winding which are not coincident with the points on the winding to which the main switching elements driving the transformer are connected. Any of the circuits shown in Figs. 9 to 13 may be used with either major or minor transformer.

The switching elements used in the inverter of the present invention may be any suitable type of semi-conductor device. They may be field effect transistors, thyristors, or Darlington transistors, the latter being either compounded from separate transistors or in monolithic form.

Any switching element may be a combination of two or more switching elements connected in parallel and working together.

Although in the foregoing description reference has been made to the clamps operating on the primary windings of the major and minor transformers, one or more of the clamps may be arranged to operate on a tertiary winding on one or both transformers. Alternatively or additionally, one or more clamps may be provided to operate on the secondary winding, i.e. the output winding, of the respective transformer. The connection points of the clamp to the secondary winding may or may not coincide with those points from which the output is taken.

In a modified embodiment of the inverter, one of the transformers, together with its associated switching elements and clamp, may be replaced by two or more transformers with associated switching elements and clamps, with the secondary windings of the replacement transformers connected in series so that the total output voltage at any time from the seriesconnected secondaries is equal to the secondary output voltage of the replaced transformer.

Although NPN transistors are shown for the main switches and for the clamp switches in Fig.

8, the inverter may also be constructed using PNP transistor switches. Further, the DC supply for any of the inverter circuits described may be reversed, (with the use of different polarity transistors where appropriate), so that the transformer centre taps are connected to the negative DC input line.

The power inverter of the present invention provides a very closely stabilised sine wave output at a stable frequency, with both output voltage and frequency being substantially unaffected by load or input voltage changes. Additionally, the inverter has very low total harmonic distortion, transmits AC power to the load with high efficiency, is relatively light in weight, and may be constructed using standard low-cost components and assembly methods. The inverter of the present invention may also form part of an AC to AC converter. Any of the inversion methods described may also be used in the construction of a three-phase DC to AC inverter, or a threephase AC to AC converter.

The clamping methods described may also be used to operate on one or more transformers which produce output pulses whose amplitudes or periods are different from those described above. The basic synthesised waveform shown in Figs. 1 to 4 may also be produced by two transformers, the primary windings of which are driven from a DC supply by means of four switching elements connected in a bridge configuration, either with or without any of the clamping methods described above.

Claims (1)

1. An inverter circuit for use in synthesising a sine wave, comprising: (a) two transformers whose primary windings are arranged to be connected in parallel across a DC source with a centre tap of each primary winding connected to one pole of the DC. source and the ends of the primary windings connected to the other pole of the DC source, and whose secondary windings are connected in series, (b) respective first switching means associated with each primary winding and through which both ends of the associated primary winding are connected to said other pole of the DC source, (c) respective second switching means associated with each primary winding or secondary winding or a tertiary winding for short circuiting the associated winding, (d) control means for controlling the operating sequence and periods of said switching means, such that each primary or secondary or tertiary winding is short circuited by said second switching means when both ends of the associated primary winding are disconnected from said other pole of the DC source by said first switching means and such that the output voltage across the series connected secondary windings comprises a series of positive pulses of varying amplitude alternating with a series of negative pulses of similarly varying amplitude.

2. An inverter circuit according to claim 1, wherein for the period (0 to ") of each of the alternating series of positive and negative pulses appearing across said secondary windings higher amplitude pulses from one transformer are produced for a part of each of the intervals 7r/6 to "/3; "/3 to 7r/2; n/2 to 2sir/3; 2sir/3 to 57r/6 and lower amplitude pulses of the same polarity are produced by the other transformer over the same part of each of the intervals Q to 7r/6; sir/3 to sir/2; n/2 to 27r/3;; 572/6 to n.

3. An inverter circuit according to claim 2, wherein the ratio of the amplitudes of the output pulses from the secondary windings of the two transformers is substantially

4. An inverter circuit according to any preceding claim wherein said second switching means comprises a diode bridge and a switching element connected between the common positive and negative junctions of the diode bridge and the other two junctions of the diode bridge each being connected to a respective end of the associated winding.

5. An inverter circuit according to claim 4, wherein said second switching means are associated with the primary windings of the transformers and wherein a capacitor is connected between the positive or negative pole of said DC source and a said common junction of said diode bridge whereby said capacitor becomes charged by commutating pulses generated by the primary winding, whereby the capacitor provides a potential higher than that of the pole to which the centre tap of the primary winding is connected.

6. An inverter circuit according to claim 5, wherein said capacitor is common to both diode bridges and is connected to said bridges through respective steering diodes.

7. An inverter circuit according to claim 5 or 6, wherein each said switching element comprises a transistor whose base is connected to the higher potential side of said capacitor through a resistor such that the base current for said transistor is drawn from said capacitor.

8. An inverter circuit according to claim 7, wherein a switching transistor is connected in series with said resistor for controlling the flow of said base current, said switching transistor being controlled by said control means.

9. An inverter circuit according to claim 4 wherein said switching element comprises a transistor whose base is connected to one pole of said DC source through a resistor and a control switch for controlling the flow of the base current of said transistor.

10. An inverter circuit according to any preceding claim, wherein said second switching means are associated with said primary windings and are connected to points on said primary windings which are symmetrical with respect to the centre tap but which are not coincident with the points on said windings which are connected to said other pole of the DC source.

11. An inverter circuit according to any preceding claim, wherein one or both of said two transformers are formed by two separate transformers having their secondary windings connected in series.

1 2. An inverter circuit according to any preceding claim, wherein said DC source is derived by rectifying an AC source.

1 3. An inverter circuit substantially as hereinbefore described with reference to Fig. 7 or Fig.

8 or Fig. 9 or Fig. 10 or Fig. 11 or Fig. 12 or Fig. 13 of the accompanying drawings.

CLAIMS (23 Feb 1981)

1. An inverter circuit for use in synthesising a sine wave, comprising: (a) two transformers whose primary windings are arranged to be connected in parallel across a DC source with a centre tap of each primary winding connected to one pole of the DC source and the ends of the primary windings connected to the other pole of the DC source, and whose secondary windings are connected in series, (b) respective first switching means associated with each primary winding and through which both ends of the associated primary winding are connected to said other pole of the DC source, (c) respective second switching means associated with each primary winding or secondary winding or a tertiary winding for short circuiting the associated winding, (d) control means for controlling the operating sequence and periods of said switching means, such that each primary or secondary or tertiary winding is short circuited by said second switching means when both ends of the associated primary winding are disconnected from said other pole of the DC source by said first switching means and such that the output voltage across the series connected secondary windings comprises a series of positive pulses of varying amplitude alternating with a series of negative pulses of similarly varying amplitude, characterised in that: : (e) for the period (0 to ") of each of the alternating series of positive and negative pulses appearing across the secondary windings, higher amplitude pulses from one transformer are produced for a part of each of a predetermined number of intervals and lower amplitude pulses of the same polarity are produced over the same part of other intervals and common intervals as said higher amplitude pulses.