GB2073946A - ???-Particle shielding of semiconductor device - Google Patents

???-Particle shielding of semiconductor device Download PDF

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Publication number
GB2073946A
GB2073946A GB8000919A GB8000919A GB2073946A GB 2073946 A GB2073946 A GB 2073946A GB 8000919 A GB8000919 A GB 8000919A GB 8000919 A GB8000919 A GB 8000919A GB 2073946 A GB2073946 A GB 2073946A
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polymer
housing
semiconductor device
semiconductor
alpha
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GB8000919A
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GB2073946B (en
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ITT Industries Ltd
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ITT Industries Ltd
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Priority to GB8000919A priority Critical patent/GB2073946B/en
Priority to DE19803048343 priority patent/DE3048343A1/en
Priority to JP131781A priority patent/JPS56104452A/en
Priority to FR8100284A priority patent/FR2473788A1/en
Publication of GB2073946A publication Critical patent/GB2073946A/en
Application granted granted Critical
Publication of GB2073946B publication Critical patent/GB2073946B/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are be prevented by coating the active surface 12 of the semiconductor chip with a thin layer 17, e.g. 20 to 100 microns, of an organic polymeric material, this layer 17 being of sufficent thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. <IMAGE>

Description

SPECIFICATION Integrated circuit manufacture This invention relates to semiconductor integrated circuits, and in particular to the minimisation, if not elimination of the effects of charged particle bombardment on such circuits.
Semiconductor integrated circuits, and in particular semiconductor memories, are becoming increasingly compact in an attempt to fabricate the maximum number of discrete elements, e.g. memory cells, in a given chip area. A recently observed phenomenon with such highly integrated devices is that of soft errors which, in contrast to hard errors which arise from manufacturing defects, are transient and of a random nature. The incidence of these soft errors is very low, typically 10-6 or 10-7 errors per hour, and they are observable only in situations where a large number of devices are employed, e.g.
in a computer.
The source of soft errors has recently been shown to be the incidence of alpha particles (helium nuclei) on the semiconductor chip, each particle generating a a large number of electron-hole pairs before coming to rest. As the number of pairs produced is comparable to the charge stored in an individual element of the device each alpha particle can introduce a spurious signal. The alpha particles originate from the radioactive decay of minute traces of uranium and/or thorium present in the packaging material, and have an energy of about 5 MeV. When slowing down in silicon each particle travels about 25 microns and loses about 3.6 eV for each electronhole pair generated. Thus each particle generates approximately 1.4 x 106 electron-hole pairs over a distance of 25 microns.The soft error phenomenon is more fully described in New Electronics, 6th March, 1979 pages 30 to 40.
Various techniques have been suggested for overcoming alpha particle generated soft errors. In a large computer system it is possible to provide error detection and correction circuitry albeit with a consequent loss of speed. Another approach is very strict quality control of the packaging materials.
However, the necessary purification of the materials involved leads to a high cost of the finished product.
According to one aspect of the invention there is provided a method of protecting a semiconductor device fomed on a surface of a semiconductor body from alpha particle bombardment, including coating the surface with a layer of an organic polymer of a thickness greater than the expected path length in the polymer of alpha particles likely to impinge on the device.
According to another aspect of the invention there is provided an unpackaged semiconductor device formed in a surface of a semiconductor body, said surface being coated with an organic polymer layer, said layer having a thickness greater than the expected path length in the polymer of alpha particles likely to impinge on the device.
According to another aspect of the invention there is provided a packaged semiconductor device, including a semiconductor body mounted in a housing, and an organic polymer layer interposed between an active surface of the body and the housing, said layer having a thickness greater than the expected path length in the polymer of alpha particles originating from the housing material.
We have found that a coating of an organic film forming polymer applied to the active surface of a semiconductor device chip provides an effective shield against alpha particle bombardment.
The energy of alpha particles emitted during the decay of uranium and thorium is in the range 4 to 8 MeV. Such particles have a range of a few centimetres in air, but only a few microns in a solid material. However, their absorption distance in silicon is comparable with the dimensions of an integrated circuit.
It has been shown (Friedlander & Kennedy Nuclear & Radiochemistry Published 1962 by John Wiley & Sons Inc.) that the range of an alpha particle in a solid is given approximately by the empirical relationship Rz/Ra = 0.9 + 0.0275Z + (0.06 - 0.0086Z) log ElM where Z is the range in element Z expressed in milligrams per square centimetre, Ra is the range of the same particle in air, M is the particle mass number in this case 4 and E is the particle energy.
From the expression the range of 5 to 8 MeV alpha particles in a polymeric material has been calculated to be 20 to 100 microns, the exact range depending on the particle energy and the elemental content of the polymer. In general, polymers with a high carbon-hydrogen ratio are more effective as alpha particle absorbers.
An embodiment of the invention will now be described with reference to the accompanying drawings in which Figures 1 to 3 show various stages in the manufacture of a particle shielded semiconductor device.
Referring to the drawings, a semiconductor device chip 11,for example a random access memory, is fabricated by standard semiconductor processing techniques, the active device area being formed in one surface 12 of the chip. The chip 11 is then mounted on a package base consisting of a leadframe 13 attached to a ceramic and glass housing member 15. Wire bands 14 are provided between the leadframe and various terminal pads on the chip 11.
To provide the active surface 12 of the chip 11 with an alpha particle shield a measured quantity of a liquid organic monomer is applied to the surface 12 and allowed to flow into an even film 17. The film 17 is then polymerised e.g. by heating, by the application of ultraviolet or an electron beam, or by the action of a free radical catalyst added to the monomer prior to application. Various polymer systems may be employed for this purpose, but they must satisfy a number of conditions.
1. The polymer must not interact chemically with the active surface of the device.
2. The polymerisation reaction must not produce any harmful residues. The polymer should thus be of the olefinic type, which produces no residue, or of the condensation type which liberates water. This water then evaporates during the subsequent processing stages.
3. The material should be film forming in nature so that the monomer spreads readily and uniformly over the surface of the device.
4. The polymerised material should adhere to the device and should be sufficiently elastic to resist flaking and/or cracking during the subsequent processing of the device.
5. The polymer must be stable at the high temperatures involved during subsequent processing of the device.
We have found that a material that satisfies these requirements is the polyimide monomer material marketed by Hitachi under the trade name PIQ. This material was originally developed as a photoresist, but when applied to a semiconductor surface to a thickness of 20 to 100 microns it provides an effective alpha particle shield. The PIQ monomer is applied to each device chip by a hypodermic syringe, sufficient being applied to form a level surface, and is then cured by heating to 180 to 220 C and preferably to 200 C. This provides the required thickness.
Following curing of the polymer layer a housing lid 1Sis isplaced over the device and the housing is sealed in a furnace at a temperature of about 400"C, a solder glass film 19 sealing the joint between the two housing portions. PIO polymer films have been found to be stable under these conditions; the heating stage infact effects a final cure of the polymer.
The embodiment just described refers to the packaging of a device in a ceramic housing, commonly known as the CERDIP package. In an alternative embodiment (not shown) a plastics package may be employed. A similar technique can be used, but in this case the package is moulded around the device in a single operation. Also, as the tem peratures involved in the plastics moulding process are lower than those required for the ceramic package, the thermal stability requirement of the polymer is less stringent.
A number of polymer systems can be used as alpha particle shields. PIO and other polyimide resins have already been mentioned, but other materials include silicone rubbers and isoprene polymers. In other applications copolymer systems, e.g. butadiene/styrene may be employed.

Claims (14)

1. A method of protecting a semiconductor deviceformed on a surface of a semiconductor body from alpha particle bombardment, the method including, coating the surface with a layer of an organic polymer of thickness greater than the expected path length in the polymer of alpha particles likely to impinge on the device.
2. 2. A method as claimed in claim 1, wherein the polymer is a poly-imide.
3. A method as claimed in claim 1 or 2, wherein the polymer layer is formed by thermal curing of a liquid monomer applied to the major surface of the body.
4. A method as claimed in claim 1 or 2, wherein the polymer layer is formed by ultraviolet or electron beam curing of a liquid monomer applied to the major surface of the body.
5. A method as claimed in claim 1, wherein said polymer is a co-polymer.
6. A method as claimed in any one of claims 1 to .
5, wherein the device is a random access memory.
7. A method of protecting a semiconductor device formed on a surface of a semiconductor body from alpha particle bombardment, the method including applying to the surface a suficient quantity of a poly-imide liquid monomer to provide a uniform coating 20 to 100 microns in thickness, and curing the monomer at a temperature of 180 to 220 C to provide a uniform polymer coating.
8. A method of protecting an unpackaged semiconductor device against alpha particle bombardment substantially as described herein with refer encetothe accompanying drawings.
9. A method as claimed in any one of claims 1 to Sand which further includes packaging the protected device in a housing.
10. A method as claimed in any one of claims 1 to 8, and comprising placing the coated device in a ceramic multipart housing and subsequently sealing the parts of the housing with a bonding material by the application of heat, the polymer being substantially unaffected by the heat.
11. An alpha particle protected semiconductor device manufactured by a method as claimed in any oneofthe preceding claims.
12. An unpackaged semiconductor device formed in a surface of a semiconductor body, said surface being coated with an organic polymer layer having a thickness greater than the expected path length in the polymer of alpha particles likely to impinge on the device.
13. A packaged semiconductor device, including a a semiconductor body mounted in a housing, and an orgaic polymer layer interposed between an active surface of the body and the housing, said layer having a thickness greater than the expected path length in the polymer of alpha particles originating in the housing material.
14. A packaged or unpackaged alpha particle pro-.
tected semiconductor device substantially as described herein with reference to the accompanying drawings.
GB8000919A 1980-01-10 1980-01-10 -particle shielding of semiconductive device Expired GB2073946B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB8000919A GB2073946B (en) 1980-01-10 1980-01-10 -particle shielding of semiconductive device
DE19803048343 DE3048343A1 (en) 1980-01-10 1980-12-20 INTEGRATED SEMICONDUCTOR MEMORY
JP131781A JPS56104452A (en) 1980-01-10 1981-01-09 Method of manufacturing integrated circuit
FR8100284A FR2473788A1 (en) 1980-01-10 1981-01-09 METHOD FOR PROTECTING INTEGRATED SEMICONDUCTOR CIRCUITS AGAINST ALPHA PARTICLES AND DEVICES OBTAINED

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8000919A GB2073946B (en) 1980-01-10 1980-01-10 -particle shielding of semiconductive device

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Publication Number Publication Date
GB2073946A true GB2073946A (en) 1981-10-21
GB2073946B GB2073946B (en) 1983-11-23

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GB8000919A Expired GB2073946B (en) 1980-01-10 1980-01-10 -particle shielding of semiconductive device

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JP (1) JPS56104452A (en)
DE (1) DE3048343A1 (en)
FR (1) FR2473788A1 (en)
GB (1) GB2073946B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722119U (en) * 1980-07-15 1982-02-04

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GB2073946B (en) 1983-11-23
FR2473788A1 (en) 1981-07-17
JPS56104452A (en) 1981-08-20
DE3048343A1 (en) 1981-09-17

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PCNP Patent ceased through non-payment of renewal fee