GB2073549A - Improvements in or relating to circuit arrangements for testing electrical characteristics of both analog and digital trunk lines connected to transit telephone exchanges of digital type - Google Patents

Abstract

A circuit arrangement is provided for testing electrical characteristics of both analog and digital trunk lines connected to a transit telephone exchange of digital type comprising a central control unit CC for controlling switching of codes in a connection network RC. The circuit arrangement includes an interface unit UIR for the connection network, an analog trunk line testing unit UPA, a digital trunk line testing unit UPD, a stored program microprocessor MIP operating in time division multiplex, or an interface UIC for the central control unit. <IMAGE>

Description

SPECIFICATION Improvements to circuit arrangements for testing electrical characteristics of both analog and digital trunk lines connected to transit telephone exchanges of digital type The present invention relates to circuit arrange menus for use in transit telephone exchanges of digital type. Such arrangements are use for testing electrical characteristics, for instance of a connection network and of both analog and digital trunk lines connecting the transit telephone exchange to further switching telephone exchanges of traditional type, or of digital type.

The transit telephone exchanges of digital type must be equipped with a testing unit for effecting measurements of the following parameters: error rate measurement of the connection network; error rate measurement on PCM lines; slip rate measurement on PCM lines (shifting recovery between trunk timing and switching exchange timing); detection of the lack of interruption of analog trunk lines; measurement of cross-talk in analog trunk lines.

This latter type of measurement requires the presence of either an automatic call machine or an automatic reply machine, connected to the switching exchange to which the analog trunks relate.

According to the invention, there is provided a circuit arrangement for testing electrical characteristics of both analog and digital trunk lines connected to a transit telephone exchange of digital type which comprises a central control unit for controlling switching of codes arriving at a connection network by way of a plurality of both digital trunk lines and, via a multiplexer-demultiplexer, of analog trunk lines, the circuit arrangement comprising: an interface unit arranged to serially receive and send data and synchronizing signals from and to the central control unit and to send and receive messages to and from a bidirectional bus: a unitfortesting of analog trunk lines, comprising a receiving section arranged to detect, according to the time-division principle, the level at which the connection network, by way of n analog trunk lines, receives n test frequencies having a plurality of values transmitted by another terminal of the trunk lines, and a transmitting section arranged to generate in a digital way, according to the time-division principle, n test frequencies having a plurality of values; a unitfortesting digital trunk lines, connected to the bi-directional bus and comprising a transmitting section arranged to generate binary testing configurations and a receiving section arranged to compare the binary configurations generated by the transmitting section with the same configuration after they have been recycled by way of the connection network; a microprocessor connected to the bidirection bus and arranged to exchange messages with the central control unit, to co-ordinate operation of the circuit arrangement, and to receive the results of the tests performed by both the analog trunk line testing unit (UPA) and the digital trunk line testing unit; and an interface unitforthe connection network comprising a receiving section arranged to supply the testing units with bothtiming pulses and data and atransmitting section arranged to re-establish and code PCM signals to be sent the connection network.

Such a circuit arrangement may be used to measure in a short time the parameters referred to above of a transit telephone exchange of digital type.

The invention will be further described, by way of example, with reference to the accompanying drawing, in which: Figure lisa block diagram of a transit telephone exchange of digital type utilizing the circuital arrangement according to the present invention; Figure 2 shows a block diagram of the circuital arrangement UCIL of Figure 1 according to the present invention; Figure 3 shows a block diagram of the testing unit of the analogical trunks UPA of Figure 2 according to the invention; Figure 4 shows a block diagram of the testing unit of the digital trunks UPD of Figure 2 according to the invention; Figure 5 showsthe algorithm of a filtering section of the digital filter FD of Figure 3; Figure 6 shows the circuital arrangement realizing the algorithm ofthe filtering section according to Figure 5;; Figure 7 shows an embodiment according to the invention of the digital integrator ID of Figure 3.

Figure 1 illustrates a transit telephone exchange comprising a connection network RC designed to effect switching of PCM codes supplied to the transit telephone exchange by way of a plurality of trunk lines. The trunk lines of PCM type are directly connected to the connection network, whereas the analog trunk lines are connected to the connection network by way of PCM multiplexer-demultiplexers MD.

Figure 1 shows the transit telephone exchange connected to a digital telephone exchange DE, which is associated with PCM trunk lines as well as with analog trunk lines by way of a multiplexerdemultiplexer MD. If the telephone exchange DE were a further transit telephone exchange, it would be connected to another circuit arrangement UCIL constituting a preferred embodiment of the present invention. The transit telephone exchange is also connected to a conventional telephone exchange CE, which is associated with a PCM multiplexerdemultiplexer MD as well as analog trunk lines. The exchange CE is further associated with an automatic call machine MCA of known type, or with an automatic reply machine DRA, whose operation is described hereinafter.

Switching of codes arriving at the connection network RC is controlled by a central control unit CC which is connected to a signalling control unit UCS as well as to a circuit arrangement UCIL constituting a preferred embodiment of the present invention.

The central control unit CC is also connected to an operator's position PO. Let us assume that, during a generic machine cycle of the arrangement UCIL, testing often trunk lines of PCM type of twenty analog trunk lines is to take place. Under these circumstances, because analog trunk lines are involved, the machine MCAorthe machine DRA wil be activated according to whether the arrangement UCIL is oper- ated to receive the frequencies orto send the test frequencies.

The unit CC controls routing ofthe codes in time channel O comprising the ten digital trunk lines undertest and the codes expressing the frequencies available on the twenty analog trunk lines to the arrangement UCIL, which can perform at most thirty simultaneous tests and two self-diagnosis tests.

The thus-routed codes are allocated in thirty pro- cessing phases of the arrangement UCIL each having a duration of about4 spec. and a repetition time of 125ssec., the arrangement being abieto process the thirty received codes and the two self-diagnosis tests simultaneously.

The detection of the aforesaid parameters requires more machine cycles at the edn of which the arrangement UClL informs the central control unit CC aboutthe result of the performed tests. The arrangement UClL of Figure 2 comprises an interface unit UIR which is connected to the connection net work RC by way of a bi-directional service PCM connection at2,048 M bit/sand which comprises a receiving section SR@ and a transmitting section ST@.

The section SRr is designed to process synchronizing words A and B allocated in the timing channel O of the PCM frame, as well as to generate alarm signals when the received signal does not have the required features (e.g. lack of receiving pulses, etc.).

Thetransmitting section STr is contrarily designed to form the PCM frame and in particulararrangesthe insertion ofthe synchronizing wordsAand B into channel 0 and provides for coding the signal before sending itto the connection network RC. Moreover, the receiving section SRrsuppliestwo units UPA and UPD with timing pulses CK having a frequency of 2,048 M bites as well as data coded in 8 bits together with the receiving timing channel counting and synchronization signal).

The transmitting section ST@ serially receives data from the units UPA and UPD as well as a synchronizing signal to which the establishment of the transmission PCM frame is to be aligned. The unit UlR is connected to the unit UPA, which is designed to perform tests on the analog trunk lines. The unit UPA essentially comprises a receiving section SRa arranged to receive during the frame time interval (125 sec.) up to 30 codes relating to as many test frequencies transmitted by way of analog trunk lines and 2 codes internally generated according to selfdiagnosis.The unit UPA further comprises a transmitting section STaarranged to generate, during the frame time interval and in a digital way, at most 32 frequencies of which 30 frequencies are employed during the tests and 2 in self-diagnosis, and an interface unit Ul, for a bidirectional bus. The sections SRa and STa are further described hereinafter.The unit UIR is further connected to the unit UPD which is designed to perform tests on digital trunks. lt is capable of perform up to 30 simultaneous tests and 2 self-diagnosis tests until the 32 available processing phases are completely engaged and it is further ananged to perform all the necessary operations within each plhase. The unit UPD essentially corn prises a transmitting section STd and a receiving section SRd, which are further described hereinafter.

The section STd receives by way of a bidirectional butthe binary configurations which areto be sentto the connection network RC, through the interface unit UIR. The unit SRd receives from the interface unit UlB the codes generated by the section ST,d and recycled by way ofthe connection network RC, and further receives the synchronizing word B allocated in the timing channel 0 of the PCM systems to he tested. The bidirectional bus is connected to a microprocessor MIP of known type, which essentially comprises the following modules:: central process unit, CPU; time base generator, TBG; recognition module for interruption requests; random access memory module, RAM; read-only memory module, ROM; module for direct ,data transfer into memory; and parallel input-output module, 1/0.

The microprocessor MIP is required to perform the following operations; to operate the unit UCIL to receive and checkthe corrctness of the messages sent from the central control unit CC; to activate the respective processes; to co-ordinate all the operations (how data are to be exchanged with UPA and UPD, test timing, etc); and to handle the diagnostic signaling from the modules Upland UPD.

The bidirectional bus is further connected to an interface unit UIC forthe central control unit, the interface unit being arranged to serially receive or send data and synchronizing signals from orto the central control unit CC, and to exchange signals with the microprocessor MIP by way of the bidirectional bus through input/output gates.

The availability to receive and send messages to the microprocessor MIP is signalled byway of interruption levels.

Figure 3 shows the block diagram of the unit UPA, whose receiving section SHa receives from the receiving section SRr of the unit UlR the timing pulses CK=2,048 M bites, synchronizing pulsessn, and 8 bit codes cd relating to signal patterns trans- mitted by way of analog trunk lines, on which an attenuation test is to be performed.

Let us assume that the test requires sending by unit MCA (see Figure 1) associated with the switching exchange CE ofconventional type and connected to The analog trunk lines under test of a test from quency at 425 Hzand at 850 Hz, respectively, liy way of trunk lines g1 and g1+1, respectively.

These frequencies are generated by the unit MCA in an analog way at a prefixed level and, while passing along the analog trunks gi and g@+@, respectively, they undergo an attenuation so that, atthe input of the unit MD provided in the transit exchange, they have a lower level than that at the output of the exchange CE.

The unit UCIL is designed to measure the level of the frequencies at the input ofthe unit MD, in order to detect whether the attenuation has an acceptable value.

The unit MD provided for sampling and coding such frequencies and the codes thus obtained are switched to the input of the unit UCIL and allocated in the processing phases, and,ffli+1, respectively, of the receiving section SRa of the unit UPA.

In particular, such codes arrive at a series-parallel converter circuit CR for the incoming data, the circuit CR being arranged to write the codes in a suitable register at a prefixed time instant. 8 bit codes are then supplied in parallel to the input of an expansion circuit ES, arranged to perform conversion of the 8 bit codes into a 12 bit code. The output of the circuit ES is connected to a digital filter FD, which operates according to the time-division principle and has an input arranged to receive prefixed coefficients, whose modification allows the filter tuning frequency to be modified. The coefficients are stored in a coefficient memory MC. The memory MC is addressed by a decoding unit DC, of the coefficient addresses, which is supplied by a sequence of timing pulses CK generated by a timing unit UT.The unit UT is formed by a phase-locked circuit, whose input receives the sequence of timing pulses CK and the synchronsing pulsessn.

During the processing phasejof the unit UPA, the digital filter FD receives 12 bits relating to a sample of the 425 Hz test frequency. Thus, at the output of the memory MC, there is available a coefficient which tunes the filter to such a frequency. During the processing phase +1, the filter FD receives 12 bits relating to a 850 Hz test frequency. Thus, at the output of the memory MC there is supplied a different coefficient from the previous one, which tunes the digital filter to this latter frequency. The digital filter FD is further described hereinafter with reference to Figures 5 and 6.

The output of the digital filter FD is connected to a digital integrating circuit ID, which detects during phases and6+1, respectively, the average values of the signal samples relating to test frequencies at 425 HZ and 850 Hz, respectively, which are available at the output of the digital filter, the circuit ID being further arranged to code the detected average value.

The average values thus obtained express the level provided by the two testing frequencies whenever they are available at the input of the multiplexerdemultiplexer MD (see Figure 1). The two codes relating to the average values are stored in as many lines of a data memory DT, whose contents is destined to be transferred to the unit MIP through a direct data transfer DMA into the respective memories.

Assuming that the microprocessor MIP knows the level at which the two test frequencies have been generated by the unit MCA, it can determined the attenuation undergone by the frequencies by comparison between the level at which the frequencies have been transmitted and that at which they have been received.

The unit UPA generates prefixed test frequencies which are sent the unit DRA, associated with the telephone exchange CE of conventional type, by way of analog trunk lines.

Accordingly, the unit DRA analogically compares a reference signal and a continuous signal relative to the average value of the received test frequency, thus detecting whether the attenuation of the test frequencies has an acceptable value. The unit UPA includes the interface unit Ula, which comprises a memory arranged to receive from the microprocessor MIP the code relating to the emission order, during the processing phase of a test frequency of 425 Hz for example, and during the processing phase ss+1 of a test frequency at 850 Hz.

The transmitting section STa comprises a unit DO1+1 controls a signal generator GS of digital type, which consists of a read-only memory in whose cells are written codes relating to signal samples, whose integration allows a sinusoidal signal to be obtained.

The read-only memory is addressed by way of counters also in the generator GS, whose counting signal has a period depending on the value of the frequency to be generated.

During the processing phases, the generator GS generates a code expressed in 12 bits and relating to a signal sample of the 425 Hz sinusoidal signal, whereas during phase,+1 the output of the generator GS provides a 12 bit code expressing a signal sample of the 850 Hz sinusoidal signal.

The output of the generator GS is connected to a compression circuit CM1 arranged to convert the 12 bit code into an 8 bit code which arrives at a parallel-series converter circuit CS which sends the codes to the transmitting section STa of the unit UIR through which the PCM frame is re-established.

The connection network RC switches the codes to the unit MD, which is connected to the analog trunk lines under test. The unit MD performs digital-analog conversion and sends to the two tested trunk lines the frequencies at 425 Hz and 850 Hz, respectively.

The exchange CE switches the frequencies to the input of the automatic reply machine DRA, which detects the attenuation according to the described embodiment.

The unit UPD of Figure 4 is designed to perform tests on the digital trunk lines as well as on the connection network RC. In particular, the unit UPD is capable of performing the following tests: error rate measurement of PCM lines; slip rate measurement of the line units which are connected to PCM systems entering the connection network RC; error rate measurement of the connection network.

The first measurement is to test the synchronizing word B of the time channel O relative to the line unit connected to the PCM turn line to be tested. The line unit tests the lining-up word and detects in the word possible errors which are indicated by setting to "1" the third bit of the time channel O relative to frame B.

The time channel 0 relative to the PCM system in question is switched to a processing channel of the unit UCIL. The measurement is performed by counting how many times the third bit has logic value "1", when the second bit of the synchronizing word also has logic value "1" (odd frame) during a prefixed number of seconds.

Testing by the unit UCIL is controlled by the mic roprocessor MIP, which has the task to: receive and decode orders from the central control CC; communicate the test parameters to the unit UPD; read the test result from the unit UPD.

The activation control of the test is generated by the unit MIP, which communicates to the unit UPD the test code and the number of the channel on which the test is to be performed. The unit MIP enters in its counters the time of the test performance.

At the expiration of time, the unit MIP sends the result of error counting expressed in 16 bits and then communicates to the central control CC the detected error rate, if this is predetermined tolerances.

Otherwise, a failure signal is generated.

The second measurement also relates to the testing of the synchronizing word B of the time channel O relating to the line unit connected to the PCM trunk line under test. The line unit tests and stores the slip event of its own elastic memory.

The elastic memory slip is stored by complementing the state ofthe fourth bit ofword B placed in the time channel 0 of the line unit under test.

The time channel 0 of the line unit undertest is switched to a processing phase of the unit UCIL, which effects measurement by counting how many times the fourth bit of the synchronizing word changes its state in a prefixed time interval.

Both the above-described tests require only the employment of a reception channel of the unit UCIL, whereas the error rate measurement of the connec -tion network requires the employment of both transmission and reception channels. This latest measurement is performed with the aid of a line unit of the connection network connected to a PCM trunk line undertest The line unittests and stores the slip event of its own elastic memory.

The elastic memory slip is stored by complement ing the state of the fourth bit of word B placed in the time channel 0 of the line unit under test. The time channel 0 of the line unit under test is switched to a processing phase of the unit UCIL, which effects measurement by counting how many times the fourth bit of the synchronizing word changes its state in a prefixed time interval.

Both the above-described tests require only the employment of a reception channel of the unit UCIL, whereas the error rate measurement of the connection network requires the employment of both transmission and reception channels. This latest measurement is performed with the aid of a line unit of the connection network connected to a PCM trunk line and through the employment by the unit UCIL of two transmission channels T1, T2 and a receiving channel R,. The transmission channel T1 and the receiving channel R1 must have the same address; in the transmission channel T2there is placed a loop locking control to be sent to the line unit involved in the test.

On the reception of the loop control sent in T2, line unit is loop-locked, sending in R1 the bits generated by way of the transmission channel T1. The binary configuration received by way of the reception channel R1 is compared with the transmitted one and the numberofwrong bits is counted. The unit UPD includes a transmitting section STd which comprises a transmitting memory RAM1 to which the unit MIP transfers the binary configurations under test; as the emission of at most 16 configurations is provided for each channel, the memory RAM1 has a capacity 16.32. 8.

Togther with the binary configurations cb to be transmitted in a generic channel, the unit MIP also furnishes the writing address in of the binary configration. This writing address coincides with the address of the channel destined to receive the binary configurations.

The output of the memory RAMf is connected to a transmission unit TR arranged to inspect cyclically the memory cells as well as to send serially the con; tents of the cell which, in the considered instant, is to be transmitted to the connection network.

The binary configuration sent to the connection network is further transmitted to a buffer register RT1, which provides for transferring each test binary configuration on the receiving section SRd of the unit UPD in order to allow the relative comparison with the same recycled binary configuration by way of the connection network RC.

The receiving section SRd includes a data register RD, which is arranged to receive from the interface unitwith the connection network UIR the 8 bit codes allocated in the timing channel 8 of the PCM trunk line under test, and an address register RI, which receives from the unit UIR the channel address, to which the associated data refer.

The unit SRd further includes an order memory MO to which the unit MIP transfers a code or relating to the type of operation to be performed within each processing phase. The unit MIP also furnishes an address in relating to the number of the processing phase during which the order is to be fulfilled.

The contents of the address register RI and the address furnished by the unit MIP are compared in a comparator CM; on detecting identity between the codes present at its inputs, it energizes one of its outputs, thus enabling the storage of the order given by the unit MIP in the order memory MO.

The codes in register RD arrive at the input of a read-only memory ROM1, which performs a transcoding operation, since it converts the 8 bits available atthe input into a further8 bits available at the input into a further 8 bit code which facilitates the test of the state of the aforesaid bits.

The code available at the output of the memory ROM, arrives at a microprogrammed counting unit UCM, which exchanges signals with a state memory MS arranged to store the state of the outstanding test during each processing phase and which further exchanges signals with a work memory ML arranged to store codes needed by the unit UCM in order to perform the aforesaid detections. The unit UCM further exchanges signals with first and second memories CT, and CT2, which are arranged to store the result of the tests performed bythe unitUCM on the aforesaid bits 2,3 and 4 and to store the number of errors made by the connection network.

The units CT, and CT2 have a capacity 32. 16, since the computation result for each test is expressed in 16 bits, so that the number of errors made by the PCM trunk line under test may be stored for instance in the unit CT1, whereas the number of slips effected by the elastic memory in the line unit under test may be stored in the unit CT2 during a processing phase analogous to that during which the error rate of the unit CT, has been stored. Alternatively, the number of errors made by the connection network may be stored during one of the remaining phases in either the unit CT, orthe unit CT2.

The unit SRd further comprises an output register RU, for sending to the unit MIP the computation result stored in the units CY, and CT2 as well as the contents of the units MS and ML, and a buffer register RT2 for sending to the unit ROM1 the contents of the buffer register RT1 provided in the transmitting section STd.

The unit UCM is arranged to perform the following operations: to detect how many times both second and third bits of the code in the register RD have logic value 1 and to determined the increase in the content of a respective phase of the unit CT1, when the detection gives a positive result; to detect the number of state variations of a fourth bit in the register RD and to increase the content of a respective phase of the unit CT2 when the detection has a positive result; and to detect the number of errors in the code in the register RD, with respect to the code in the register RT2 and to increase the content of a respective phase of the unit CT1 or CT2, whenever it detects the presence of an error.The results of the measurements performed by the unit UCM are therefore available in the units CT1 and CT2 and can be read by the unit MIP both at the expiration of the test execution and at intermediate time intervals. Figure 5 illustrates an algorithm of a filtering cell of the digital filter FD of Figure 3. The filter FD consists in fact of four cells in cascade of the second order having a structure according to fundamental rules. The frequency response is obtained by applying the transformation of a CAUER's analog low-pass filter into a digital band-pass filter by means of a bilineartransformation process. A second order cell is capable of performing in 2,asec. the addition, multiplication and division operations provided by the algorithm. Such a filter is therefore able to build up 64 numerical filtering cells of the second order in a time-division frame.The algorithm provides the performance of a first addition operation between the 12 bits relating to frame T1 of a generic channel and the bits corres- ponding to the output of first and second multipliers, whose multiplication coefficientsc and d, respectively, represent the coefficient of first and second degree, respectively, of the poles. The input of the first multiplier receives a codex relating to frame t-1, which is stored in a first section of a unit M, whereas the input of the second multiplier receives a code y relating to frame T1~2, which is stored in a second ofthe unit M. The code y is also supplied to a third multiplier, whose multiplication coefficientb represents the second degree coefficient of the zeros.

The performance of a second addition operation is also provided at the output K1 of the first adder, the output of a third multiplier and that of a fourth multiplier, whose input receives the codex relating to frame tE and has a multiplication coefficienta which represents the first degree coefficient of the zeros.

The output K2 of the second adder provides a gain higher than 1 so that a divider DV is provided to normalize the gain to unity.

Figure 6 shows a circuit arrangement for realizing the filtering cell, whose algorithm has been illustrated in Figure 5.

The filtering cell receives channel timing signals and frame timing signals ct, which are to be decoded in order to obtain the pulses controlling the processing phases of the cell. The cell comprises a random access memory RAM2, which comprises 32 memory lines equal to the number of channels provided in each frame.

The memory RAM2 further comprises a first section arranged to store wordsx, and a second section arranged to store words y.

According to the algorithm each word is to be formed by 16 bits; the memory RAM2 consequently has a capacity 32. 32 and has been implemented in the embodiment with a memory 256.4.

The output of the memory RAM2 is connected to a multiplexer MT1, whose output signals are supplied to a shift register RSa, arranged to receive in parallel 4 bits and to enable the relative shifting in series.

The first four outputs of the register RSa are supplied to the input of a multiplying circuit ML, which is designed to reduce to 17 the number of bits resulting from the product performed by said circuit.

The last four outputs of the register RSa are sup plied to a register RSb, which is similar to RSa and whose last four outputs are supplied to a second input of the multiplexer MT1. The second input of the multiplier ML receives the aforementioned coefficients, whose values determine the tuning frequency of the filter. The coefficients are stored in a coefficient memory MC (see Figure 2) and applied to unit ML by way of a coefficient register RC.

The output of the multiplier ML is connected to a register RP of the product and partial results, whose output is connected to the input of a second multip lexer MT2 and may be further recycled and applied to a further input of the multiplier ML. The multiplexer MT2 further receives the 12 input bitsdiwhich are available at the output of the expansion circuit ES (see Figure 2), as well as the output of the divider DV.

The output of the multiplexer is connected to a summing circuit CS, whose input further receives the output of a storing register RA, to which are sup plied the bits available at the output of the summing circuit CS.

By means of a logic unit LC arranged to perform a contraction operation from 17 to 16 bits, the output of the register RA is applied to a writing unit US which, during four consecutive phases, enables in the memory RAM2 the writing of the bits available at the unit LC.

As shown in Figure 6, the four multiplication oper ations of Figure 5 are performed by the multiplier ML in successive time intervals; similarly, the two addi tion operations are performed by the summing circuit CS in successive time intervals. The performance of the operations according to the algorithm illustrated in Figure 5 occurs in five consecutive phases. The first one provides the sum, by way of the circuit CS, of the input bits di with the result of multiplication x.c, where x represents the code extracted from the first section of the memory RAM2, in which the preceding frame had been written and c represents an 8 bit coefficient present in register RC.

The value of said coefficient depends on the frequency to be filtered.

The performance of the operation provides: the performance of multiplicationx.c in four consecutive phases executing four partial products (8.4) by means ofthe multiplier ML.

These partial products are stored in the unit RP, whose contents are recycled at the input of the unit ML; the selection of the input bitdiperformed by multiplexer MT2 which sends itto the unit CS, said unit providing for summing itto the contents (initially 0) of the storing register RA. The result of the addition is stored again in the storing register RA; the sum of the contents of the register RA with the productx.c available at the output of the register RP; the store of the sum di +x.c in the register RA.

The second phase provides the sum, performed by the unit CS, of the contents of RA with the multiplication result of y.d, where y is a 16 bit datum extracted from the second section of the memory RAM2, in which the preceding frame had been stored, and d is an 8 bit coefficient extracted from the memory MC via the register RC.

The performance of the operation provides: the execution of y.d multiplication in fourconsecutive phases similarly to the aforesaid; the sum of the contents of the register RA with the producty.d, as well as the storage of the sum in the register RA in order to have: k, = di +x.c + y.d; the storage in the first section of the unit RAM2 of datum k, by way of four consecutive writing operations (k, is to be extracted from the successive frame as datumx).

The third phase provides the sum of k, with the productx.a, wherex is represented by a 16 bit datum in the register RSb, and a is a 8 bit coefficient in the memory MC.

The performance of the operation provides: the- execution of a multiplicationx.c according to the aforesaid: the execution of a multiplication xe according to the aforesaid; the execution of the sum of the multiplication result with the contents k1 of the register RA; the storage of datum in the second section of the memory RAM2 (said datum x is to be extracted from the successive frame as datum y).

The fourth phase provides the sum ofthe register RA contents with the multiplication result yb, where y is a 16 bit datum in the register RSb, and h is an 8 bit coefficient.

The execution of the operation provides: the execution of the sum of the multiplication result with the content of the register RA, so as to obtain: k,= k, +x.a +y.b.

The fifth phase provides that datum k2, represented as a 17 bit datum, since it considers the gain (in band) of the cell, be reduced to a value corresponding to the unitary gain of the cell (12 bits).

Accordingly, the fifth phase provides: the execution by the unit DV of the division of the contents k2 of register RS; the emission of the result in order to allow the relative processing performed by the second cell.

Figure 7 illustrates the block diagram of the digital integrator ID, which includes a compression circuit CM2, whose input receives the 12 bit channels available at the output ofthe digital filter FD. The output of the circuit CM2 is supplied as a 7 bit code to a comparison circuit CF1, whose second input receives a 7 bit code, later on called mean which is available at the output of a mean counter CN1.

The comparison in the circuit CF1 between the output of the circuit CM2 and the "mean" datum, relative to the mean value of the data present in that channel during the preceding frame, is performed with means value/2.

The output of the comparison circuit CF, is supplied to a logic network RL, in order to adapt the contents of counter CN, according to the following provisions.

The value of the "mean" of each channel is stored in a random access memory RAM2 having a capacity 32.8 which, at the beginning of each phase transfers the previous "mean" value into the counter CN,.

The output of the counter CN, addresses a readonly memory ROM2 arranged to perform a transcoding operation in order to render available at the outputs codes expressing the power corresponding to each "mean" value. The transcoded codes are supplied to a second comparison circuit CF whose other input receives the output of the memory RAM3.

The output of the circuit CF2 is supplied to a logic network RL2 arranged to test the result of the comparison performed by CF2 and to control a counter CN2 of the up/down type.

At the beginning of each timing phase, the number reached by the counter in the previous cycle is inserted in the counterCN2. This number is stored in a random access memory RAM4 in which, at the end of each timing phase, is inserted the contents of the counter CN2.

A decoding unit DC2 is arranged to energize its output when CN2 exhausts either its up or down counting capacity.

The energization of the output of the unit DC2 enables a multiplexer MT3 to generate at its output the code available at the output of the memory ROM2 in order to adaptthe "mean" value in the memory RAM3, by way of a multiplexer MT4.

The code at the output of the multiplexer MT2 is further supplied to an output register RU2.

The circuit arrangement aims to determine the average powerofthe signal supplied by the digital filter. A minimum time interval t, is provided to detect a tone really present and a maximum time interval t2 for interrupting the tone which is not to be detected by the integrator.

The unit CF, performs the comparison between the input code and the "mean" code detected during the preceding cycle and the result of the comparison allows the unit RL, to perform the following operations: if the input code is higher than "mean"/2, RL, determines an increase in CN, by a number of steps ranging from 1 to 4; if the input code is equal to "mean", this latter is left unchanged; if the received code is lowerthan "mean"/2, RL, decreases CN, by one step.

The unit RL, determines the numberz of pulses by which CN, is to be incremented by determining the ratio between the number written in the counter CN, and the number df frames present during the time interval t2.

Ift2 = 8 m sec. and the number written in CN2 is 255 255, then z =-4.

8.8 As CN2 is decreased by only one unit, whereas the increase may be effected up to four steps, the circuit is made insensitive to the microinterruptions of the test frequency.

The memory ROM2 provides at the output a code expressing the detected power.

In order to eliminate fluctuations of the thusdetermined power value, the unit ID further comprises means capable of adapting the value written in the memory RAM3 only if there is detected a prefixed number of either positive to negative increases. In fact, should the detected value be ranging around the value detected during the preceding cycle, the contents of the memory RAM3 are not adjusted, so that the value detected during the previous cycles is sent to the register RU2.

The unit CF2 effects the comparison between level 1 a detected during phased and level 1 k detected during phasea-,.

The result of the comparison enables the unit RL2 to perform the following operations: if 1 a is higher than 1k the counter CN2 is increased by a step; if 1 a is equal to 1k no operation is performed; if 1 a is lowerthan 1 k, the counter CN2 is decreased by a step.

As long as the counter CN2, at the considered phase, has not exhausted its own counting cycle, the register RU2 receives by way of MT3 the value 1 k stored in RAM3 and detected during the preceding cycle. When the counter CN2 exhausts its own counting cycle, there occurs energization of DC3, which determines the emission, by way of MT3, of the adjusted value la available at the output of ROW3, thus enabling RU to receive the said adjusted level 1a.

Claims (11)

1. A circuit arrangement for testing electrical characteristics of both analog and digital trunk lines connected to a transit telephone exchange of digital type which comprises a central control unit for controlling switching of codes arriving at a connection network by way of a plurality of both digital trunk lines and, via a multiplexer-demultiplexer, of analog trunk lines, the circuit arrangement comprising: an interface unit arranged to serially receive and send data and synchronizing signals from and to the central control unit, and to send and receive messages to and from a bidirectional bus; a unit for testing of analog trunk lines comprising a receiving section arranged to detect, according to the time-division principle, the level at which the connection network, by way of n analog trunk lines, receives n test frequencies having a plurality of values transmitted by anotherterminai of the trunk lines, and a transmitting section arranged to generate in a digital way, according to the time-division principle, n test frequencies, having a plurality of values; a unis fortest- ing digital trunk lines, connected to the bidirectional bus and comprising a transmitting section arranged to generate binary testing configurations and a receiving section arranged to compare the binary configurations generated by the transmitting section with the same configurations afterthey have been recycled by way of the connection network; a microprocessor connected to the bidirectional bus and arranged to exchange messages with the central control unit, to co-ordinate operation of the circuit arrangement, and to receive the results of the tests performed by both the analog trunk line testing unit (UPA) and the digital trunk line testing unit; and an interface unit for the connection network comprising a receiving section arranged to supply the testing units with both timing pulses and data and a transmitting section arranged to re-establish and code PCM signals to be sent to the connection network.

2. A circuit arrangement as claimed in claim 1, in which the digital trunk line testing unit is arranged to count in a prefixed time interval how many times logic value 1 is provided by bit 3 of a synchronising word associated with a frame transmitted by way of a digital line under test, and to count the number of state variations of bit 4 associated with the said synchronizing word.

3. A circuit arrangement as claimed in claim 1 or 2, in which the receiving section of the analog trunk line testing unit-comprises: a parallel-out circuit arranged to supply in parallel received codes at prefixed time instants; an expanding circuit arranged to expand to a larger number of bits codes at the output of the parallel-out circuit; a digital filter arranged to filter, according to the time-division principle, codes at the output of the expanding circuit, the filter being tunable tox frequencies in response to the application, on an input, ofx groups of coefficients; a coefficient memory arranged to store thex groups of coefficients to be supplied to the digital filter; a first decoding unit arranged to address the coefficient memory; a timing unit arranged to supply the first decoding unit with the timing pulses for generating addresses of the coefficient memory; a digital integrator arranged to provide at each processing phase the average value of the codes at the output of the digital filter and to convert the code relating to the average value into a code relating to its power; and a data memory arranged to store the codes at the output of the digital integrator at the end of each processing phase.

4. A circuit arrangement as claimed in any one of the preceding claims, in which the transmitting sec tion of the analog trunk line testing unit comprises: a decoding unit for decoding orders supplied by the microprocessor and stored in a memory of an interface unitforthe microprocessor; a signal generator arranged to generate in a digital way, according to the time-division principle, n test frequencies having a plurality of values; a first compressor circuit arranged to compress to 8 bits, 12 bit codes atthe output of the signal generator; and a series-out circuit arranged to supply the codes from the output of the first compressor circuit.

5. Acircuit arrangement as claimed in anyone of the preceding claims, in which the transmitting section of the digital trunk line testing unit comprises: a first random access memory arranged to receive from the microprocessor prefixed binary test configurations which are to be sent, during a processing phase,, to a line unit which is connected to the PCM trunk line under test and which has received a loop closing control signal during the phase$~1; a transmitting unit arranged to inspect the cells of the first random access memory and to serially generate the binary test configuration, which, at a generic instant, is to be sentto the transmitting section of the interface unit for the connection network; and a first buffer register arranged to store the binary test configuration at the output of the transmission unit

6. A circuit arrangement as claimed in any one of the preceding claims, in which the receiving section of the digital trunk line testing unit comprises: a data register arranged to receive from the receiving section of the interface unitforthe connection network the binary configurations to be tested; an address register arranged to receive from the receiving section of the interface unit for the connection network the number of the trunk line to which the binary configuration stored in the data register relates; an order memory arranged to receive from the microprocessor a code relating to the type of operation to be performed on the binary configuration present in the data register; a comparator circuit arranged to compare the address contained in the address regis tes with an address supplied by microprocessor and to energize its output to cause writing of the code at the input of the order memory when the addresses are identical; a second buffer register arranged to receive the binary configurations contained in the first buffer register; a first reading-only memory arranged to perform a transcoding operation of the codes at the output of the data memory and of the codes at the output of the second buffer register; a microprogrammed metering unit arranged to perform the aforesaid operations on the codes at the output of the first reading-only memory; a state memory arranged to store the condition of the outstanding test by the metering unit in each processing phase; a work memory arranged to receive from the metering unit the codes necessary to the test execution; first and second metering memories arranged to receive from the metering unit the result of the tests performed on the codes received at its input; and a first output register arranged to receive the contents of the first and second metering memories before being sent toe microprocessor.

7. Acircuit arrangement as claimed in claim 3 or in any one of claims 4to 6 when dependent on claim 3, in which the digital filter comprises a plurality of cells, each arranged to perform an algorithm comprising the following operations; a first addition operation between the codes relating to a frame T of a generic channel and the codes at the outputs of first and second multipliers arranged to multiply the codes relating to a frame Ti~, and to a frame To~2, respectively, with first and second multiplication coefficient representing the first and second degree coefficients, respectively, of poles of the filter response, a second addition operation between the result of the first addition operation and the codes at the outputs of second and third multipliers arranged to multiply the codes relating to frames Ti-l and t-2, respectively, with third and fourth multiplication coefficients representing the first and second degree coefficients, respectively, of zeros of the filter response; and a division operation on the result of the second addition operation.

8. A circuit arrangement as claimed in claim 7, in which each cell of the digital filter comprises: a second random access memory comprising a first section arranged to store the codes relating to the frames Tilt and a second section arranged to store the codes relating to frames To~2; a first multiplexer whose first input is arranged to receive the codes at the output of the second random access memory; a first shift register whose input is arranged to receive the codes at the output of the first multiplexer; a multiplier arranged to perform the multiplication between a coefficient, contained in a coefficient register connected to a coefficient memory, and a prefixed number of bits at the output of the first shift register; a partial result register whose input is arranged to receive the output of the multiplier and whose output is connected to a further input of the multiplier; a second multiplexer, a first input of which is arranged to receive the codes relating to the frame T, a second input of which is arranged to receive the codes at the output of the partial result register, and a third input of which is arranged to receive the output of a divider circuit; a summing circuit arranged to sum the codes at the output of the second multiplexer and the codes at the output of an accumulator register; the accumulator register which is connected to the output of the summing circuit and whose output is connected to the input of the divider circuit; a compression logic unit arranged to compress the code at the output of the accumulator register; and a writing unit arranged to perform writing of the codes at the output of the logic unit in the second random access memory.

9. A circuit arrangement as claimed in claim 3 or in any one of claims 4 to 8 when dependent on claim 3, in which the digital integrator comprises: a second compressing circuit whose input is arranged to receive the codes at the output of a digital filter; a first comparison circuit arranged to compare the code at the output of the compressing circuit with the code at the output of a first counter; a logic network arranged to increment the first counter by one or more steps when the code at the output of the compressing circuit is higher than the code at the output of the first counter, and to decrement the first counter by one step when the code at the output of the compressing circuit is lower than the code at the output of the first counter; a third random access memory arranged, at the beginning of each processing phase, to transfer into the first counter the code relating to the average value detected during the preceding cycle; a second reading-only memory whose output is arranged to generate codes relating to the power of the codes at the output of the first counter; a second comparison circuit, whose first input is connected to the output of the second reading-only memory and whose second input is connected to the output of the third random access memory; a second logic network arranged to increment or decrement a second counter of up/down type, according to whether the code at the first input of the second comparison circuit exceeds or does not exceed the code at the first input; a fourth random access memory arranged to transfer to the second counter, at the beginning of each timing phase, the content it reached during the preceding cycle; a second decoding unit arranged to energize its output when the second counter exhausts its capacity; a third multiplexer arranged to be controlled by a signal at the output of the second decoding unit and having a first input connected to the output of the third random access memory and a second input connected to the output of the second reading-only memory; a fourth multiplexer arranged to send to the third random access memory the code at the output of the first counter or the code at the output of the third multiplexer; and a second output register arranged to receive the code atthe output of the third multiplexer.

10. Acircuit arrangement substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

11. Atransittelephone exchange including a circuit arrangement as claimed in any one of the preceding claims.