GB2073487A - Semiconductor memory device - Google Patents

Description

1 GB 2 073 487 A 1

SPECIFICATION

Semiconductor memory device This invention relates to a semiconductor memory device and in particular to a non-volatile erasable programmable read-only memory (EPROM) device.

Figure 1A of the accompanying drawings shows a prior art EPROM cell 110 having a floating gate 114F for controlling the writing and reading of each cell. With no charge on the floating gate 114F, the cell is normally in a low threshold state (VT + 1.OV). It may be programmed to a high threshold state (VT:-:- + 5V) by applying a high voltage VD to the drain 120D and a high voltage Vc to the control gate 114C (VD is typically 10 1 5V and Vc is typically 20-25V with the soUrce voltage Vs = OV, and the substrate bias voltage V8 = OV). The shifting of the threshold voltage is accomplished through hot electron injection at the drain pinch-off region of the channel, as shown schematically by the arrows beneath floating gate 114F in Figure 1A. The injected electrons are permanently trapped on the polysilicon floating gate 114F which is isolated from the substrate V5 and control gate by dielectric layers 126C and 126F. Layer 126F is made of a thermal oxide (such as Si02) and 15 is usually approximately 1000 A (100 nm) thick. The presence of excess electrons on the floating gate 114F requires the control gate voltage Vc to go to a more positive voltage to reach the inversion (or "threshold") voltage. A cell written into its high threshold state will not conduct when Vc is + 5V during the read cycle. All cells 110 in a memory array can be erased by illuminating the array with ultraviolet radiation, which provides the trapped electrons with suff icient energy to escape from the floating polysilicon gate into the Si02 dielectric layers above or below it, to be collected in the substrate or by the floating gate (this is known as internal photoemission). Alternatively the array can be erased by applying a strong electric field between the floating gate and the control gate or substrate, resulting in momentary electronic conduction through the respective Si02 layer (this is known as Fowler - Nordheim conduction).

Three key factors control the efficiency of selective writing in a memory array utilizing the memory cell of 25 Figure 1 A. First there is the strength of the capacitive coupling Ccl between the floating gate and control gate, indicated diagrammatically in Figure 1 b. This capacitive coupling depends on the geometric overlap between the two gates and on the thickness and refractive index of the insulating layer 126C between the two. Unforunately, if this layer is made too thin, there is a possibility of shorts between the two gates, particularly during the high voltage condition existing during a write operation. The second and third factors 30 are the channel length L between the source and drain, and the channel doping concentration P. The shorter L and the higher P, the more efficient is the hot electron injection mechanism. However, a short channel length L can cause punch-through between source 120S and drain 120D when the drain is in the high voltage condition, and a high doping P can cause junction avalanche breakdown in the high voltage condition. Both phenomena must be avoided absolutely in a memory array.

The prior art has also taught implicitly or explicitly that the parasitic capacitances from control gate 114 C and floating gate 114F to source 120S and drain 120D adversely affect the operation of cell 110, and must be minimized by critical self alignment techniques. Especially to be minimized is the side capacitance Cdl between floating gate 114F and drain 120D which allows floating gate 114F to follow the potential on drain 120D.

During a write operation, because of the high value of the drain voltage VD, every unaddressed cell on a selected column of the memory array exhibits low level conduction (about 10 microamps) due to side capacitance Cdl coupling of the drain to the floating gates of non- accessed cells thereby turning on slightly certain of the non-accessed cells. A 64K EPROM (256 rows by 256 columns) has in the worst case a parasitic current due to this effect of several milliamps, which is greater than the 1 milliamp write current of the addressed cell. Currents of this magnitude may load the data line voltage and cause errors due to reduced write efficiency. This condition is known as "drain-turn-on".

According to a first aspect of the present invention, there is provided a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semi-conductor material substrate, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of the device, wherein each memory cell comprises a pair of source-drain regions separated by a channel region and the field of the device includes channel stop regions formed over only a portion of the field to reduce the capacitance between the memory cells and the field, and preferably the channel stop regions are formed directly adjacent only one of two sides of each of a selected number of source-drain regions, to reduce the junction capacitance between each channel stop region and its adjacent source-drain 55 regions.

According to a second aspect of the present invention, there is provided a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portions of the top surface in which memory cells and access circuitry are not formed forming a field of the device, the device comprising a plurality of source-drain regions formed in the 60 semi-conductor material substrate, each memory cell being formed by a pair-of source-drain regions separated by a channel region, a floating gate positioned above but insulated by gate insulation from a portion of the channel region and also positioned above but insulated from a portion of the drain region, and a control gate insulated from but extending over both the floating gate and the portion of the channel region not covered by the floating gate and wherein the semiconductor material substrate is doped with an impurity 65 2 GB 2073487 A:

2 of a given conductivity and the field of the device is doped with an impurity of the same conductivity such that a higher doping concentration is formed in the field of the device the higher doping concentration being formed in the parts of the field of the device bounded by adjacent control gates and adjacent source drain regions to provide protection against leakage currents.

According to a third aspect of the present invention there is provided a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface in which memory cells and access circuitry are not formed forming a field of the device, the device comprising: a plurality of source-drain regions formed in the semiconductor material substrate, each memory cell being formed by a pair of source-drain regions separated by a channel region, a floating gate positioned above but insulated by gate insulation from a portion of the channel region and positioned above but insulated from a portion of the drain region and a control gate insulated from but extending over both the floating gate and the portion of the channel region not covered by the floating gate, and wherein the semiconductor material substrate is doped with an impurity of a given conductivity and the field of the device is doped with an impurity of the same conductivity such that a higher doping concentration is formed in the field of the device, the higher doping 15 concentration being formed in those portions of the field of the device bounded by adjacent control gates and adjacent strips of conductive material from which are formed floating gates before each strip has been etched into individual floating gates, thereby to substantially reduce the junction capacitance of each source-drain region with the channel region and the field of the device compared to the junction capacitance when the higher doping concentration is formed throughout the field of the device, while at the same time 20 maintaining adequate protection against leakage paths.

The present invention provides a method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of the device, which field is formed with channel stop regions between adjacent ones of a plurality of strip-like source-drain regions, in which method each channel strip region is formed directly adjacent only one corresponding source-drain region to reduce the junction capacitance between each channel stop region and the two adjacent source-drain regions.

Further, the present invention provides a method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of atop surface of a semiconductor material substrate, 30 the remaining portion of the top surface not formed with memory cells and access circuitry forming afield of the device, which field is formed with channel strips between adjacent ones of a plurality of strip-like source-drain regions, in which method each channel stop region is formed directly adjacent two corresponding source-drain regions after the formation of a second plurality of conductor strips disposed substantially perpendicularly to the source-drain region strips to act as gates, to prevent field inversion when 35 high programming voltages are applied to the drain and gate of each memory cell and to enhance channel doping at the edge of the channel regions to increase programming efficiency.

Also, the present invention provides a method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of 40 the device, the method comprising: forming a masking oxide on a silicon substrate to a selected thickness; opening windows in the masking oxide through to the underlying substrate in the form of strips; placing a selected impurity in the substrate through said windows to form a plurality of source-drain regions; oxidizing the substrate exposed by the window to a selected thickness to form a step in the silicon for use in further processing; removing all oxide from the substrate exposing channel regions in between adjacent 45 source-drain regions; forming a gate insulation of a selected thickness overthe surface of the substrate; forming polycrystalline silicon overthe gate insulation to a selected thickness; doping said polycrystalline silicon with a selected impurity to a selected conductivity; forming said doped polycrystalline silicon into a first plurality of strips, each strip being parallel to and directly over part of a uniquely corresponding source-drain region and also overlying a portion of the semiconductor substrate adjacent to said source-drain region to form a gate of a memory cell incorporating the corresponding source-drain region; forming insulation of selected thickness overthe exposed surface of each strip of polycrystalline silicon; forming a second conductive layer to a selected thickness on said insulation; forming the second conductive layer into a second plurality of strips disposed substantially perpendicularto the previously formed first plurality of strips formed parallel to the source-drain regions; and implanting a selected impurity in that portion of the semiconductor substrate not covered by said first or second plurality of strips which forms the field of the device to form channel stop regions therein.

In another aspect the present invention also provides a method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of the device, the method comprising: forming a layer of masking silicon nitride on top of a thin layer of masking silicon dioxide on a silicon substrate; open windows in the silicon nitride and dioxide masking layers through to the underlying substrate in the form of long strips; placing a selected impurity in said substrate through said windows to form a plurality, of source-drain regions; oxidizing the strips in said substrate exposed by the window to a selected thickness to forma gate insulation for the t.

i 3 GB 2 073 487 A portion of a floating gate to be formed over said source-drain regions; removing said masking nitride and performing a short oxide etch to remove only said thin masking oxide while leaving unetched substantially most of said gate insulation grown over said source-drain regions exposing channel regions in between adjacent source-drain regions; forming a gate insulation of a selected thickness in the silicon channel regions exposed in the previous step; forming polycrystalline silicon over the gate insulation to a selected thickness; doping said polycrystalline silicon with a selected impurity to a selected conductivity; forming said doped polycrystalline silicon into a first plurality of strips, each strip being parallel to and directly over a substantial part of a uniquely corresponding source-drain region and also overlying a portion of the semiconductor substrate adjacent to said source-drain region to form a floating gate of a memory cell incorporating the corresponding source-drain region; forming insulation of selected thickness over the exposed surfaces of each strip of polycrystalline silicon; forming a second conductive layer to a selected - thickness on said insulation; forming the second conductive layer into a second plurality of strips disposed substantially perpendicularly to the previously formed first plurality of strips formed parallel to the sourte-drain regions; and implanting a selected impurity in that portion of the semiconductor substrate not 15, covered by said first or second plurality of strips which forms the field of the device to form channel stop regions therein.

Thus, the portion of the floating gate overlying the drain region is deliberately more strongly capacitively coupled to the drain region than are the floating gate structures of the prior art (which deliberately sought to minimize this coupling capacitance) to allow the floating gate potential to follow more closely the drain potential than previously attained with prior art coupling capacitances. This results in an increase in the vertical field strength, accelerating the hot electrons from the pinch- off region of the channel onto the floating gate during programming of the cell. Concurrently and surprisingly, an additional advantage is that despite the stronger capacitive coupling between the drain and the floating gate during a read operation, the channel between the source and the drain in non-accessed cells is not made conducting by the drain turn-on phenomenon because only a portion of the channel region is covered by the floating gate, while the - remaining portion of the channel region, covered by the control gate of the device, is held non-conductive by the low potential on this control gate.

In one embodiment of a semiconductor memory device according to this invention a region of thin oxide is formed underneath a portion of the floating gate over the channel region of each memory cell. This region of thin oxide allows a floating gate to be reprogrammed using electron tunneling with a relatively high voltage 30 pulse supplied to the floating gate through either its drain capacitance or control gate capacitance. The "tunneling" dielectric may be, for example silicon dioxide or silicon nitride and the cell is easily reprogrammed by dropping the potential on the control gate to a low level (particularly -20V) while holding the source, drain and substrate at zero volts. The electrons on the floating gate (for an N channel, enhancement mode device) are swept off the floating gate into the substrate of the device thereby deprogramming the particular cell.

During the deprogramming operation of a particular cell, all of the other cells possessing the same control gate may be prevented from being discharged by applying a positive voltage of about +20V to the corresponding drains. This prevents a strong field f rom being created across the floating gate. to the substrate and thus prevents the charge on these other floating gates from being altered. Alternatively, all floating gates associated with a given control gate structure can be erased simultaneously by maintaining the voltage on each of the drains atthe voltage of the substrate.

In order that the invention may be readily understood, embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1A is a sectional diagrammatic side view of a known memory cell; Figure 1B shows schematically the drive capacitances of the memory cell of Figure 1A; Figure 2A is a sectional diagrammatic side view of a memory cell of a semiconductor memory device embodying this invention, showing capacitance Cd2 between the floating gate and the drain with or without provision for tunnel erase; Figure 2B shows schematically the drive capacitances of the memory cell of Figure 2A (capacitance Ct2 is 50 present only when provision for tunnel erase is made):

Figure 3A is a sectional view of three memory cells in an EPROM device embodying the invention, each memory cell having a single diffusion; Figure 3B is a plan view of a 3 X 3 array of the memory cells shown in Figure 3A; Figure 4 illustrates graphically the relationship between the voltage on the floating gate and the, ratio 55 Cd/Cc, both for a memory cell of a semiconductor memory device embodying the invention and for prior art devices, Cd being the drain-to-floating gate capacitance and Cc the control gate to floating gate capacitance; and Figures 5A to 5G illustrate the steps of one embodiment of a method according to the invention for forming a high density EPROM device in accordance with the invention.

Figures 6A and 6B illustrate the first few steps of a second embodiment of a method according to the invention for forming a semiconductor memory device; Figure 6C shows in cross-section an electrically erasable read only memory device (EEPROM) embodying the invention formed by the method partly illustrated in Figures 6A and 613; and Figure 7 is a sectional diagramatic side view of a memory cell of a semiconductor device embodying the, 65 4 GB 2 073 487 A 4 invention.

Referring now to the drawings, Figure 2 illustrates a memory cell 210 for a non-volatile EPROM device, The cell 210 has a floating gate 214Foverlapping most of drain 220D to forma drain-to-floating gate capacitance Cd2, and overlapping a channel portion 218F adjacent to drain 220D to form capacitance Cf2. Control gate 214C extends over floating gate 214F to form capacitance Cc2 as in the prior art memory cell 110 shown in Figure 1. However, in addition, control gate 214C has a portion 214C'which extends down towards a channel portion 218C' adjacent to source 220S thereby forming capacitance Cb2 between control gate portion 214C' and channel portion 218C'. During a write operation, a drain write voltage Vwd establishes an accelerating field from source 220S to drain 220D and also redistributes residual electrons on floating gate 214F through series coupling capacitances Cd2 and Cf2 (see Figure 213). A negative charge accumulates on that portion of 10 floating gate 214F comprising part of capacitance Cd2 over drain 220D, and a positive charge accumulates on that portion of floating gate 214F comprising part of capacitance Cf2 over channel portion 218F thereby establishing an inversion region in channel portion 218F. Essentially the drain diffusion 220D is used as a second control gate to create not only a strong lateral electric field between source 220S and drain 220D in response to the drain write voltage Vwd (applied to the drain in conjunction with a control gate write voltage 15 Vwc on the control gate) but also a strong transverse field across oxide 226F for enhanced hot electron injection from the channel portion 218F to floating gate 214F.

The control gate write voltage Vwc applied to control gate 214C inverts channel portion 218C'through capacitance Cb2, completing a conductive path across channel 218 of the addressed cell. Control gate write voltage VwG also assists in the establishment of the inversion in channel portion 2,18F beneath floating gate 20 214F across dielectrics 226C and 226F by means of capacitance Cc2. Electrons from source 220S are - accelerated laterally along the two inversion regions of channel 218 by drain write voltage Vwd. A tiny fraction of these hot electrons are injected across dielectric 226F into floating gate 214F by the transverse electric field 224F across capacitance Cf2 created by the control gate write voltage Vwc and by the drain write voltage Vwd coupled to the floating gate by capacitance Cd2. It is important to note that hot electron injection occurs essentially only in the pinch-off region of channel 218F, that is, at most 1 micrometre away from the drain diffusion. This fact is used to greatadvantage in the high density array shown in Figures 3A and 3B to prevent accidental write-disturb, as will be described below.

- During a read operation, cells that have been programmed with charge Qj on floating gate 214F have a high threshold and remain non-conductive. However, unprogrammed cells without charge Qj readily conduct in response to lower access control gate read voltage Vrc and drain read voltage Vrd. The increased drive capacitance in cell 210 over prior art cell 110, caused by the deliberate increase in the value of capacitance Cd2 relative to the prior art cell 110, results in higher density of charge Qj on the floating gate

214F and more channel control without a corresponding increase in cell area or access voltages.

The series control of channel 218 through two independent capacitances Cf2 and Cb2 prevents low level 35 drain turn-on current across partially addressed cells (i.e. across cells accessed only by a drain write voltage Vwd without a corresponding control gate write voltage Vwc). N channel inversion must be established in both channel portion 218C' by the read voltage VrG applied to control gate 214C during read, and in channel portion 218F by the drain voltage Vrd applied to drain 220D during read and the read voltage Vrc in order to support channel current.

Surface punch-through across channel 218 is eliminated in non-accessed cells (i.e. in cells to which neither control gate read voltage Vrc nor drain read voltage Vrd is applied) and partially accessed cells (i.e. in cells to which only drain read voltage Vrd is applied) because of the absence of at least one of tle required series inversions. The length of channel 218 may therefore be shortened beyond the punch-through limit of prior art cell 110. The vision of channel 218 into two independent portions 218C' and 218F for access control, raises the design option of different dopant levels in each portion. The dopant level and hence channel inversion threshold voltage of either or both channel portions may be lowered (or raised) to suit each design application. For example, a lowered threshold in portion 218C' provides increased cell drive during a read operation without adversely affecting the write efficiency, which is dependent on and proportional to the doping concentrations in channel portion 218F.

The density of an EPROM device memory array may be increased by employing a single diffusion 320 in each memory cell as shown in Figures 3A and 313, the diffusion 320 functioning as either the source or the drain, depending on the respective voltage relationships between diffusion 320 and the adjacent diffusions 320L and 320R. Each diffusion 320 (such as diffusion 320L, 320 and 320R) in the array-340 forms a bit line shared by all floating gates 314F overlapping it. The control gates 314A, 314B, 314C, et. al. run perpendicular 55 to the diffusions 320, and control the channel conduction through channel portions 318C'and 318F between any two diffusions 320. Each diffusion 320 has channel portions 318C'and 318F on each side. The space 319 between adjacent rows in Figure 3B (such as between rows 314A and 314C) is an isolation region, formed by either a self aligned channel stop ion implantation followed by prolonged oxidation, or by a conventional isoplanar process isolation. The first isolation technique (i.e., channel stop ion implantation) is preferred 60 because it gives higher array density and a more planar topography, and heavy channel stop boron ion implantation can be used to advantage during a write operation because it substantially raises the channel doping concentration at the edges of the channel as a result of lateral diffusion of the implanted impurities from the isolation region into the channel region during subsequent high temperature processing. The channel edges therefore become the region where programming will preferentially occur. With a heavy 65 t a GB 2 073 487 A, 5 channel stop isolation implantation, the channel doping in the rest of the channel 3118F,218W can be kept just low enough to provide a slightly positive device threshold voltage for an N channel enhancement mode device.

Each diffusion 320 is contacted at a via 337 at every 8 or 16 rows 314 with a metal line 335 running parallel to the diffusion. Note that prior art cell 110 requires a via opening for every two cells, and any non-opened via results in catastrophic array failure. By contrast each via in the array 340 is shared by 8 or 16 cells, and a non-opened via is non-catastrophic since it simply raises somewhat the diffusion bit line resistance, which can be taken into account in the circuit design. The result is an increase in cell density and yield over the prior a rt.

The process employed to form an array of memory cells of a semiconductor memory device embodying the invention is a two polysilicon level process requiring an underlying drain diffusion beneath the floating -gate 314F which must be provided early in the process. This requires an additional masking step but the added diffusion can be employed as another level of inter-connect for use in dense peripheral circuitry (standard self-aligned processing does not allow diffusions running under polysilicon). The full process for a Aense array embodiment will be described below.

The array 340 requires special write and read voltage conditions to ensure that no accidental programming or erroneous reading takes place. In Figure 3B, if cell A2 is to be programmed into its high threshold voltage state then column 335 (and thus underlying drain region 320 since column 335 is connected to drain 320 by via 337) is brought to + 1 5V (i.e. Vwd = 15V) with all other columns at OV. Control gate row 314A is brought to +20V (i.e. Vwc = + 20V) with ail other rows at OV. Cell A2 now possesses the correct field conditions for hot 20 electron injection (i.e. a horizontal field from source 320L to drain 320 and a vertical field from the N channel between source 320L and drain 320 to floating gate 314F beneath gate 314) and will be programmed by the injection of charge onto floating gate 314F. Cell B2 has the correct drain write voltage Vwd but no channel current since the voltage on control gate 314B is low. Cell A1 has an inverted channel but no accelerating horizontal field since column 335L and thus the voltage Vwd on drain 320L is low. Cell A3 is the only cell otherthan A2 with both an accelerating horizontal field between source and drain and an inverted channel with a strong field for hot electron injection. However, because of a low voltage (OV) on drain 320R and the non-symmetrical nature of the three-cell structure 310, floating gate of cell A3 does not overlap the channel pinch-off region, which under thespecified voltage conditions occurs within approximately 1 micrometre of diffusion 320. Therefore, any hot electrons injected from the channel will be collected harmlessly on control gate 314A rather than on the floating gate of cell A3. Note also that the non-symmetrical nature of the three-cell structure 310 results in an electric field across capacitance W3 which is much smaller for cell A3 than for cell A2 because the floating gate of cell A3 is coupled (through capacitance Cd3) to diffusion 320R which is at OV, while the floating gate of cell A2 is capacitively coupled to diffusion 320, which is at +1 5V.

From the above description, it is seen that this invention has turned to advantage the non-symmetrical nature of the three-cell structure 310 to make possible the very dense implementatidn of array 340. In manufacturing the array, caution must be exercised to ensure that the floating gate 314f does not approach by closer than 0.5-1.0 micrometres the diffusion 320L to its left, i.e. the channel beneath control gate portion 314C' must have sufficient length, and a doping concentration properly adjusted to prevent accidental writing into a cell during the write cycle at an adjacent cell.

It should be noted that if the cell is manufactured such that U3> Cc3 (through choice of dielectric film thicknesses and overlap areas) then the drain write voltage Vwd rather than the control gate write voltage Vwc is the dominant voltage during a write operation and therefore the control gate write voltage Vwc can be brought to +5v, which is the same as the control gate read voltage Wc. This has the circuit design advantage that the entire row decoding circuitry can now be designed to operate in the low voltage range both for read 45 and write operations.

Reading cell A2 can be performed in several ways. One way is to raise all columns 335 to +5v, with the exception of column 3351-, which is at OV. Row line 314A is also brought up to +5V with all other rows at OV.

If cell A2 is in the low threshold state then it discharges column 335 towards OV through the series channel between 335 (drain) and 335L (source). The voltage drop on column 335 is sensed by a charge sense amplifier at the bottom of the column, which is latched after the voltage on columns 335 (or equivalently, the voltage on drain 320) has dropped a few hundred millivolts below +5v. Cell A3 does not conduct because its source 320 is never allowed to drop by a full transistor threshold voltage below its control gate voltage 314A.

If the cell A2 is in its high threshold state it will not conduct under the conditions set forth in the above paragraph, leaving column 335 (or diffusion 320) at +5V. The sense amplifier can compare the voltage drop 55 on column 335 with that through a reference cell similar to cell A2. Because of the added degree of freedom of the memory cells 210,310 (Figures 2 and 3, respectively) the circuit designer can give the reference cell more or less floating gate-to-drain overlap capacitance Cd2 than the cells in the array, thereby effectively setting the trip-point of the sense amplifier at an intermediate level between---0- and "V states without the need for complicated means for generating on the chip an intermediate voltage level, which voltage level may in any case be more sensitive to process variations. It should be pointed out, however, that the method described above for write and read is only one of several possible alternatives.

Erase of all cells in array 340 is performed, as in all prior art floating gate devices, by ultraviolet illumination. alternatively, for memory cells with tunnel erase provision, electrical erase may be employed at a cost of some additional processing.

1 6 GB 2 073 487 A.

6 Any floating gate memory cell can have a voltage derived from the voltages and capacitances physically coupled to it. For the prior art memory cell 110 this voltage is given by (see Figure 113):

VFG110 QFG+NCCC1 + VSCS1 + VdUl) 5 (Ccl + Cf 1 + Cs'] + CM) In equation (1) QFG is the excess charge (negative for electrons) on the floating gate. For a typical memory cell 110 we have the following values:

Cel = 10 Co, Cf l = 5Co, Cs'] = 0.5Co, Cd 'I = 0.5Co, where Co is some unit capacitance whose magnitude depends on the thickness and dielectric constantof the dielectric isolation around 114F. When GM = 0 (non-programmed device), we have from (l):

is Read (VD = Vc = 5Vr % 110 = 3.3V (1 a) vs = V13 = OV) Write (VD = VC = 15V % 110 = 9.8V (1 b) VS = V13 = OV) 20 By comparison, the cel 1210 of the present invention has its floating gate voltage given by (see Figure 213):

VFG210 = QFG + (VcCe2 + VbM + VdCd2) (2) 25 (Cc2 + W2 + Cd2) For the typical 210 device, using the same unit Co we have the following values:

Cc2 = 12 Co, W2 = 2.5 Co, Cd2 = 10 Co.

Cc2 is increased relative to Cel because of the additional f loating gate area over the drain. W2 is smaller than Cf l because only half the channel 218F is coupled to 214F. Cd2 is increased because of the deliberate 35 drain overlap.

The dielectric between 214F and the drain is thermally grown in single crystal silicon and can therefore be made thinner, and is therefore of higher capacitance per unit than thatfor the dielectric constituting capacitance Cc2, which is grown on the polycrystalline silicon floating gate material. Capacitance Cs2 is zero since the floating gate must not overlap the source diffusion. These values give from equation (2) for the case QFG 0: 40 Read (VD VC 5V VFG210 = 4.5V (2a) VS VB OV) i Write (VD = VC = 15V VFG210 = 13.5V (2b) 45 VS = Vs OV) y For maximum drive during a read operation, the floating gate voltage WG should be as high as possible to strongly invert the channel 118 or 218F. Forthe same transistor channel width and length, equations (1 a), (2a) show that cell 210 has considerably more drive than cell 110 (the drive is proportional to %G Vt)2 50 where Vt is the floating gate threshold voltage, -+1.OV).

Similarly for maximum injection field during programming the voltage WG should be as high as possible, which from equations (1b), (2b) is much more so for 210 than 110. In addition, since, when VC VD 15V; Vs = Vs = OV in each case, VFG210 is higher by3.7V than WG1 10 the net excess charge OFG stored at the end of the programming pulse is higher by the equivalent 3.7V in cell 210 over that for cell 110. In other words, the - voltage window between "0" and '1- states is increased by up to 3.7V, which permits improved non-voiatility. It should be clear from the above discussion that the improved read and write operation efficiency of cells 210,310 can be traded in fora smaller (higher density) cell, or lower operating voltages.

Equation (2) also clarifies the statement made earlier about the design flexibility in changing the floating gate voltage WG on the reference cell of the sense amplifier by simply increasing or decreasing the capacitance component Cd2.

Figure 4 illustrates the different operating ranges of the prior art memory cells and memory cells of a semiconductor memory device embodying the present invention. The magnitude of the floating gate voltage WG controls injection efficiency during programming and channel transductance during a reading operation and Figure 4 shows that fora ratio of Cd over Cc greater than the prior art limit of about 0.2, the structure of a 65

7: GB 2 073 487 A.7 memory cell of a semiconductor memory device embodying the invention increases the voltage on the floating gate by several volts during the programming mode of operation of the cell and by about 1 volt during the read operation of the cell. The prior art cell operated with a ratio of Cd/Cc of less than 0.2. Thus a relationship of the voltage on the floating gate to the drain voltage of 5 volts, for example, during the read operation is shown by the three dots on the left-most portion of the bottom curve of Figure 4. With a memory cell of a semiconductor memory device embodying the invention, the floating gate voltage varies between a little under 4 volts to a little under 5 volts for a drain voltage of 5 volts during a read operation, whereas with the prior art cell the floating gate voltage varied between 3 and about 3.75 volts.

Similarly, during the programming operation, a prior art memory cell yielded a voltage of from about 9 to

11 volts on the floating gate when the capacitance ratio Cd/Cc was less than 0.2. However, with a memory 10 cell of a semiconductor memory device embodying the invention, the floating gate shows a voltage of about 11.5 to 14 volts for a drain voltage of 15 volts during the programming operation. These higher voltages illustrate the difference between the prior art memory cells and memory cells of a semiconductor memory device embodying the invention and in particular during the programimming operation illustrate the increase in injection efficiency during programming and channel transconductance during reading of the 15 cell.

For a wide range of applications it is inconvenientto use ultraviolet radiation to erase the charge QFG on the floating gate. Cells 210,310 can be modified so that erase can be performed electrically. This is done by the addition of a small region 215F, 315F where the dielectric between floating gate 214F and substrate 218 is sufficiently thin to allow electronic conduction by tunneling under high field conditions. The tunneling current is exponentially dependent on the electric field aplied across the region 315F. For example, at 10V applied, 315F may conduct a current density of 1 milliamp per CM2 whereas at 8V applied it will only conduct a current of 1 nanoamp per CM2. The very sharp field dependence is used to advantage in the present embodiment to prevent accidental program or erase in unselected cells.

Writing can be as in 210,310 by hot electron injection together with some tunneling. As in 210,310 no hot 25 electron injection occurs in partially selected cells, but in addition no tunneling is allowed in these cells because the floating gate voltage VFG is below the threshold field for efficient tunneling when only one but not both of voltages VD and Vc are atthe high programming voltage. For example let us assume that the thickness and dielectric constant of region 215F are such that the voltage VFG must exceed 9V (with the substrate bias voltage V13 = OV) to achieve tunneling. From equation (2), (assuming capacitance Ct2 = 2Co) a 30 programmed cell has VFG = 13.5V (as before) and will allow tunneling whereas a partially accessed cell has VFG = 6.8V (VC = 15V, VD = OV) or VFG = 5.7V (Vc = OV, VD = 15V), both of which voltages are too low for tunneling. Again the drain coupling capacitance Cd2 is used here to advantage to enhance the field at the selected cell, and inhibit it on all non-selected cells in the array.

Erase is performed by applying a pulse of typically -20V to rows 314 and grounding all column diffusions 35 320, with substrate 311 also grounded. From equation (2), the cells along the accessed row then have:

W ChG +(-20 x 12 Co) C4G volts (3) CTotal ET-ota 1 +10 40 When QFG = 0 (non-prog rammed) the erase field isweak, buterase bytunneling (electron ejection)will still occur, and is allowed to take the threshold of channel portion 318F into depletion (this would not be allowed were it not for the series channel portion 318C'which remains in enhancement). When QFG is negative (programmed device) the field due to excess electrons on the floating gate greatly enhances the 45 tunnel erase until all such excess electrons have been removed, for a complete erase. This takes typically 1 -10 microseconds.

A semiconductor memory device embodying the invention is manufactured in accordance with the following method.

Referring to Figure 5A. one particular method begins with a wafer of Ptype silicon substrate 530 of approximately ten ohm-centimetres resistivity and with [1001 crystallographic orientation. However, it is possible to start with an N- type silicon substrate 532 (Figure 7) of approximately 20 ohm-centimetres resistivity and with [100] crystallographic orientation and to form therein regions 531 of isolated P type wells such as are common in CIVIOS manufacturing process. Such Ptype wells 531 can be formed in the N substrate through doping the required silicon regions with boron and then driving the dopant in a diffusion 55 step. Although this is an additional step to the process flow it allows added flexibility to the circuit designer because the control circuitry can be fabricated in a P type well which may be electrically isolated from the large P type well in which the memory array is fabricated. It is then possible for example to generate negative voltages on the chip from a positive supply voltage, or to apply high programming voltages to the P type well of the array but not to the periphery devices fabricated in separate P type wells. Initially, a masking oxide 60 is grown using standard oxidation techniques to a thickness of about 2000 angstroms (200 nm). Windows are then opened in this oxide through to the underlying substrate in the form of long strips.

A selected impurity or dopant such as arsenic or phosphorous is then placed into the substrate through these openings to form a plurality of source-drain regions 520DL, 520D and 520DR, for the to-be-formed cells using conventional doping techniques such as diffusion or ion implantation. Typically, the dopant 8 GB 2 073 487 A, 8 concentration of these regions is such that these regions are of N+ conductivity type (i.e., the dopant concentration is in excess of 101' atoms per cubic centimetre). Each region can function as a source or a drain depending on its biasing.

Next, as shown in Figure 5B, the wafer is oxidized to consume approximately 1000 angstroms (100 nm) of silicon in each source-drain region 520 so as to drive in the dopant and to form a step in the silicon forfuture 5 mask alignment. The silicon under the masking oxide oxidizes at a much slower rate than the silicon in a source-drain region. All the oxide is then stripped from the wafter.

Next a gate oxide 526F of from 50 to 1000 angstroms (5 to 100 nm) thickness, depending upon circuit requirements, is grown over the surface of the water. It is well known in the industry that thermal oxidation rates over a heavily doped N + type regions such as source-drain region 520D can be several times higher 10 than the oxidation rate over a lightly P type doped region such as channel region 518. By controlling the N+ doping concentration in the range of 5X 1018 atoms CM-3 to 5X1019 atoms CM-3 it is possible to accurately control the rates of oxide growth both over the P type channel region 518 and over the N+ type source-drain region 520D. For example, if an EPROM device which is electrically programmable but erasable by ultraviolet radiation is required, the gate oxide 526F overthe channel region 518 will be grown to a thickness of approximately 200 to 1000 angstroms (20 to 100 nm) and the oxide over the source-drain region 520 will be only slightly thicker. If an electrically programmable and electrically erasable (EEPROM) device is required, the gate oxide 526F overthe channel is not grown so thick and is in the range of 50 to 200 angstroms (5 to 20 nm) thick to allow tunneling. The thickness of the oxide overthe source- drain region 520 can be made substantially thicker if is is desired that no tunneling should occur over the source-drain region. Alternatively, the oxide over channel region 518 can be grown as for the EPROM device and a region of tunnel oxide can then be defined by an extra masking step as described by E. Harari in U.S. patent No. 4,115,914 byfirst etching the gate oxide 526F in the region shown in Figure 5b as 515F and then growing a thin tunnel oxide onto the exposed silicon surface to a thickness in the range of 50 to 200 angstroms (5 to 20 nm).

Ina second embodiment the masking layer for forming the source-drain regions consists of a thin layer 550 of silicon dioxide of greater than 50 angstroms (5nm) thickness capped with a layer (560) of silicon nitride to a thickness of about 1000 angstrom 0 00 nm) as illustrated in Figure 6A. Windows are then opened in the nitride and oxide layers through to the underlying substrate in the form of long strips and the N+ regions are formed by doping as in the first embodiment. These exposed source-drain regions are then 30 oxidized in the thickness range between 200 angstroms (20 nm) and 6000 angstroms (600 nm). Contrary to the previous embodiment, this oxide is not stripped back and forms the gate insulation 568 over the drain region 520D. Next the masking silicon nitride 560 is etched back and the thin silicon oxide layer 550 is dip-etched back, exposing the silicon 518 in the channel region but not the drain region (the oxide 568 over the drain is grown to a thickness suff icient to compensate for partial thinning during this dip etch). A thin 35 dielectric layer 567F (Figure 6B) is then formed in the channel region 518. This can be a thermal oxide grown in the thickness of 50 angstroms (5nm) to 1000 angstroms (100 nm), or a thermal nitride of thickness less than 200. angstroms (20 nm). The remainder of the method in this embodiment is the same as for the first embodiment. The key difference between the two embodiments then is that in the first the gate insulation is formed in the same step for both the insulation over the drain and that over the channel, whereas in the second embodiment the two regions have their gate insulation formed in two independent steps, providing an extra degree of freedom in selection of their respective thicknesses or constituents, thereby affecting their capacitances per unit area. As has been shown in equation (2) the relative values of the capacitances Cd2 and Cf2 are of crucial importance to the efficiency of the memory cell for all programming modes. Therefore the ability to independently control dielectrics 568 and 567F which influence capacitances Cd2 and Cf2 respectively is a distinct advantage. In addition, the formation of a very thin insulator 567F with formation of a thicker insulator 568 results in an electrically programmable and electrically erasable (EEPROM) device, since the thin insulator 567F can be used to allow programming and erasing by electronic tunneling whereas the thicker oxide 568 serves to enhance the capacitive coupling Cd2 of the floating gate 514F to the drain without permitting tunneling through to the drain diffusion.

Returning now to the first embodiment, the gate oxidation step is followed by the implantation of a P type impurity (preferably boron) through the gate oxide 526Fto dope the channel region such as region 518L or 518 between each directly adjacent pair of source-drain regions 520 to a surface concentration of 1012 to 1013 impurity atoms per square centimetre. This implantation occurs at about 50 KeV. It is also possible to perform the implantation just prior to the gate oxidation step. The actual doping level in the channel regions 55 depends upon the desired device threshold and the desired programming voltage.

Following the boron implantation, polycrystalline silicon 514 is deposited over the surface of the wafer to a thickness of about 1000to 3000 angstroms (100to300 nm) using conventional polysilicon deposition techniques (see Figure 513).

The polycrystalline silicon is then converted to N+ conductivity type by conventional doping techniques. 60 Typically phosphorous is used to dope the polysilicon although other N type dopants can also be used if desired.

The polycrystalline silicon 514 is next masked and etched using conventional techniques to form a plurality of strips, each strip (such as 514F) being parallel to and directly over part of a uniquely corresponding N+ type source-drain region (such as region 520D). Each strip not only overlies a 9 GB 2073487 A 9 corresponding source-drain region but also overlies a portion of the channel region 518 to the left of this diffusion for example strip 514F overlies source-drain region 520D and channel region 518F (the word "left" refers to the left side of the diffused N+ type source-drain region 520 when this region is viewed in cross-section as shown, for example, in Figure 3A or Figure 5Q. The masking step to define strips such as 514F is a critical alignment step. It is the one step in the method requiring extremely good alignment between the polysilicon pattern 514F and the source-drain diffusion pattern 520. If the strip 514F is too drastically misaligned to the left of diffusion 520, the floating gate of the resulting memory cell will be more tightly coupled to the channel and less tightly coupled to the drain, and vice versa for misalignment in the opposite direction. The widths of diffusions 520 and channel regions 518 must be chosen that the device (in all the EPROM and EEPROM embodiments) still function in all programming and reading modes in extreme 10 cases of misalignment between the strips 14F and diffusions 500. This requirement for tight alignment is - unique to the method and device embodying the invention. It is a relatively simple requirementto meet with the latest generation of lithography printing equipment (10:1 reduction printers). In a typical high density arraythe degree of misalignment at this masking step should not exceed approximately 1.0 micrometres.

15, Figure 5C shows the structure as it now appears with the P- type silicon substrate 530 containing formed 15 therein the N+ type source-drain regions as exemplified by region 520D, gate oxide 526F formed over the surface of the device, floating gates of polycrystalline silicon as exemplified by gate 514F formed over source-drain region 520 such that a portion of the floating gate 514F extends over the channel region 518L between source-drain region 520D and source-drain region 520DL and P type channel regions 518L and 518 formed on the left and right sides of source-drain region 520.

The polycrystalline silicon strips 514F, 514FL and 514FR, for example, extend along the surface of the device and will be subjected to a second masking and etching operation to delineate the lateral dimensions of each floating gate 514. (The three strips 514FL, 514F and 514FR are exemplary only; it being understood that only a small portion of the total memory array is being shown for illustrative purposes, and that structure similarto that shown extends on both or all sides of that structure shown in, for example, Figures 25 5A to 5G, and Figures 3A and 3B). However, first the structure is oxidized in a well known manner to provide an oxide layer 526C of a selected thickness, typically approximately 1000 angstroms (100 nm) over the exposed surfaces of each strip 514F of polycrystalline silicon.

Following the formation of oxide layer dielectric 526C, a second polycrystalline silicon layer 514C is deposited to a thickness of approximately 2000-5000 angstroms (200 - 600 nm). Layer 514C will, following a masking and etching step, comprise the gate electrode for a row of memory cells. A cross-section through the resulting structure is shown in Figure 5D and a plan view in Figure 5E. At this time, the second polycrystalline silicon layer 514C covers the top surface of the device like a sheet. Underlying the layerare; strips of polycrystalline silicon 514FL, 514F and 514FR (Figure 5E) and beneath at least a portion of each of these strips is a corresponding source-drain region 520DL, 520D and 520DR, respectively.

Prior to the growth of oxide 526C, the device is submitted to an oxide etch to partially etch back to 200 angstroms (20 nm) the gate oxide 526F in the exposed regions between polycrystalline silicon strips stri-ps 514FL, 514F and 514FR. The second oxide layer 526C is then grown on the device. Oxide 526C comprises the interelectrode isolation dielectric between the floating gates 514FL, 514F and 514FR (Figure 5C, 5D) and the to-be-formed second polycrystalline silicon layer 514C from which the control gate electrodes will be 40 formed.

The oxidation process used to form oxide layer 526C can also be used to substantially reduce the boron concentration in the channel region not covered by the floating gates 514FL, 514F and 514FR by taking advantage of boron redistribution into the grown oxide. This beneficially reduces the threshold voltage of that part of the channel not underlying the floating gate regions 514FL, 514F and 514FR and thereby 45 increases the transconductance of this part of the channel.

The formation of oxide layer 526C also serves the purpose for the EEPROM embodiments of substantially increasing the thickness of the tunnel oxide 567F (Figure 6C) in the area 569i which is exposed when f loating gate 514F has been defined. Effectively then for the memory cell of the EEPROM embodiment shown in cross-section in Figure 6C, the area of thin tunnel oxide is defined by virtue of being surrounded by thicker 50 oxide on all four sides: oxide 568 over the drain, oxide 569 overthe remainder of the channel, and isolation oxide 319 (Figure 313) on both sides of the floating gate 514F.

Alternatively, the interelectrode isolation 526C can be formed by deposition of silicon nitride or alternatively by a composite structure such as is formed by a short oxidation followed by the deposition of silicon nitride. This sandwich structure is of a type well known in the semiconductor arts.

Following the formation of the dielectric 526C, a second conductive layer 514C is deposited. This layer can be polycrystalline silicon or some form of a low resistivity silicide or refractory metal which can withstand subsequent oxidation. Preferably this layer comprises polycrystalline silicon.

Following the formation of the second polycrystalline silicon layer 514C, the device is masked and etched to form strips of polycrystalline layer 514C perpendicular to the previously formed polycrystalline strips 514FLr 514F and 514FR. The etching process is continued through the dielectric 526C and polycrystalline silicon strips 514FL, 514F and 514FR so as to expose the underlying gate oxide 526F. The result is a structure shown in plan in Figure 5G but lacking the metal leads 535.

The previously described boron field implant between the source-drain regions 520DL, 520D and 520DR ! 65 can, if desired, be performed at this step in the process. When this is done, the field implant occurs in egions: 65

GB 2 073 487 A - 539 and 519 shown in plan view in Figure 5E and as further shown in plan view in Figure 5G. In this step, the boron is implanted to a concentration of about 1 to 5 X 1013 atoms per square centimetre. The boron implantation is automatically self aligned to the complement area of the first and second polycrystalline silicon layers 514F, 514C shown in Figures 5D, 5E and 5G and represented by region 539 and 519 in Figures 5E and 5G. The N+ diffusions 520D automatically over-compensate forthe boron in those areas in which regions 520D are exposed tothe ion implantation. The P type boron prevents field inversion when high programming voltages are applied to the drain and gate electrodes 520D and 514C, respectively, and also enhances the channel doping at the edges 529 (Figure 5E) of the channel regions of each floating gate device thereby in turn increasing the programming efficiency. This occurs because hot electron injection is more effective in a more highly doped region of the channel than in the more lightly doped regions of the channel. 10 At the same time, however, because only the edges 529 (Figure 5E) of each channel between source- drain regions 520D and 520DR, for example, (Figure 5C) have a higher doping concentration, the transconductance of the channel regions 518C1 and 518F for example is not reduced.

In this configuration, the polycrystaline silicon from which floating gate regions 514F, 514FL and 514 FR are formed has been etched to form the individual floating gates prior to the ion implantation in the field 15 regions between the floating gates.

In an alternative method, the boron can be implanted into that portion of the feld of the structure left exposed and bounded by conductive strips 514C and 514FL, 514F and 514FR as shown in Figure 5E. In this embodiment,the ion implantation effectively is automatically self- aligned to the complement area of the first and second polycrystaline silicon layers 514F and 514C represented by region 539 of Figure 5E. This reduces 20 by approximately one-half the junction capacitance of the diffused region 520D, for example, with the channel region and the field since only the right-hand side of each diffusion 520 (Figures 5C, 5D, 5E) is heavily P type doped due to field ion implantation, yet adequate protection is obtained against leakage paths. Again, in this embodiment, the boron is implanted to a concentration of about 1X1013 to 5x1 013 atoms per square centimetre.

An isolation thermal oxidation step is next performed to grow an isolation thermal oxide layer of about 1000-5000 angstroms (100 - 500 nm) thickness overthe top surface and field regions of the device. This oxidation also oxidizes the side regions of the first and second polycrystalline silicon layers (514FL, 514F, 514FR and 514C) exposed by the etching operation which forms the second polycrystalline silicon layer 514C into control gate strips and the first polycrystalline silicon layer into isolated floating gates.

Overthe thermal oxide (not shown in the drawings) is next deposited a phosphorous-doped pyroglass which is densified and reflowed by conventional thermal processing. The phosphorous doped glass provides additional protection to the device against unwanted contaminants which alter the electrical characteristics of the device.

The remainder of the method is standard.

In Figure 5F is shown the completed structure prior to the deposition of the scratch protection layer. Layer 534 is aphosphorous doped glass reflowed to smooth the surface topography and layer 535 comprises metal lines running parallel to the source-drain regions such as 520D and over the corresponding source-drain region such as 520DL. Contact is made between each metal line 535 and the source-drain region 520 underlying that line every eightto sixteen cells as shown in Figure 5G by via 537. A plan view of 40 the device is shown in Figure 5F. This feature greatly increases the array packing density by reducing the number of vias required to contact each source-drain region 520.

The above description -relates only to the formation of programmable memory cell arrays of the semiconductor memory device. Transistors used in the periphery of the device for decoding, buffering, and logical operations are processed in a conventional manner using either the first layer polycrystalline silicon 45 or the second layer polycrystalline silicon or metalization for the gate electrodes and additional masking steps, such as for the formation of transistors with sources and drains self aligned to the gates, may be required. The peripheral circuitry can, of course, be fabricated using conventional isoplanar MOS technology.

As described above, production of the electrically erasable device is substantially identical to that of the 50 device erasable by ultraviolet radiation except for an additional masking step between the implantation of the boron to form the source-drain regions 520 of the device and the deposition of the polycrystalline silicon from which the floating gate electrodes 514F et. al. are formed. The areas of the thin tunneling dielectric are formed in the oxide 526F beneath the floating gates 514FL, 514F and 514FR for example (Figure 513) overlying the channel region away from the source-drain regions 520DL, 520D and 520DR. The gate oxide 526F is etched away in these defined regions through to the underlying silicon and the structure is then reoxidized to form a gate oxide of approximately 50-150 angstroms (5 - 15 nm).

Alternatively, a thermal nitride is grown to a thickness of about 50-100 angstroms (5 - 10 nm) in the exposed region. The processing sequence described above beginning with the depositing of the first polycrystalline silicon layer then follows.

Any area of the tunnel oxide exposed when polycrystalline silicon layer 514 is defined and etched will be oxidized to a thickness at which no tunneling can occur during the subsequent oxidation of the wafer to form the interelectrode isolation oxide 526C.

The EPROM device disclosed above lends itself to a particularly dense and compact array. Preferably, in an EPROM device embodying the invention, the ratio of the drain-to-floating gate capacitance Cd to the floating 65 1 11 1 GB 2 073 487 A 11 gate-to-control gate capacitance Cc is greater than 0.3. In the prior art this ratio was preferably kept equal to or less than 0.1. Figure 4 illustrates, as described above, the effective increase in the floating gate potential as a result of the increase in the ratio of these two capacitances.

The structure of memory cells of a semiconductor memory device embodying the invention, contrary to the prior art structures, prevents drain turn-on during a read operation. Interestingly, this structure also avoids the requirements for a higher effective gate voltage due to a positive charge on the floating gate after deprogramming and therefore avoids operating on the right hand portions of the programming efficiency curve by not having an N type region (of a type disclosed in the prior art) underneath the floating gate. Additionally, the memory cell structure of a semiconductor memory device embodying the invention can use a control gate solely to turn on the channel directly under the control gate and not under the floating gate. Because the floating gate is controlled by the drain voltage, the drain can provide both the horizontal iand vertical accelerating and injection fields for use during the programming of the floating gate.

In an alternative of the method embodying this invention, a multi-layer sandwich insulation can be used between the first layer of polycrystalline silicon 514F and the second layer of polycrystalline silicon 514C.

Preferably, the first layer of polycrystalline silicon 514F is thermally oxidized to a thickness of approximately 15 to 500 angstroms (5 to 50 nm) and then a second layer of insulation comprising silicon nitride is deposited using well known techniques (such as continous vapour deposition) to a thickness of between about 100 to 800 angstroms (10 to 80 nm). The result is a structure which minimizes the effect of pinholes and which also seals the underlying chip to some extent from moisture penetration and other impurities.

Following the deposition of this layer of silicon nitride, a further thin layer of oxide can, in some cases, be 20 formed on the structure to serve as a layer to which polycrystalline silicon adheres or alternatively the top surface of the silicon nitride can be thermally oxidized to provide the thin oxide layer or left as it is.

Furthermore, the gate oxide described above can be replaced by insulation comprising a composite layer of, for example, silicon oxide and silicon nitride.

Figures 5F to 6C shows cross-sections of three different memory cells of a semiconductor embodying the 25 invention produced in accordance with the alternative embodiment. The key distinguishing feature between the three embodiments lies in the difference of thickness of gate insulation. The memory cell shown in Figure 5F forms a cell erasable by ultravoilet radiation only when the region 51 FF (shown in broken lines) is omitted, in which cell the dielectric 526F overthe channel 518 is of approximately the same or slightly less thickness than the dielectric 526D over the drain 520D. When the region 515F is incorporated the memory cell 30 is electrically erasable, the gate dielectric in the region 515F being thinner than in the rest of the channel or over the drain. Tunneling occurs in the region 515F during programming or erasing. The memory cell shown in Figure 6C can be ether a cell erasable by ultraviolet radiation or an electrically erasable cell depending on the thickness of the dielectric 567F over the channel region. Forthe memory cell to be erasable by ultravoilet radiation only, the thickness of the dielectric 567F is such that no electronic tunneling can occur, whereas if 35 the memory cell is to be electrically erasable dielectric 567F is suff iciently thin to permit tunneling during programming and erasing.

Thus, previously thought dis-advantages of an EPROM memory cell have been turned to advantage to provide a non-volatile EPROM device which is capable of a faster read cycle through the avoidance of drain turn-on of bit cells connected to the same drain line as the bit cell being read, and which is capable of a more efficient write cycle without sacrificing the eff iciency and speed of reading. In the present device, contrary to the prior art, the drain-to-floating gate capacitance Cd2 (Figure 213) is deliberately maximized to improve write and read efficiency, and the drain-turn-on condition is avoided by essentially decoupling the floating gate from the source diffusion. Furthermore, the device provides a floating gate capable of attaining a higher capacitively coupled voltage than previously available in the prior art thereby to further improve the 45 efficiency of the write cycle.

The invention thus provides a more dense non-volatile EPROM having a higher injection charge density per applied write voltage.

Further, a non-volatile EPROM device embodying the invention has a higher drive capacity, a more effective injection charge writing, a greater read threshold window, and a greater read current per applied 50 access volt.

Also, a non-volatile EPROM device embodying the invention has separate channel portions for access and for injection charge, does not have low level parasitic currents during write or read, and can be electrically programmed and electrically erased.

Claims (33)

1. A semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semi-conductor material substrata, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of the device, wherein each memory cell comprises a pair 60 of source-drain regions separated by a channel region and the field of the device includes channel stop regions formed over only a portion of the field to reduce the capacitance between the memory cells and the field.

2. A device according to claim 1, wherein the channel stop regions are formed directly adjacent only one of two sides of each of a selected number of source-drain regions, to reduce the junction capacitance 65 12 GB 2 073 487 A ' 12 between each. channel stop region and its adjacent source-drain regions.

3. A semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portions of the top surface in which memory cells and access circuitry are not formed forming a field of the device, the device comprising a plurality of source-drain regions formed in the semiconductor material substrate, each memory cell being formed by a pair of source-drain regions separated by a channel region, a floating gate positioned above but insulated by gate insulation from a portion of the channel region and also positioned above but insulated from a portion of the drain region, and a control gate insulated from but extending over both the floating gate and the portion of the channel region not covered by the floating gate and wherein.the semiconductor material substrate is doped with an impurity of a given conductivity and the field of the device is doped with 10 an impurity of the same conductivity such that a higher doping concentration is formed in the field of the device, the higher doping concentration being formed in the parts of the field of the device bounded by adjacent control gates and adjacent source drain regions to provide protection against leakage currents.

4. A semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface in which memory 15 cells and access circuitry are not formed forming a field of the device, the device comprising: a plurality of source-drain regions formed in the semiconductor material substrate, each memory cell being formed by a pair of source-drain regions separated by a channel region, a floating gate positioned above but insulated by gate insulation from a portion of the channel region and positioned above but insulated from a portion of the drain region an d a control gate insulated from but extending over both the floating gate and the portion of 20 the channel region not covered by the floating gate, and wherein the semiconductor material substrate is doped with an impurity of a given conductivity and the field of the device is doped with an impurity of the same conductivity such that a higher doping concentration is formed in the field of the device, the higher doping concentration being formed in those portions of the field of the device bounded by adjacent control gates and adjacent strips of conductive material from which are formed f loating gates before each strip has been etched into individual floating gates, thereby to substantially reduce the junction capacitance of each source-drain region with the channel region and the field of the device compared to the junction capacitance when the higher doping concentration is formed throughout the field of the device, while at the same time maintaining adequate protection against leakage paths.

5. A device according to claim 3 or 4, wherein the impurity in the field with a higher doping concentration 30 than the impurity in the other portion of the semiconductor material substrate is boron.

6. A device according to claim 5, wherein the concentration of boron is in the range of approximately 1 x 1013 to 5 X 1013 atoms per square centimetre.

7. A device according to anyone of claims 3 to 6. wherein a selected number of source-drain regions each serve as both the source of one memory cell and the drain of another memory cell.

8. A device according to anyone of claims 3 to 7 wherein the junction capacitance of each source-drain region with the channel region and the field of the device is reduced by approximately one-half compared to the capacitance of the junction when said higher doping concentration is formed throughout the field of the device.

9. A device according to anyone of claims 3to 8, wherein said impurity in the field with a higher doping 40 concentration than the impurity in the other portion of the semiconductor material substrate is provided to a surface concentration of 1012 to 1013 impurity atoms per square centimetre.

10. A device according to anyone of claims 3 to 9, wherein the control gate is insulated from both the floating gate and the portion of the channel region not covered by the floating gate by insulation comprising a layer of silicon dioxide and a layer of silicon nitride.

11. A device according to claim 10, wherein the silicon dioxide layer is of approximately 5 to 50 nm thickness and the silicon nitride layer is of approximately 10 to 80 nm thickness.

12. A device according to anyone of claims 3 to 11, wherein a region of the gate insulation between the floating gate and said portion of the channel region overlapped by the floating gate is selectively thinned.

13. A device according to claim 12, wherein the region of selectively thinned insulation has a thickness of 50 approximately 5to 25 nm and the floating gate insulation is selected from the group of insulators comprising silicon dioxide and silicon nitride.

14. A device according to anyone of claims 3 to 13, wherein the memory cells are formed in a P type well formed by selectively diffusing boron into an N type substrate.

15. A device according to claim 14, wherein the P type well is doped with a P type impurity to a concentration in the range of 1 X 1015 atoms CM-3 to 1 X 1017 atoms CM-3 and said N type substrate is doped to a concentration in the range of 3 x 1014 atoms CM-3 to 1 X 1017 atoms cm-3.

16. A method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top surface notformed with memory cells and access circuitry forming a field of the device, which field is formed 60 with channel stop regions between adjacent ones of a plurality of strip- like source-drain regions, in which method each channel strip region is formed directly adjacent only one corresponding source-drain region to reduce the junction capacitance between each channel stop region and the two adjacent source-drain regions.

17. A method of forming a semiconductor memory device having memory cells and access circuitry 65 P 11 c 13 GB? 073 487 A.13 formed in a portion of a top surface of a semiconductor maten. al substrate, the remaining portion of the top surface not formed with memory cells and access circuitry forming a field of the device, which field is formed with channel strips between adjacent ones of a plurality of strip-like source-drain regions, in which method each channel stop region is formed directly adjacent two corresponding source-drain regions after the formation of a second plurality of conductor strips disposed substantially perpendicularly to the source-drain region strips to act as gates, to prevent field inversion when high programming voltages are applied to the drain and gate of each memory cell and to enhance channel doping at the edge of the channel regions to increase programming efficiency.

18. A method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top 10 surface notformed with memory cells and access circuitry forming a field of the device, the method comprising: forming a masking oxide on a silicon substrate to a selected thickness; opening windows in the masking oxide through to the underlying substrate in the form of strips; placing a selected impurity in the substrate through said windows to form a plurality of source-drain regions; oxidizing the substrate exposed 15; by the window to a selected thickness to form a step in the silicon for use in further processing; removing all 15 oxide from the substrate exposing channel regions in between adjacent source-drain regions; forming a gate insulation of a- selected thickness over the surface of the substrate; forming polycrystalline silicon over the gate insulation to a selected thickness; doping said polycrystalline silicon with a selected impurity to a selected conductivity; forming said doped polycrystalline silicon into a first plurality of strips, each strip being parallel to and directly over part of a uniquely corresponding source-drain region and also overlying a 20 portion of the semiconductor substrate adjacentto said source-drain region to form a gate of a memory cell incorporating the corresponding source-drain region; formi ng insulation of selected thickness over the exposed surface of each strip of polycrystaline silicon; forming a second conductive layer to a selected thickness on said insulation; forming the second conductive layer into a second plurality of strips disposed substantially perpendicular to the previously formed first plurality of strips formed parallel to the source-drain regions; and implanting a selected impurity in that portion of the semiconductor substrate not covered by said first or second plurality of strips which forms the field of the device to form channel stop regions therein.

19. A method of forming a semiconductor memory device having memory cells and access circuitry formed in a portion of a top surface of a semiconductor material substrate, the remaining portion of the top 30 surface not formed with memory cells and access circuitry forming a field of the device, the method comprising: forming a layer of masking silicon nitride on top of a thin layer of masking silicon dioxide on a silicon substrate; opening windows in the silicon nitride and dioxide masking layers through to the underlying substrate in the form of long strips; placing a seletted impurity in said substrate through said windows to form a plurality of source-drain regions; oxidizing the strips in said substrate exposed by the window to arselected thickness to form a gate insulation for the portion of a floating gate to be formed over said source-drain regions; removing said masking nitride and performing a short oxide etch to remove only said thin masking oxide while leaving unetched substantially most of said gate insulation grown over said source-drain regions exposing channel regions in between adjacent source- drain regions; forming a gate insulation of a selected thickness in the silicon channel regions exposed in the previous step; forming polycrystalline silicon over the gate insulation to a selected thickness; doping said polycrystalline silicon with a selected impurity to a selected conductivity; forming said doped polycrystalline silicon into a first plurality of strips, each strip being parallel to and directly over a substantial part of a uniquely corresponding source-drain region and also overlying a portion of the semiconductor substrate adjacent to said source-drain region to form a floating gate of a memory cell incorporating the corresponding source-drain 45 region; forming insulation of selected thickness over the exposed surfaces of each strip of polycrystalline silicon; forming a second conductive layer to a selected thickness on said insulation; forming the second conductive layer into a second plurality of strips disposed substantially perpendicularly to the previously formed first plurality of strips formed parallel to the source-drain regions; and implanting a selected impurity in that portion of the semiconductor substrate not covered by said first or second plurality of strips which 50 forms the field of the device to form channel stop regions therein.

20. A method according to claim 18 or 19, wherein said impurity in the field of the device is formed by implanting boron to a surface concentration of about 1 X 1013 to 5 X 1013 atoms per square centimetre.

21. A method according to claim 18,19 or 20, wherein both the first and second plurality of strips are formed from polycrystalline silicon,

22. A method according to anyone of claims 18 to 21, wherein the impurity implanted in the field of the device is automatically self-aligned to the complement area of the first and second polycrystalline silicon layers to prevent field inversion when high programming voltages are applied to the drain and gate and to enhance the channel doping at the edges of the channel regions of each floating gate to increase programming efficiency.

23. A method according to anyone of claims 18to 22, wherein said step of forming insulation of selected thickness over the exposed surfaces of each strip of polycrystalline silicon comprises oxidizing the resulting structure to provide an oxide layer of selected thickness over the exposed surfaces of each strip of polycrystalline silicon.

24. A method according to claim 23, wherein the step of forming insulation of selected thickness over the 65 14.GB 2073487 A, 14 exposed surfaces of each strip of polycrystalline silicon further comprises forming a layer of silicon nitride of selected thickness over the oxide layer.

25. A method according to claim 24, wherein said oxide layer is formed to a thickness of between about 5 to 50 nm and said silicon nitride layer is formed to a thickness of between about 10to 80 nm.

26. A method according to anyone of claims 18to 25, and further comprising removing the portions of the first plurality of strips not beneath the second plurality of strips prior to implanting the selected impurity into the field of the device.

27. A method according to anyone of claims 18to 26, wherein said gate insulation over said source-drain regions comprises thermal silicon dioxide with thickness in the range 25 to 600 nm.

28. A method according to anyone of claims 18 to 27, wherein said gate insulation over the channel 10 regions has a thickness between about 5 apd 50 nrn and is selected from the group of insulators consisting of silicon dioxide and silicon nitride.

29. A method according to anyone of claims 18 to 28, wherein the area of gate insulation over the channel regions is bounded on all sides by thicker layer of thermal oxide to limit electronic tunneling to the area of the gate insulation over the channel regions.

30. A method according to anyone of claims 18 to 29, wherein the memory cells are formed in a P type well formed by selectively diffusing boron in a N type substrate.

31. A semiconductor memory device substantially as hereinbefore described with reference to Figures 2A to 7 of the accompanying drawings.

32. A method of forming a semiconductor memory device substantially as hereinbefore described with 20 reference to Figures 2Ato 7 of the accompanying Orawings.

33. Any novel feature or combination of features herein disclosed.

i Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey, 1981. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

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