GB2072387A - Method and apparatus for memory address modification in digital systems - Google Patents

Abstract

A digital system, including a processor unit, a memory unit, and signal lines interconnecting the processor unit and memory unit for communicating memory addresses and instructions therebetween, includes apparatus for monitoring the signal lines to detect when a pre-determined instruction is accessed from the memory unit by the processor unit to issue a select signal that controls memory address circuits to modify the address signals that are applied to the memory unit. <IMAGE>

Description

SPECIFICATION Method and apparatus for memory address modification in digital systems The present invention is directed to a method and apparatus for selectively modifying the address signals applied to a digital memory element having a plurality of addressable memory locations and in particular to apparatus that expands the addressing space so that at least two separate memory locations are separately addressable with the same effective address.

BACKGROUND OF THE INVENTION Digital processor-based units of the type to which this invention is directed typically include a digital storage unit (i.e., memory) which provides the processor with a program and working storage. An address bus, comprising N lines, interconnects the processor and memory, thereby providing the capability of identifying 2N addressable information storage locations. The information contained by the storage unit is accessed when the processor unit places an N bit address word on the address lines. While there may be a number of addressing options open (e.g., immediate addressing, indirect addressing, base addresssing, and the like) the storage capacity of the storage unit is usually limited to the addressing capacity defined by the number of address lines used to form the address bus.

Thus, for example, a digital system that includes 16 individual address lines for communicating an address from the processor to the memory can identify 65,536 information storage locations.

Further, each of the defined storage loca tio:-.s of the storage unit is fixed as to the r'jr.#ber of bits. At times, this can be a Fioblem. For example, each addressable memory location of the system may be defined as an 8 bit binary word. If it is desired to modify less than the entire word, all b- bits must be accessed, the desired bits modified, and the newly constructed word written back into the memory. If only one or two bits of the word are to be modified, this can be a relatively tedious and time consuming chore for the digital system.

SUMMARY OF THE INVENWON The present invention provides apparatus to alleviate the aforementioned problems by selectively modifying the addressing signals applied to the memory element so that each separate address communicated from a processor unit is capable of identifying one of at least two addressable memory locations. Two embodiments of the invention are discussed.

In one embodiment the invention is used in connection with a micrnprncessor-based video game apparatus to provide a memory element with an addressing system that allows a memory address to identify at least two separate bit-structures of the memory element. The contents of the memory element is accessible on a byte-per-byte basis or on a bit-per-bit (actually two bits2 basis. In an alternate embodiment the invention is used to expand the available addressing capabilities of a digital system.

In either embodiment the invention is used in conjunction with a microprocessor unit and memory storage element that are interconnected by data and address lines or buses. A decode circuit is coupled to the data bus to monitor the transmission of the instruction words communicated thereon from the memory storage element to the processor unit.

When the predetermined instruction word is detected, the decode circuit issues a select signal that modifies the address circuits used to communicate the address bus to the memory storage element. The address modification provided by the present invention allows the memory storage element to be structured so that it can be accessed on a byte (8 bit) basis when the select signal is absent. When the select signal is present, however, the memory address circuits are modified so that the address word appearing on the address bus will identify individual two-bit storage locations of the memory storage element.

The advantages achieved by the present invention are readily evident: First, the invention allows one to simply, easily, and with a minimum of circuit modification, effectively expand the addressing capability of data processing system. Typically, the number of address used to define and identify individual storage locations of a memory storage element is generally limited by the number of signal lines used to form the address bus that conveys the address to the memory storage element. Thus, for example, N address signal lines will define 2N memory locations. The present invention expands this count to at least twice that number.

A further advantage of the invention, stemming from the capability of accessing stored information in one of two (or more) different bit groupings, allows large amounts of binary data to be quickly stored with the capability of modifying only small portions of the data.

For a fuller understanding of the features, nature and advantages of the present invention, reference should be had to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE 71hffEDRAWINGS Figure 1 is a functional block diagram representation of a digitally implemented video display game system incorporating the present invention; and Figure 2 is a somewhat more detailed block diagram of the memory circuits and decode circuit of Fig. 1; and Figure 3 is a block diagram system that illustrates use of the present invention to expand the addressing capability of the system.

DETAILED DESCRIPTION OF THE ILLUSTRA TIVE EMBODIMENTS The embodiment of the present invention illustrated in Figs. 1 and 2 is used in a microprocessor based video game apparatus that utilizes a raster scan type video display.

Video information is assembled and stored in a display random access memory (RAM) at addressable locations corresponding to locations on a video display screen. During actual display time the assembled video information is sequentially accessed from the display RAM, assembled with various other signals to form a composite video signal that is transmitted to a video display for visual presentation.

Such apparatus is illustrated in Fig. 1 which shows a microprocessor 10 coupled to a memory unit 12 by an address bus 14 and address multiplex circuit 16. The microprocessor 10 and memory unit 12 are also interconnected by a data bus 20.

The memory unit 12 includes a program read only memory (ROM) 22, which contains the operating instructions for the microprocessor 10, and a display RAM 24 which holds the video information, in digital form, to be displayed. The data bus 20 is coupled to the input circuits of the display RAM 24 by a data multiplex circuit 26. The data output lines 28 of the display RAM 24 are connected to the data bus 20 by a buffer circuit 30.

The data bus is also connected to the bus examination logic 34 at each instruction word read from the program ROM 22 and communicated to the microprocessor 10 by the data bus 20. The examination logic 34 is activated by a SYNC signal initiated by the microprocessor 10 each time an instruction is read from the program ROM 22. The SYNC signal is conducted to the examination logic 34 by the signal line 35.

A signal line 36 communicates the output of the examination logic 34 to the address multiplex circuits 16 and the data multiplex circuit 26. The examination logic 34 produces a SELECT signal when a predetermined instruction word appears on the data bus 20; and the SELECT signal is communicated the address and data multiplex circuits 16 and 26, respectively, by the signal line 36. The purpose and function SELECT signal will be discussed in further detail below.

The output circuits of the display RAM 24, in addition to being coupled to the data bus by the buffer 30, are also connected to two (2) 4-bit shift registers 40 and 42 by the RAM output line 28. Two (2) 4-bit "nibbles" are concomitantly transferred to the parallel inputs of the shift registers 40 and 42. The respective serial outputs of the shift registers 40 and 42 are conducted to a color generator 44 as a 2-bit code describing luminance and color, by signal lines 46 and 48.

Synchronous operation of the system of Fig.

1 is effected by timing signals that are derived from a periodic square wave (in this case 10MHz) produced by a clock oscillator 50.

The square wave signal is applied to a sync generator 52 by a signal line 54. Although not specifically shown, it is to be understood that the sync generator includes the appropriate counting circuits for generating horizontal and vertical timing signals that ultimately form the horizontal and vertical sync signals that synchronize the sweep of an electron beam to provide a raster for video display. The horizontal and vertical sync signals are delivered to a video adder 56 where they are combined with color and luminance signals from the color generator 44 to form a composite signal on line 56 that is conducted to the display 60.

Additionally, the counting circuits (not shown) of the sync generator 52 are used to form address signals that are communicated to the address multiplex 16 by signal lines 62.

These address signals provide a direct memory access (DMA) of the video information stored in the display RAM 24 during each actual display frame.

The sync generator 52 also forms a CLK signal that is delivered to the microprocess 10 and the examination logic 34. The CLK signal provides the basic timing for the microprocessor 10; and is used by the examination logic 34 to drive a counter, as will be described below.

The sync generator 52 will also provide a LOAD signal that is delivered to the shift registers 40 and 42 to direct their acceptance of video information from the display RAM 24. Along with the LOAD is a CLOCK signal that effects the serial transfer of the video information on to the respective lines 46 and 48. Finally, the sync generator 52 also provides an ACCESS signal that is used by the address multiplex 16 in performing multiplex functions as will be described hereinafter.

Referring now to Fig. 2 there is illustrated in more detailed the display RAM 24 architecture, the address and data multiplex circuits 16 and 26, and examination logic 34. As shown, the display RAM 24 includes eight (8) 16K by 1 RAMs Mo-M7. The address bus 14 is coupled to the address circuits of each individual RAM M0-M7 by the address multi piex 16, which is constructed from a pair of staggered multiplex units 16a and 16b. The lower 14 lines of address bus 14, comprising the 14 individual address lines A0-A13, are applied to the A input section of the multiplex unit 16a.The upper 14 address lines A2-A,5 are applied to the B input section of multiplex unit 16a. Selection of which of the input sections A or B of the multiplex unit 16a is to be communicated to the output section (0) is made by the digital state of the signal communicated by the signal line 36 from the examination logic 34. Thus, for example, a logic zero on the signal line 36 selects the input section A and the address lines Ao-A,3 for communication to the output section 0 of the multiplex unit 16a. Alternately, a logic one will select the B input section. The address signals (i.e., Ao-A13 or A2-A,5) selected by the multiple unit 16a are directed to yet another multiplex unit 16b and applied to the input section A thereof.The DMA address signals formed by the sync generator 52 are applied to the B input section of the multiplex unit 16B. Selection as to which of the address signals (i.e., the DMA address or that portion of the bus 14 selected by the multiplex unit 16a) are finally directed to the RAMS Mo-M7 is effected by the ACCESS signal that is applied to the control (CTL) input of the multiplex unit 16b. The access signal is essentially a symmetrical, periodic (square wave) signal having a frequency of approximately 1.25 MHz that functions to provide the microprocessor 10 and the sync generator (via the DMA address signals) with alternate access to the display RAM 24.

The examination logic 34 is shown in Fig. 2 as including a decoder circuit 70 having 8 inputs to which are attached the corresponding signals lines Do-D7 of the data bus 20.

The signal line carrying the SYNC signal from the microprocessor 10 (Fig. 1) to the decoder logic 34 is applied to the enable (EN) input of the decoder 70. The output of the decoder 70 is coupled to the load (LD) input of a four stage binary counter 72. The CLK signal from the sync generator 52 (Fig. 1) provides the .king that drives the binary courier 72. A ti; d preset 74 is connected to the preset (PR) inputs of the binary counter 72 and the signal line 36, which controls the data multiplex circuits 16a and 26, emanates from the terminal count (TC) output of the counter 72. For purposes that will be explained more fully below, the counter is structured to count from the preset number to its terminal count (i.e., 1111 binary or 15, decimal), at which time it issues a terminal count pulse on the output line 36.Upon receipt of the immediately succeeding pulse of the CLK signal, the Q4 output of the binary counter 72, which is tied to the enable (EN) input of the binary counter 72, becomes a logic zero and latches the binary counter in a latched state until again preset.

The electronic beam (not shown) which scans the display screen 64 provides a raster that includes 232 adjacent, horizontal lines.

During each horizontal line scan, the beam is capable of being turned on or off 256 times; that is, the electron beam is capable of "assuming" 256 positions during each line scan.

Thus, the viewing area of the screen 64 can be thought of as being divided into 59,392 (256 X 232) positions or "pixels" by the scanning electron beam.

The color and luminance of each pixel are defined by two bhts of video information.

Thus, to be able to store an entire frame of video information for display on the display screen 64, the system must have a storage capacity of at least 118,784 bits (59,392 X 2) or 1 4,848 bytes, which storage capacity is easily met by the use of eight 16K (by 1 bit) RAMs Mo-M7.

In normal operation, the video information to be displayed on the display screen 64 is generated by the microprocessor 10, under direction of the program stored in the program memory 22, and stored in the display RAM 24. This video information is stored in the display ram at addressable locations that correspond to locations on the display screen 64 at which the information will be positioned. The video information often requires modification in response to changes in the input signals applied to the microprocessor 10 on the player control inputs.

During active display time, the multiplex unit 16b (Fig. 2) of the address multiplex unit 16 selects the DMA address signals provided by the sync generator 52 for application to the display RAM 24. The DMA address signals sequentially access the video information a byte at a time. The accessed byte is directed to the shift registers 40 and 42 by the signal lines 28 and loaded into the shift registers 40, 42 in response to the LOAD signal on the signal line 43, each register 40 and 42 accepting a 4-bit portion of the accessed byte.

Clock pulses in the form of the CLOCK signal provided by the sync generator 52 serially shift the video information from the shift registers 40 and 42 onto the signal lines 46 and 48.

The video information from the shift registers 40 and 42 is applied to a color generator 44 to create a video signal containing color and luminance information, depending upon the states of the bits applied thereto via the signal lines 46 and 48. The color/luminance signal produced by the color generator 44 is then communicated to the video adder 58 and on to the display unit 60. The display ram is updated with new information by the microprocessor 10 during the microprocessor access time (i.e., during one phase of the ACCESS signal). In this case, the address signals used to access the display RAM 24 are generated by microprocessor 10 and communicated to the address circuits of the RAMs M0-M7 by the address bus 14 via the A input sections of the multiplex unit 16a and 16b.

The video information is initially established in the display RAM 24, and periodically updated, by data that is assembled by the microprocessor 10 and conducted to the display RAM 24 on the data bus 20 and via the data multiplex (MPX) circuit 26 (Fig. 1). As illustrated in Fig. 2, the data MPX circuit 26 includes a multiplex (MPX) unit 26a which receives as it data inputs the eight signal lines D0-D7 of the data bus 20.The MPX unit 26a is constructed in a manner well known in the art to communicate the data bus 20 to the RAMS Mo-M7 in one of two modes; in the first mode, each of the signal lines D0-D7 of the data bus 20 is respectively conducted to a corresponding one of the RAMS Mo-M7. In a second mode, the signal line D6 is applied to RAMS Mo-M7 and the signal line D, is ap plied to the RAMS M4-M7. Mode selection is affected by the signal conducted by the signal line 36 from the TC output of the counter 72.

Thus, a binary zero selects the first (normal) mode and a binary one selects the second mode.

The data MPX circuit 26 includes a read/write multiplex (R/W MPX) unit 26b which communicates a read/write (R/W) signal created by the microprocessor 10 to the RAMS Mo-M7 to affect to the read/write operation. The R/W MPX 26b receives the signal line 36 from the counter 72 and, when the signal communicated thereon is a binary zero, communicates the R/W signal to all RAMS M ,-M7 simultaneously. However, when the signal on the signal line 36 is a binary one, the R/W signal is communicated to only a pair of the RAMS M0-M7, as determined by the states of signals communicated by the signal lines A < ,-A1 of the address bus 14.

The instructions which direct the operation of microprocessor 10 are sequentially accessed from the program memory 22 and communicated to the microprocessor by the data bus. A predetermined class of instructions available to the microprocessor is reserved specifically for address modification by the invention to allow smaller than 1-byte components of the information. The present invention incorporates a microprocessor manufactured by MOS Technology, Inc. of Norristown, Pennsylvania, and sold under the part number MCS6502. One particular instruction class in the instruction repertoire for such a microprocessor is an indirect-X (IND-X) instruction.For the 6500 microprocessor series, an IND-X instruction is a 2 byte instruction, the first byte being the operation code and the second byte being a "pointer" address in the zero page" location of the display memory 24 (i.e., the first 256 stooge locations).

These two bytes of memory location contain an address identifying yet another storage location in the display RAM 24. The IND-X instruction cycle is performed by the microprocessor 10 as follows: 1. The operation code is accessed from the program memory 22 and decoded.

2. The microprocessor then accesses the next sequential address of the program ram 22 to obtain the base address.

3. The X register (not shown) internal to the microprocessor 10 is added to the base address to form a pointer address.

4. The pointer address is used to form an address that accesses a memory location of display RAM 24 to obtain a first address byte (ADDR-1).

5. The microprocessor increments the pointer address and again reads the display ram 24 to obtain the second portion of the address (ADDR-2).

6. The address (i.e., the combination of ADDR-1 and ADDR-2) is placed on the address bus 14, data placed on the data bus 20, and the R/W signal generated to write data into the memory location of display RAM 24 specified. Alternately, data can be read.

As noted above, the IND-X instruction is utilized to set the present invention into operation. This is accomplished as follows: When the memory circuits are to be modified, the IND-X instruction is accessed during normal program sequence from the program memory 22 by the microprocessor 10. The SYNC signal, generated by the microprocessor 10 when an instruction is being accessed, gates the signals then appearing on the data bus 20 to the circuitry of decoder 70 for decoding.

When the IND-X is decoded, the decoder 70 provides a pulse that is applied to the LD input of the binary counter 72. This causes the binary counter 72 to be preset to a binary 11 (i.e., "1011"). When so present, the Q4 output of the binary counter 72 goes from a logic 0 state to a logic 1 state. This, in turn, enables the binary counter 72, bringing it out of its previously latched, disabled state. The binary counter 70 now begins to count the CLK signal applied to the C input. At the end of the instruction cycle for the IND-X, and at the time that the address is presently placed on the address bus 14 and data is placed on the data bus 20, the counter 72 will reach its terminal count of 15 and will issue from the TC output thereof a signal on the signal line 36.

As Figs. 1 and 2 indicate, the signal from the TC output of the binary counter 72 is communicated by the signal line 36 to the multiplex unit 16a where it is applied to the CTL input to effect selection of the signals applied to the B inputs of the multiplex unit 16a, i.e. signal lines A2-A,5. This address is communicated to the display RAM 24 via the multiplex unit 16b during a microprocessor access period.

At the same time, the terminal count pulse provided by the binary counter 72 is also communicated by the signal line 36 to the data multiplex unit 26 and R/W MPX unit 26b. As noted above, a pair (i.e., one of the RAMs Mo-M3 and one of the RAMs M4-M7) of the RAMs Mo-M7 are selected during the presence of the terminal count signal by the R/W MPX unit 26b, as determined by the signals on the two address lines Ao and A,.

The data signal appearing on the data bus signal line D6 will be written to a one-bit location of the selected one RAMs M0-M3 at the address identified by the signals appearing on the signal lines A2-A15 of the data bus 14.

Similarly, the data signal appearing on the signal line D7 of the data bus 20 will be written to the one bit location of the selected RAM M4-M7 at the same identified address.

Upon the next sequential pulse of the CLK signal, the binary counter 72 will assume the state .that sequentially follows its terminal count, i.e., zero (binary "0000"). The terminal count signal terminates, returning the address multiplex and data multiplex circuits 16 and 26, respectively, to their normal states.

At the same time, the Q4 output of the binary counter 72 assumes a binary 0 which, when coupled back to the enable (EN) input of the binary counter 72, disables the counter until again preset to force the Q4 output to a binary 1.

Thus, by using a predetermined instruction, for example, as described herein, an indirect X (IND-X) instruction of the 6500 microprocessor series instruction set, the address to the display ram was momentarily modified to allow the microprocessor 10 to write information to a storage unit defining the smallest resolution element of the display screen, i.e., two bits, which describe a display screen pixel.

However, the invention can be alternately utilized to expand the addressing capability of a digital system, such as that shown in Fig. 1.

Thus, turning now to Fig. 3, the alternate embodiment of the present invention is shown. As illustrated, the alternate embodi- ment includes the memory element 90, which would include the program and display memory of Fig. 1, but would have twice the address memory locations capable of being addressed by the 16 signal lines of the address bus 14, i.e., 216 x 2 or 131,072. Each field 92, 94 is addressed on a mutually exclusive basis by the signals communicated thereto on the address bus 14 via a multiplex (MPX) unit 96. Operation of the present invention selects which half 92, 94 of the memory element 90 as applied thereto the address bus 14, using the IND-X instruction.

The circuitry of Fig. 3 would replace the address multiplex 16 and memory unit 12 of Fig. 1. All other components would remain essentially the same. During normal operation, the state of the signal on line 36 would be a binary zero. However, in the same manner as described above, accessing an IND-X instruction will cause the binary state of the signal line 36 to become a logic 1. Applied to the control (CTL) input of the MPX 96, this logic 1 causes the address bus 14 to be removed from the field 92 of the memory element 90 and applied to the field 94 thereof.

While the above provides a full and complete disclosure of one embodiment of the invention, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the invention. Using the present invention, one or more predetermined instructions can be used to modify the address communicated on the address bus 14 and apply the address to different sections of the memory. Thus, each such predetermined instruction would increase the available storage capacity by a factor of 2.

Therefore, the above description and illustrations should not be construed as limiting the scope of the invention, which is defined by the claims appended hereto.

Claims (12)

1. In a digital system including a processor unit, a memory element for storing binary information, and signal lines intercoupling the processor unit and the memory element for communicating address and data signals therebetween, the binary information including a plurality of instruction words selectable by the processor unit, apparatus for expanding the number of available addresses of the memory element by the processor unit, the apparatus comprising:: means coupled to the signal lines for monitoring the instruction words appearing thereon to provide a select signal when at least a predetermined one of the instruction words is communicated on the signal lines; means responsive to the selected signal and coupled to the signal lines for communicating a first portion of the address signals appearing thereon to the memory element when the select signal is absent and for communicating a second portion of the address signals to the memory unit when the select signal is present.

2. The digital system of claim 1, wherein the monitoring means includes means for providing the select signal when one of a predetermined class of the instruction words is communicated on the signal lines.

3. Apparatus for altering the address signals communicated to a memory unit from a digital processor unit, the memory unit and the digital processor unit being interconnected by signal lines for communicating digital instruction words and address words therebetween, the apparatus comprising: means coupled to the signal lines and responsive to at least a predetermined one of the instruction words for issuing a binary signal when the predetermined instruction word is detected on the signal lines; means coupled to the signal lines and responsive to the signal for modifying the address signals communicated to the memory unit.

4. The apparatus of claim 2, wherein the modifying means include a multiplex unit for selecting and communicating a first portion of the signal lines to the memory unit when the binary signal is absent and for selecting and communicating a second portion of the signal lines to the memory unit when the select signal is present.

5. The apparatus of claim 2, including means for enabling the detecting means only when an instruction word is present on said signal lines.

6. The apparatus of claim 2, including means for modifying the data communicated to the memory unit during the presence of the binary signal.

7. The apparatus of claim 2, wherein the binary signal issuing means includes means for issuing the binary signal in response to any one of a predetermined class of the instruction words is detected on the signal lines.

8. The method of altering the address signals communicated to a memory unit from a digital processor unit interconnected by signal lines that communicate multi-bit instruction words and address words therebetween, comprising the steps of: monitoring the signal lines to detect the communication thereon of a predetermined one of the instruction words to the processor unit; generating a binary signal for a predetermined time period upon detection of the presence of the predetermined one of the instruction words on the signal lines; modifying the address signals communicated on the signal lines during the predetermined time period of the binary signal.

9. A digital system comprising a processor, memory means, signal lines for communicating address signals, data signals, and instruction words between the memory means and the processor, and detection means operable to detect the presence of at least one particular instruction word on said signal lines and, in response thereto, to cause particular address signals on said signal lines to address a different memory location from that which would be addressed by the same address signals prior to said detection.

10. A system as claimed in claim 9, in which said address signals are operable to address a complete memory word prior to said detection, and only a portion of a word after detection.

11. A system as claimed in claim 10, wherein said address signals are operable after said detection to address a portion of a word which is different from the word addressed by the same address signals prior to detection.

12. A digital system substantially as herein described with reference to Figs. 1 and 2, optionally modified as described with reference to Fig. 3, of the accompanying drawings.