GB2071937A - Controller for coupling power to an N phase load - Google Patents

Abstract

An N phase induction motor 11 having a torque that is considerably higher during starting than while running during normal operation is selectively connected, during the starting period, to an N phase power line source phi a, phi b, phi c, and during normal operation to an N phase, variable frequency pseudo- sinusoidal switching converter 21, 22, 26. In response to a phase and frequency lock being achieved between the pseudo- sinusoidal and power line powers, power from power line terminal K for phase K is decoupled from the motor winding for phase K, as pseudo-sinusoidal power of phase K is being applied to the winding for phase K, where K is selectively and sequentially 1, 2 ... N. The reverse operation is performed in response to a change command signal after a phase and frequency lock has been achieved between the pseudo-sinusoidal and power line power. <IMAGE>

Description

SPECIFICATION Controller for coupling power to an N phase load Technical field The present invention relates generally to an apparatus for controlling the power applied to an N phase load and, more particularly, to an apparatus for controlling the coupling of power to an N phase load from an N phase power line and an N phase pseudo-sinusoidal source, where N is an integer greater than two.

Background art It is old to control an N phase power load, such as an N phase induction motor, by varying the frequency of an N phase pseudo-sinusoidal switching converter than inverts a DC voltage into a multi-step wave having substantially vertical edges, between which are constant voltage variations. A primary advantage of such a system is that the power requirements of the converter decrease with decreasing frequency requirements of the load, thereby resulting in energy savings in a proportional system. Inverters of the converters generally employ semiconductor elements, such as bipolar or field effect power transistors.While these semi-conductor elements are capable of handling the power requirements for normal, variable speed operation, it has been found that there are certain load conditions which require excessive, possibly destructive currents to flow through the semiconductor elements.

In particular, certain induction motors have a breakway torque, during starting, that is much larger than the torque during normal running operation. The high breakaway torque, during starting, may result in destructive surge currents through the semiconductor elements of the converter.

It is, accordingly, an object of the present invention to provide a new and improved apparatus for enabling a variable frequency, multi-phase load that is normally driven by a pseudo-sinusoidal switched inverterto be driven by currents that are possibly destructive to the inverter.

Another object of the invention is to provide an apparatus for applying starting current to a multiphase motor having a much higher starting torque than normal running torque, wherein the motor is responsive during normal operation to variable frequency pseudo-sinusoidal power from a switched inverter which is incapable of handling the current required by the motor during the starting interval.

Disclosure of the invention In accordance with one aspect of the invention, the problem is solved by synchronous switching of power applied to an N phase load from an N phase power line, sinusoidal source and a switched N phase inverter source, where N is an integer greater than two. A first switch means is provided in series between phase K of the power line sinusoidal source and phase K of the load, where K = 1, 2 ... N. The N phase inverter derives N pseudo-sinusoidal waves having substantially vertical edges, with the N waves being displaced from each by 360/N. Phase Kofthe inverter includes an AC output terminal connected to phase K of the load.The converter in phase K includes second switch means between a DC source for the inverter and an output terminal so that opening of the second switch means prevents current from flowing from the DC source to the output terminal and closing of the second switch means results in current flowing from the DC source to the output terminal. The first and second switch means are controlled in synchronism so that there is synchronized switching to phase K of the load between the power line current at phase K and current from the pseudo-sinusoidal power at phase K. For the motor starting application, the first and second switch means are controlled so that power from power line terminal K is decoupled from the motor winding for phase K as pseudo-sinusoidal power of phase K is being applied to the motor winding for phase K.The power is transferred from power line terminal K to pseudo-sinusoidal power of phase K in sequence for the difference phases. When the windings for all N phases are responsive to the power, the frequency of the sinusoidal power is varied.

To change the N phase synchronous motor or other load from variable speed or frequency operation to fixed frequency operation powered by the N phase power line, the pseudo-sinusoidal power of phase K is removed from phase K of the load as phase K of the power line is being applied to phase K of the load. Again, the powers for the different phases are sequentially switched.

To provide a smooth and orderly transfer of power between the sinusoidal and pseudo-sinusoidal sources, with a minimum of transients, frequency and phase lock between control for the pseudosinusoidal source is achieved. In addition, switching preferably occurs when zero current is derived by the power line andXinverter to minimize transients.

The first and second switch means may take many different configurations. In a first embodiment, the second switch means includes only switching elements of the switching inverters. In this embodiment, the DC source supplied to the inverter is decoupled from the load when the second switch means is open circuited by back biasing or cutting off all of the semiconductor elements included in the inverter. Because of the frequency and phase lock, the semiconductor elements of the inverter are initially operated so the current initially applied by the inverter has the same phase as the current which is being removed from the load by the first switch means. Preferably, such a current has a zero amplitude, to minimize transients and enable precise switching to be achieved with bilateral silicon controlled switches of the first switching means.Forward gate bias for the silicon controlled rectifier switches of the first switching means is removed during the half cycle of the power line voltage immediately preceding activation of the inverter.

Current continues to flow through the silicon controlled rectifier switch of the first switching means until a zero power line current occurs, at which time the silicon controlled rectifier switch automatically opens and operation of the inverter is initiated.

The inverter for phase K in the first embodiment is preferably, but not necessarily, connected to phase K of the load through a relay contact, which can be considered as part of the second switch means. The relay contact, as well as all of the switching elements of the inverter, is open circuited in response to a motor start command. After frequency and phase lock between the power line and a control for the inverter has been achieved, the relay contact is closed. The contact remains closed until after certain operations have been performed in response to a signal which commands the load to be decoupled from the inverter pseudo-sinusoidal power and coupled back to the power line. Such a relay contact is a safety precaution which is not necessary in all instances.

In accordance with a further embodiment, the second switching means for phase K includes a bilateral silicon controlled rectifier switch that is gated on in synchronism with the effective opening of the silicon controlled rectifier switches of the first switching means, after phase lock between the inverter and the power line has been achieved in response to a motor start command. The silicon controlled rectifier switches of phase K of the second switching means remain in a forward biased state until the half cycle immediately preceding the application of gate forward bias to the silicon controlled rectifier switch of phase K of the first switching means, after the reverse transfer control has caused frequency and phase lock to be achieved between the power line and inverter.By utilizing the two silicon controlled switches, an orderly transfer of power is made in both directions between the power line and the inverter without the rigorous control of the starting time for the inverter, as exists in the first embodiment wherein the second switching means does not include the silicon controlled rectifier switch.

It is another object of the invention to provide a new and improved apparatus for changing an N phase load from variable frequency operation powered by a switching converter that derives N phase pseudo-sinusoidal power to fixed speed operation powered by an N phase power line.

A further object of the invention is to provide synchronous transfer of an N phase load between an N phase power line and an N phase pseudosinusoidal switching converter with a minimum of transients being derived during the transfer.

Because the switched inverter which drives the N phase pseudo-sinusoidal source need not handle large transients, as occur during start of many induction motors, the inverter can employ lower power semiconductor switching elements. Thus, in many applications there can be a substantial reduction in the high cost of the switching inverters, with a slight increase in complexity of low level, relatively inexpensive control circuitry.

It is therefore, an additional object of the invention to provide a new and improved, relatively inexpensive variable frequency controller for a multiphase load.

The advantage of having synchronous transfer of a load from the variable frequency, pseudosinusoidal inverter to a fixed frequency power line is that for certain applications there are extended periods of fixed frequency operation. During these periods of fixed frequency operation, little power is dissipated in the inverters, to increase the operating efficiency of the system.

It is, therefore, an additional object of the invention to provide a more efficient system for enabling a multi-phase load to be controlled at variable or fixed frequency.

Another reason for providing the reverse synchronous transfer of the load from the variable frequency inverter to the fixed frequency power line is that added reliability and system flexibility are provided during scheduled maintenance of the variable speed system or in the event of an unscheduled shut down due to the variable speed system.

It is, therefore, still another object of the invention to provide a new and improved more reliab!e system capable of supplying variable and fixed frequency power to a multi-phase load.

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of several specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.

Brief description of drawings Figure lisa block diagram of the present invention which is applicable to several different embodiments; Figure 2 is a circuit diagram of a preferred configuration for a trip switch bridge of one phase in the apparatus of Figure 1; Figure 3 is a waveform of the voltage applied between two phases of the load of Figure 1 in response to activation of the trip switch bridges for those phases; Figures 4, 5 and 6 are circuit diagrams of three different embodiments of series switches which can be employed between the output of each trip switch bridge and each phase of the load in the system of Figure 1; and Figures 7 and 8 are circuit diagrams of series switches which can be employed between each phase of the sinusoidal source and each phase of the load in the system of Figure 1.

Best mode for carrying out the invention The drawing and detailed description of the draw ing are concerned with a three phase system, i.e., a system having a three phase sinusoidal input, a three phase load, and a three phase pseudosinusoidal switched bridge inverter. It is to be understood, however, that the principles of the invention are applicable to any system having three or more, i.e., more than two phases. It is also to be understood, in considering Figure 1, that many connections are not specifically illustrated, to simplify the drawing. Instead, like connections have like nomenclature and many of the connections are indicated by notations on the drawing.

Reference is made more particularly to Figure 1 wherein a three phase load, in the form of Y connected induction motor 11 having three phase windings 12, 13 and 14, is selectively connected to a three phase sinusoidal power line source, having phases ap bp, and 0,,, respectively applied to power line terminals 15, 16 and 17 and to a variable frequency switched, pseudo-sinusoidal source derived at terminals 18,19 and 20 by an AC to DC and AC converter including rectifier 25 and a switching inverter containing trip switch bridge 21,22 and 23.

Bipolar DC voltages +E and-E are applied to bridges 21-23, as well as other components of the system, by a three phase AC rectifier 25 responsive to the three phase power line sinusoidal input at terminals 15-17.

Rectifier 25 includes a pair of output terminals 26 and 27 on which are respectively derived equal but opposite polarity DC voltages +E and -E, referenced to ground terminal 28.

The DC voltages applied to bridges 21-23 are switched by the bridges, during normal operation, so that the bridges derive a notched, multi-level output waveform having substantially vertical edges and flat transitions between these edges. Bridges 21-23 are responsive to control signals from trip switch bridge controller 31 so that the pseudosinusoidal waveforms derived from the bridges are phase displaced from each other by 120 degrees, i.e., 360/N, where N = the number of phases of the system. During normal operation, the frequency of the waveform derived from each of bridges 21, 22 and 23 is variable, to control the speed of induction motor 11. To this end, a three phase variable frequency oscillator 32 is provided as an input for controller 31.

Under certain circumstances, however, it may be prudent to disconnect trip switch bridges 21-23 such that they are not required to supply power to motor 11. In particular, motor 11 may have a starting breakaway torque that is much larger than the normal running torque thereof. Under such circumstances, trip switch bridges 21-23 may be incapabie of supplying adequate power to the load, without destruction to the components thereof. In accordance with the present invention, the load is started directly from the three phase power line, sinusoidal source applied to terminals 15-17 and after the heavy starting load has subsided, the system is switched so that the load is driven by the pseudo-sinusoidal source, enabling the motor speed to be varied in a continuous manner.In addition, the system can be operated in reverse sequence so that, if desired, the variable speed mode can be exited and then the load can be switched to the sinusoidal, power line source.

In a preferred embodiment, each of trip switch bridges 21-23 has a configuration as illustrated in Figure 2 and the voltage variation between a pair of the trip switch bridges is indicated by the waveform of Figure 3. Considering Figure 2, the trip switch bridge includes four bipolar NPN power transistors 35-38 having the emitter-collector paths thereof series connected with each other, between positive and negative DC power supply terminals 26 and 27.

A common terminal between the emitter of transistor 36 and the collector of transistor 37 is connected to an output terminal, such as output terminal 18 at which is derived the pseudo-sinusoidal waveform, of a type illustrated in Figure 3. Shunting the emitter collector path of each of transistors 35-38 is a separate anti-parallel diode 39, to provide bilateral current flow between the bridge and load 11. At a common terminal for the emitter of transistor 35 and the collector of transistor 36 is connected the cathode of diode 41, having a grounded anode. At a common terminal between the emitter of transistor 37 and the collector of transistor 38 is the anode of diode 42, having a grounded cathode. Diodes 41 and 42 provide paths to ground for current flow to zero output voltage.

The base electrodes of transistors 35-38 are responsive to sequenced control voltages from trip switch bridge controller 31,so that the transistors are activated either in a saturated or cut-off condition, whereby the transistors can be considered as series conducting or cut-off switches. As described in greater detail in Belgium patent 878880, transistors 35-38 of each of bridges 21-23 are activated to derive the notched waveform of Figure 3 between a pair of adjacent trip switch bridge output terminals.

For example, the waveform of Figure 3 exists between terminals 18 and 19, during normal opera tion of trip switch bridges 21 and 22. A waveform having the same shape as that of Figure 3 exists between terminals 18 and 20 in response to activation of trip switch bridges 21 and 23 but the waveform between terminals 18 and 20 is displaced 120 degrees from the waveform of Figure 3; similarly, between terminals 19 and 20 of trip switch bridges 22 and 23 there is derived a waveform having the same shape as the waveform of Figure 3, but displaced 240 degrees from it.

At 60Hz, the pseudo-sinusoidal waveform of Figure 3 is characterized by having 24 substantially vertical edges and 23 substantially horizontal portions to form notches between the vertical edges during each 360 degree cycle. The first and second half cycles are mirror images of each other, with each including relatively short duration, relatively constant, horizontal portions at a zero value, and at an E value, which is one-half of the maximum 2E value of the waveform. At the maximum, 2E value, each half cycle of the waveform includes a pair of relatively short, substantially constant, horizontal levels and a considerably longer, substantially constant level.Each of bridges 21-23 is initially activated by controller 31 so that the voltages initially applied to terminals 18-20 are all zero, a result initially achieved by driving two center transistors 36-37 of bridges 21-23 to an on condition. Bridges 21-23 are sequentially driven out of the initial condition so that the waveform of Figure 3 is repeatedly applied between the output terminals of the bridges.

To control the application of sinusoidal power from power line terminals 15-17 and pseudosinusoidal power from bridge output terminals 18-20 to load 11, six series switches 41-46 are provided. As described later in this writing, the series switches may take different configurations; in certain instances series switches 44,45 and 46 may not be necessary. Switches 41,42 and 43 are respectively connected between power line terminals 15, 16 and 17 and windings 12, 13 and 14 of load 11. In contrast, series switches 44,45 and 46 are respectively connected between pseudo-sinusoidal outputter minals, 18, 19 and 20 and windings 12, 13 and 14 of load 11.Switches 41-43 are responsive to control voltages derived from power series switch control ler, 47, while switches 44-46 are responsive to control signals from bridge series switch controller 48.

Controllers 47 and 48 are responsive to sequencer 49. Sequencer 49 includes a motor start switch 51, which enables motor 11 to be initially connected to power line input terminals 15-17 and to be subsequently connected to the pseudo-sinusoidal three phase voltages derived from terminals 18-20. Sequencer 49 also includes a reverse transfer switch 52 which, when activated, causes motor 11 to be switched from energization by the pseudosinusoidal voltages derived from terminals 18-20 to the sinusoidal voltages derived from terminals 18-20 to the sinusoidal voltages derived from power line terminal 15-17. Sequencer 49 is responsive to positive peak voltage detectors 53, 54 and 55 which respectively detect the peak voltages applied to power line terminals 15,16 and 17.Sequencer 49 is also responsive to negative going zero value detectors 56,57 and 58 which respectively derive a control output signal in response to a negative going zero crossing in the three phase voltages applied to power line terminals 15,16 and 17. It is to be understood that detectors 53-55 can be responsive to a negative peak voltage of the sinusoidal power line voltage applied to terminals 15-17, in which case detectors 56-58 are responsive to positive going zero crossings of the power line voltages. In one mode of operation, sequencer 49 is also responsive to control signal outputs of positive peak detectors 61-63, which respectively sense the positive peak current applied by bridges 21,22 and 23 to terminals 18, 19 and 20.The positive peak currents supplied to terminals 18-20 occur after the center of the position portion of the pseudo-sinusoidal voltage waveform because of the smoothing effects of inductive load 11 on the current.

To provide for the smooth transfer of energy between the three phase sinusoidal source supplied to power line terminals 15-17 and the pseudosinusoidal sources at terminals 18-20, it is necessary for the pseudo-sinusoidal sources to be at the same frequency and phase as the three phase power line source at the time of the transfer. To this end, the trip switch bridge controller 31 is responsive to phase locked loop 65. Initially, during the strating period, phase locked loop 65 is responsive to the three phase power line terminal 15 until a phase lock has been achieved between the control voltage applied by controller 31 to bridges 21-23 and the voltage at terminal 15.Phase locked loop 65 is responsive to control signals derived within trip switch controller 31 and respectively applied to trip switch bridges 21-23, so that the frequency and phase of the pseudo-sinusoidal voltages derived from the trip switch bridges are locked to the frequency and phase of the signal effectively applied to phase locked loop 65. When a phase lock has been achieved between the sources at terminals 15-17 and terminals 18-20, as sensed by phase lock detector 64, sequencer 49 is activated to decouple the power line terminal 15 from phase locked loop 65 and to substitute the three phase output of variable frequency oscillator 32 for the power line voltages.

After the three phase variable frequency oscillator output has been coupled to phase locked loop 65, variable speed control of motor 11 is achieved by varying the frequency of oscillator 32.

Sequencer 49 responds to the various inputs thereof, viz: closure of switch 51 or 52 and the outputs of detectors 53-58 and 61-64, to control activation of controllers 47 and 48 for series switches 41-46. Sequencer 49 also supplies control signals to phase locked loop 65, to determine whether the phase locked loop is to be responsive to the three phase output signal of variable frequency oscillator 32 or the power line sinusoidal wave applied to terminal 15. In one mode of operation, sequencer 49 also activates controller 31 so that all ofthetrnns:s- tors 35-38 of trip switch bridges 21-23 are initially cut-off and the transistors are initially activated, after cut-off, so that the first negative going notch in the pseudo-sinusoidal waveform is derived.

According to one embodiment, each of series switches 44,45 and 46 is a normally open circuited relay contact 71, as illustrated in Figure 4. In this embodiment, it is essential for all of the transistors 35-38 of all of the trip switch bridges 21-23 to be initially cut-off and for the bridges to be activated so that the first negative going notch is derived from the trip switch bridge after closure of contact 71.

Contact 71 of each of series switches 44,45 and 46 is closed by controller 48 applying an energizing voltage to relay coil 72, which is associated with contact 71. In response to the energizing voltage being applied to coil 72, contact 71 is closed.

In accordance with a second embodiment, Figure 5, each of series switches 44,45 and 46 includes normally open circuited relay contacts 73, controlled by coil 74. Contact 73 is shunted by a bilateral silicon controlled rectifier switch including oppositely connected silicon controlled rectifiers 74 and 76, to provide bilateral conduction for current flowing through the series switch. In operation, sequencer 49 responds to closure of motor start switch 51 by activating coil 74 to initially cause contact 73 to be open circuited. Subsequently, after detection of (1) phase and frequency lock, (2) the peak voltage of the AC sinusoidal power, and (3) the negative going zero crossing of the AC input power, gate voltages are applied to the gate electrodes of silicon controlled rectifiers 75 and 76. After the gate electrodes of rectifiers 75 and 76 have been forward biased and the rectifiers are conducting, controller 48 applies an energizing voltage to winding 74, causing contact 73 to close.

In response to reverse transfer switch 52 being closed, sequencer 49 supplies an activating voltage to controller 48. After frequency and phase lock between the pseudo-sinusoidal output voltages of bridges 21-23 and the sinusoidal power line voltages at terminals 15-17 has been detected by detector 64, sequencer 49 supplies an energizing voltage to winding 74 causing the winding to open circuit contact 73. Current flow from the pseudo-sinusoidal source to the load continues through rectifiers 75 and 76 until a positive peak voltage of the sinusoidal current is detected by detectors 61-63, which causes removal of the forward bias voltage for the gate electrodes of silicon controlled rectifiers 75 and 76.

At this time current is flowing through rectifier 76 to the exclusion of rectifier 75 because the phase lock assures positive voltage from the pseudo-sinusoidal source. Current continues to flow through rectifier 76 until a zero crossing occurs in the pseudo-sinusoidal waveform because of the inherent properties of the silicon controlled rectifier. Silicon controlled rectifier 75, which is in a non-conducting state at the time that a positive peak current is detected, remains in the cut-off state.

The switch configuration of Figure 5 can be modified, in the manner illustrated by Figure 6. In Figures, relay winding 74 activates contact 73 and silicon controlled rectifiers 75 and 76 are energized by sequencer 49 in the same manner as described in connection with Figure 5. In Figure 6, however, current limiting resistor 77 is connected in series with the anode cathode path of silicon controlled rectifiers 75 and 76, to prevent excessive current from being drawn from trip switch bridges 21-23.

One preferred comfiguation for each of series switches 41,42 and 43, respectively connected between power line terminals 15, 16 and 17 and windings 12, 13 and 14, is illustrated in Figure 7. The series switch illustrated in Figure 7 includes normally open circuited relay contact 81, which is closed in response to energization of coil 82 by a control voltage from power series switch controller 47, in turn responsive to an output of sequencer 49. In series with normally open contact 81 is a bilateral silicon controlled rectifier switch including back to back, parallel silicon controlled rectifiers 83 and 84, having gate electrodes that are also responsive to an output of controller 47.

In response to closure of motor start switch 51, sequencer 49 activates power series switch controller 47 in such a manner as to cause energization of coil 82 of all of switches 41-43 and the application of forward biasing voltage to the gate electrodes of silicon controlled rectifiers 83 and 84. Thereby, current flows, with an arbitrary phase, from each of power line terminals 15-17 to windings 12-14 through contact 81 and one of silicon controlled rectifiers 83 or 84, depending upon the polarity of the power line voltage.After phase lock between the power line voltage and the pseudo-sinusoidal voltages at the output terminals of trip switch bridges 21-23 has been detected by phase lock detector 64 and a positive peak voltage value for the AC power line voltage at terminals 15-17 has been detected, sequencer 49 is activated to apply a signal to controller 47, causing the forward bias to be removed from the gates of silicon controlled rectifiers 83 and 84. Rectifier 84 continues to conduct until the voltage of the phase to which it is connected goes through zero. Rectifier 83, being back biased by the power line voltage, remains in a non-conducting state once the forward bias is removed from the gate electrode thereof.After negative going zero detectors 56-58 detect a zero value for the power line voltage, sequencer 49 activates controller 47 to remove the energization from winding 82, causing contact 81 to open.

In response to closure of reverse transfer switch 52, sequencer 49 activates power series switch controller 47 in such a manner as to cause an activating voltage to be applied to winding 82, whereby contact 81 is closed. After detectors 53-55 have detected a peak positive voltage at terminals 15-17 and negative going zero detectors 56-58 have detected a negative going zero crossing at terminals 15-17, sequencer 49 activates controller 47 to apply a forward biasing voltage to the gate electrodes of silicon controlled rectifiers 83 and 84. Thereby, current is applied by terminals 15-17 through series switches 41-43 to windings 12-14, respectively.

A further embodiment of series switches 41-43 is illustrated in Figure 8. The embodiment of Figure 8 is very similar to that of Figure 7, except that normally open relay contact 85 is connected in parallel with the anode cathode paths of silicon controlled rectifiers 83 and 84. Contact 85 is controlled by winding 86, which is energized by controller 47 simultaneously with the forward and reverse biasing of gate electrodes of silicon controlled rectifiers 83 and 84. Because of the considerably longer response time of winding 86 and contact 85 than the response time of rectifiers 83 and 84, contact 85 is not closed simultaneously with forward biasing of the rectifiers.

The contact, however, is, in many instances, more energy efficient when carrying line currents for long periods of time.

Consideration is now given to the operating sequence of a circuit wherein each of series switches 44,45 and 46 includes a single contact 71, as illustrated in Figure 4, and each of series switch 41, 42 and 43 includes a pair of back to back silicon controlled rectifiers 83 and 84, in.series with a relay contact 81, as illustrated in Figure 7. It is initially assumed that no voltage is applied to any of the phase windings 12-14 of motor 11 and that switch 51 is open.

In response to closure of switch 51, sequencer 49 is activated so that a control voltage is initially applied to trip switch bridge controller 31, to cause the trip switch bridge controller to open circuit transistors 35-38 of each of trip switch bridges 21-23.

Thereby, output terminals 18, 19 and 20 of trip switch bridges 21,22 and 23 are positively disconnected from the DC voltages at terminals 26 and 27.

Sequencer 49 then supplies a control signal to bridge series controller 48, causing winding 74 of each of series switches 44,45 and 46 to be deenergized, whereby each contact 73 of all three switches 44-46 is open circuited. Sequencer 49 is then activated to energize power series switch controller 47 in such a manner that the controller 47 supplies an energizing voltage to winding 82 of each of series switches 41-43, whereby contact 81 of each of switches 41-43 is closed. Controller 47, at this time, also supplies a forward bias to the gate electrodes of silicon controlled rectifiers 83 and 84, whereby power from each of terminals 15-17 is applied to each of wings 12-14, respectively.

Sequencer 49 is at this time activated in such a manner as to control phase locked loop 65 to be responsive to the sinusoidal, power line voltage at terminal 15. Phase locked loop 65 compares the frequency and phase of the power line voltage at terminal 15 with control signals generated in controller 31 fortrip switch bridges 21-23. The phase locked loop responds to the frequency and phase difference between the power line voltage and control voltage derived by controller 31 for bridges 21-23, and eventually causes the control voltages for the bridges to become locked in frequency and phase with the frequency and phase of the power line voltages. Phase lock cannot occur until the breakaway torque or motor load 11 has subsided and the motor is running at normal torque because of transients coupled to the power line terminals by load 11.When the control signal for one of the bridges 21-23 is frequency and phase locked with one phase of the power line voltage, all of the remaining control signals for the bridges are frequency and phase locked to the power line frequency and phase. The phase lock is detected by phase lock detector 64 which applies a phase lock indicating signal to sequencer 49.

In response to the phase lock indicating signal, sequencer 49 applies to control signal to controller 48, which causes controller 48 to supply an energizing voltage to winding 74 of series switch 44.

Thereby contact 73 of series switch 44 is closed.

Closure of series switch 44, however, has no effect on the voltage applied to winding 12, because output terminal 18 of trip switch bridge 21 is decoupled from DC power supply terminals 26 and 27 by virtue of the back bias applied by controller 31 to the base electrodes of transistors 35-38 of bridge 21.

After contact 73 of series switch 44 has been closed, sequencer 49 supplies an energizing voltage to positive peak voltage detector 53, responsive to the power line voltage at terminal 15. In response to detector 53 sensing that a positive peak has occurred in the phase of the power line voltage applied to terminal 15, the detector applies an activating signal to sequencer 49, to advance the state of the sequencer so power series switch controller 47 is activated. Controller 47 response to sequencer 49 by supplying a back bias to the gate electrodes of silicon controlled rectifiers 83 and 84 in series switch 41. At the time the back bias is applied to the gate electrodes of the silicon controlled rectifiers, rectifier 84 is in a conducting state and rectifier 83 is cut off, in response to the positive voltage applied to terminal 15.Thereby positive current continues to flow through the anode cathode path of rectifier 84 until the power line voltage at terminal 15 reaches a zero value. In consequence, power line current continues to flow through winding 12 of load 11.

After sequencer 49 has activated controller 47 so that the positive forward bias is removed from the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 41, the sequencer applies an enabling voltage to negative going zero detector 56.

Thereby, detector 56 is able to respond to the negative going zero crossing of the power line voltage applied to terminal 15. In response to detector 56 sensing the negative going, zero crossing of the power line voltage applied to terminal 15, the detector derives an output signal that is applied to sequencer 49. In response to the output signal of detector 56, sequencer 49 supplies a control signal to trip switch bridge controller 31, to cause the trip switch bridge transistors to be activated by the control signal of controller 31. Because frequency and phase lock has been achieved between the power line voltage at terminal 15 and the control signal for bridge 21, the first negative notch, Figure 3, is initially applied by the bridge to terminal 18.The negative notch is coupled through series switch 44 to winding 12, to the exclusion of the negative sinusoidal wave at power line terminal 15. Current resulting from the negative notch flows through winding 12towindings 13 and 14, thence through series switches 42 and 43 to terminals 16 and 17. The pseudo-sinusoidal waveform at terminal 18 is coupled to terminals 16 and 17 for 120 degrees of the power line frequency. There are very few transients between the power line and pseudo-sinusoidal waveforms during the swltch-over period because of the frequency and phase lock which has been achieved between them and because of the notched, multi-level, variable duration nature of ths pseudosinusoidal waveform.

Sequencer 49, after having activated trip switch bridge controller 31 to energize trip switch bridge 21 to cause the first negative notch in the waveform of Figure 3 to be derived, supplies a control signal to power switch controller 47. In response to this control signal, controller 47 removes the energizing voltage from winding 82 of series switch 41, to cause contact 81 of switch 41 to be open circuited. Thereby, the power line voltage at terminal 15 is removed from winding 12.

After the transfer of power from terminal 15 to terminal 18forwinding 12 had been accomplished, power is similarly transferred from power line terminal 16 to trip switch bridge output terminal 19 for winding 13. The sequence involves closing contact 71 in the series switch, detecting the peak positive voltage at terminal 16, removing the forward bias applied to the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 42, detecting a negative going zero crossing at terminal 16, activating trip switch bridge 22 so the first negative notch is derived therefrom and opening contact 81 of series switch 42. After contact 81 of series switch 42 has been opened, the sequence is repeated for switches 43 and 46 in response to output signals of detectors 55 and 58.

After contact 81 of series switch 46 has been opened, sequencer 49 is energized so that phase locked loop 65 becomes responsive to the three phase output of variable frequency oscillator 32, instead of to the power line voltages at terminals 15-17. Simultaneously, sequencer 49 supplies a signal to a suitable controller which enables the frequency of oscillator 32 to be varied. The frequency variations of oscillator 32 enable the speed of motor 11 to be controlled.

The operation of the system will now be considered in response to closure of reverse transfer switch 52. In response to closure of switch 52, sequencer 49 activates phase locked loop 65 so that the phase locked loop becomes responsive to the power line voltage at terminal 15, instead of the three phase output of variable frequency oscillator 32. Phase locked loop 65 activates trip switch bridge controller 31 to cause the frequency and phase of the pseudo-sinusoidal voltages derived at terminal 18, 19 and 20 to be frequency and phase locked to the power line voltages at terminals 15-17. When phase and frequency lock between the voltages at terminals 18-20 and 15-17 has been achieved, phase lock detector 64 derives a signal which is applied to sequencer 49.Sequencer 49 responds to the output of phase lock detector 64 by supplying an activating signal to power series switch controller 47. Power series switch controller 47 responds to the signal from sequencer 49 to apply an energizing voltage to winding 82 of each of series switches 41,42 and 43, whereby contacts 81 of all three series switches are closed. Power continues to be applied to load 11 exclusively by the pseudo-sinusoidal sources at terminals 18,19 and 20, at this time, because the gate electrodes of silicon controlled rectifiers 83 and 84 of series switches 41-43 have not been forward biased.

Sequencer 49 is then activated to enable negative going zero crossing detector 56. In response to detector 56 sensing a negative going zero value in the power line voltage applied to terminal 15, sequencer 49 is energized to supply a control voltage to power series switch controller 47. Controller 47 responds to this voltage to apply a forward bias voltage to the gate electrodes of the silicon controlled rectifiers 83 and 84 of series switch 41. Because zero voltage is, at this time, applied across the anode and cathode of silicon controlled rectifiers 84, substantial current does not immediately ffow through either of the rectifiers. Because of the frequency and phase locked condition between the power line sinusoidal voltage at terminal 15 and the pseudosinusoidal voltage at terminal 18, the voltage at terminal 18 is also zero at this time.The voltage at terminal 18 is zero at this time because all of switches 35-38 of trip switch bridge 21 are in a cut-off condition in response to the control voltage applied thereto by trip switch bridge controller 31.

After elapse of a relatively small fraction of a cycle of the AC power line frequency applied to terminal 15, e.g., 0.12% of a cycle, sequencer 49 is advanced to a state whereby it commands controller 31 to back bias the base electrodes of transistors 35-38. Thereby, the voltage at terminal 18 is decoupled from the DC voltages at terminals 26 and 27 and the pseudosinusoidal voltage is no longer applied to terminal 18 and winding 12. Sequencer 49 is then activated so that controller 48 is supplied with a de-energizing voltage for winding 72 of series switch 44. Contact 71 of series switch 44 then opens, to decouple winding 12 from the DC voltages applied by terminals 26 and 27 to bridge 21.

Series switches 42 and 45 are then controlled by sequencer 49 in a manner similar two that described in connection with series switches 41 and 44. In particular, zero crossing detector 57 is activated, forward bias is applied to the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 42, transistors 35-38 of trip switch bridge 22 are cut off, and contact 71 of series switch 45 is open circuited. After contact 71 of series switch 45 has been open circuited, the same sequence is repeated for series switches 43 and 46 and the transistors of trip switch bridge 23 remain activated to a cut-off condition after a negative going zero crossing of the power line voltage applied to terminal 17 has been sensed by detector 58.

From the foregoing it should be apparent that in certain situations series switches 44,45 and 46 are not necessary. In particular, if it is assured that switching transistors 35-38 of trip switch bridges 21-23 can be positively activated and deactivated in the manner described, the need for the series switches can be avoided. In other embodiments, as illustrated in Figures 5 and 6, terminals 18-20 are not positively decoupled from terminals 26 and 27, and trip switch bridges 21-23 are continuously energized by control signals from controller 31.

Consideration is now given to the manner in which the system operates with series switches 44-46 having the configuration illustrated in Figure 5 and the series switches 41-43 having the configuration illustrated in Figure 7. The same operating sequence applies to the switch of Figure 6.

In response to closure of motor start switch 51, sequencer 49 is activated so that a signel is applied to bridge series switch controller 48. Controller 48 responds to the signal from sequencer 49 to back bias the gate electrodes of silicon controlled rectifiers 75 and 76 in each of series switches 44-46.

Sequencer 49 then supplies power series switch controller 47 with an input signal. Controller 47 responds to the signal from sequencer 49 to supply an energizing voltage to winding 82 of each of series switches 41-43, whereby contact 81 in each of the eries switches is closed. Controller 47 also responds to the signal from sequencer 49 to apply forward bias voltage to the gate electrodes of silicon controlled rectifiers 83 and 84 in each of series switches 41-43. Thereby, load windings 12, 13 and 14 are supplied with power from the three phase, sinusoidal power line source connected to terminals 15-17, to the exclusion of the pseudo-sinusoidal voltages applied by bridges 21-23 to terminals 18-20.

With power being supplied by terminal 15-17 to load 11, sequencer 49 activates phase locked loop 65 so that it is responsive to the power line voltage at terminal 15. When the transients of load 11 associated with the large, initial breakaway torque have subside, frequency and phase lock between the voltages at terminals 15-17 and control signals generated by controller 31 is achieved.

In response to frequency and phase lock between the voltage at terminal 17 and a control voltage generated by controller 31 for bridge 23 being achieved, as indicated by an output signal of phase lock detector 64, sequencer 49 is activated to enable an orderly transfer of power from terminals 15-17 to terminals 18-20. In particular, the signal from phase lock detector 64 activates sequencer 49 so that positive peak voltage detector 53 is enabled. In response to detector 53 sensing that the voltage at terminal 15 has a positive peak value, the detector supplies a signal to sequencer 49. Sequencer 49 responds to the signal from detector 53 by supplying a control signal to power series switch controller 47.

Controller 47 responds to the signal from sequencer 49 by removing the forward bias for the gate electrodes of silicon controlled rectifiers 83 and 84 in series switch 41. At this time, rectifier 83 is not conducting because a negative voltage is being applied to the anode of silicon controlled rectifier 84.

The positive voltage continues to be coupled through rectifier 84 to winding 12 until a negative going zero crossing of the voltage at terminal 15 occurs. The negative going zero crossing of the voltage at terminal 15 is sensed by detector 56, which is enabled by the sequencer after the sequencer has supplied controller 47 with a signal causing removal of the forward bias from the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 41.

In response to the negative going zero crossing of the voltage at terminal 15 being sensed by detector 56, sequencer 49 is activated so that a control voltage is applied to bridge series switch controller 48. Controller 48 responds to the voltage applied to it by sequencer 49 by applying a forward bias to the gate electrodes of silicon controlled rectifiers 75 and 76 in series switch 44. Because of the frequency and phase lock between the operation of bridge 41 and the power line voltage applied to terminal 15, at this time bridge 21 is activated by controller 31 so that the next transition derived from it is the first negative notch in the waveform of Figure 3.Thereby, there is a smooth transition in the waveform applied to winding 12 as the winding is decoupled from terminal 15 in response to opening of series switch 41 and coupled of the winding to terminal 18 in response to closure of switch 44.

After forward bias has been applied to the gate electrodes in silicon controlled rectifiers 75 and 76 in series switch 44, the previously described cycle is repeated for series switch 42 and 45. In particular, the peak value of the voltage applied to terminal 16 is detected, forward bias is removed from the gate electrodes of silicon controlled rectifiers 83 and 84 in series switch 42, the negative going zero crossing of the voltage at terminal 16 is detected and then forward bias is applied to the gate electrodes of silicon controlled rectifiers 75 and 76 of series switch 45. The same sequence is then followed for control of series switches 43 and 46 to provide synchronized switching of power from terminal 17 to terminal 20.

After forward bias has been applied to the gate electrodes of silicon controlled rectifiers 75 and 76 of series switch 46, lower impedance connections are established between load 11 and terminals 18-20 and a more positive break is established between the windings and terminals 15-17. To this end, sequencer49 is activated after the application of forward bias to the gate electrodes of silicon controlled rectifiers 75 and 76 of series switch 46 to cause a control signal to be applied to switch controller 48.

Switch controller 48 responds to the signal from sequencer 49 to activate winding 74 of each of series switches 44-46 whereby contact 73 of each of the series switches is closed. Thereafter, sequencer 49 supplies a signal to power series switch controller 47. Controller 47 responds to the signal from sequencer 49 by removing the energizing voltage of winding 82 of each of series switches 41-43, whereby contact 81 of each of the series switches is opened.

After windings 82 have been de-energized, sequencer 49 is activated so that phase locked loop 65' becomes responsive to the output of three phase variable frequency oscillator 32, to the exclusion of the voltage at terminal 15. With phase locked loop 65 responsive to the output of oscillator 32, variations in the frequency of the oscillator are reflected in changes in the speed of motor 11.

Consideration is now given to the operations performed by the system, including the switches of Figures 5 and 7, when it is desired to change the operation of motor 11 from variable frequency and speed to a fixed speed situation, determined by the power line frequency. Such operations are performed in response to closure of reverse transfer switch 52. Sequencer 49 responds to closure of switch 52 by supplying a signal to bridge series switch controller 48. Controller 48 responds to the signal from sequencer 49 to supply forward bias to the gate electrodes of silicon controlled rectifiers 75 and 76 of each of series switches 44-46. Sequence 49 is then activated to supply a control signal to phase locked loop 65.Phase locked loop 65 responds to the control signal from sequencer 49 so that the phase locked loop responds to the power line voltage at terminal 15, to the exclusion of the output of variable frequency oscillator 32. When frequency and phase lock has been achieved between the power line voltage at terminal 15 and the operation of trip switch 21-23, phase lock detector 64 supplies an enable signal to sequencer 49. Sequencer 49 responds to the enable signal from detector 64 by supplying a control signal to bridge series switch controller 48. Controller 48 responds to the signal from sequencer 49 by removing the energizing voltage for winding 74 of each of series switches 44-46, whereby contact 73 of each of switches 44-46 is open circuited. Sequencer 49 is then activated so that a control signal is applied to power series switch controller 47.Controller 47 responds to the signal from sequencer 49 by supplying an energizing voltage to winding 82 of each of series switches 41-43, whereby contact 81 of each of switches 41-43 is closed.

The system is now in a condition to provide for an orderly transfer of power from the pseudosinusoidal waveforms at terminals 18-20 to the sinusoidal power line voltages applied to terminals 15-17. To this end, sequencer 49 is now activated so that an enable voltage is applied to positive peak current detector 61, responsive to the current supplied by terminal 18 to winding 12. In response to the current supplied by terminal 18 to winding 12 having a positive peak value, detector 61 supplies a control signal to sequencer 49. Sequencer 49 responds to the signal from detector 61 by supplying a signal to bridge series switch controller 48. Controller 48 responds to the signal from sequencer 49 by remov ing the forward bias applied to the gate electrodes of silicon controlled rectifiers 75 and 76 of series switch 44.At this time, the anode cathode path of rectifier 75 is back biased by the positive voltage at terminal 18, but the anode cathode path of rectifier 76 is forward biased. Current thus continues to flow through the anode cathode path of rectifier 76 until the current at terminal 18 drops to a zero value.

Thereafter, current is no longer supplied by terminal 18 to winding 12.

There is, however, no discontinuity in the current flowing through winding 12, because the winding now becomes connected to the power line voltage at terminal 15. To this end, sequencer 49 enables detector 56 after the forward bias has been removed from the gate electrodes of silicon controlled rectifiers 75 and 76 of series switch 44. In response to the power line voltage at terminal 15 having a negative going zero value, detector 56 derives a signal which is applied to sequencer 49. Sequencer 49 responds to the signal derived from detector 56 by supplying power series switch controller 47 with a signal.

Controller 47 responds to the signal from sequencer 49 by supplying a forward bias voltage to the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 41. The forward bias applied to the gate electrodes of rectifiers 83 and 94 in which 41 is thus synchronized with the removal of forward bias from rectifiers 75 and 76 of series switch 44. Because the transition in forward bias from switch 44 to switch 41 occurs in synchronism with zero crossing of the frequency and phase locked voltages at terminals 15 and 18, there is a smooth transition from the pseudo-sinusoidal voltage at terminal 18 to the sinusoidal power line voltage at terminal 15.

After forward bias has been applied to the gate electrodes of rectifiers 83 and 84 in series switch 41, the cycle is repeated for switches 42 and 45. In particular, detedtor 62 senses a peak positive current at terminal 19 of bridge 22, after which the forward bias is removed from the gate electrodes of silicon controlled rectifiers 75 and 76 in switch 45. This operation is followed by detector 57 sensing a negative going zero crossing of the voltate at terminal 16, which in turn is followed by forward biasing the gate electrodes of silicon controlled rectifiers 83 and 84 of series switch 42. This sequence is then repeated for switches 42 and 46 in response to signals derived by detectors 55, 58 and 63. After forward bias has been applied to the gate electrodes of rectifiers 83 and 84 of switch 43, the reverse transfer operation has been completed. Load 11 remains responsive to the fixed frequency power line voltage applied to terminals 15-17 until motor start switch 51 is again closed.

While there have been described and illustrated several specific embodiments of the invention, it will be clear that variations in the details of the embodiments specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims (24)

1. Apparatus for controlling the application of power to an N phase load comprising N phase power line terminals, where N is an integer greater than two, first switch means for selectively applying current from phase K of the power line terminals to phase Kofthe load, where K = 1,2...N, AC to DC to AC switching converter means responsive to the power line terminals for selectively deriving N phase pseudo-sinusoidal power at N output terminals, means for applying the power to output terminal K to phase K of the load, means for synchronizing the switching converter means with the power at the power line terminals so that a control signl for phase K of the pseudo-sinusoidal power is phase and frequency locked to phase Kofthe power line terminal, and means responsive to a phase and frequency lock between the pseudo-sinusoidal and the power line powers for controlling the first switching means and the applications of the pseudosinusoidal power to the N output terminals so that there is synchronized switching to phase Kofthe load between the power line current at phase K and current from the pseudo-sinusoidal power at phase K.

2. The apparatus of claim 1 wherein the converter includes for phase K a plurality of switching elements series connected between DC power supo- lyterminals and the output terminal for phase K, said controlling means maintaining all of the series switching elements for phase K in an open circuit condition except while phase K pseudo-sinusoidal power is applied to phase K of the load.

3. The apparatus of the claim 2 wherein the means for controlling includes for phase K a switch in series between a load terminal for phase K and a phase K converter terminal to which the switching elements of phase K supply the pseudo-sinusoidal power of phase K, said controlling means including means for maintaining the switch of phase K (a) open while power is being applied to phase K of the load by power line terminal K and (b) closed while pseudo-sinusoidal power is applied by the switching elements of phase Kto the phase K converter terminal.

4. The apparatus of claim 2 wherein the controlling means further includes means for opening and closing the first switch for phase K and for initiating and terminating operation of the switching elements of phase K while the voltage at the power line terminal for phase K is substantially zero after the frequency and phase lock has occurred.

5. The apparatus of claim 1 wherein the means for controlling the application of pseudo-sinusoidal power from phase Kto phase K of the load includes a bilateral silicon controlled rectifier switch in series between phase K of the load and the output terminal for phase K, and means for selectively applying and removing forward bias to and from control electrode means of the bilateral silicon switch.

6. The apparatus of claim 5 wherein the means for applying for phase K includes means for sensing a zero crossing of the voltage at the power line terminal of phase K which occurs after the frequency and phase lock has occurred and simultaneously with opening of the first switch means for phase K.

7. The apparatus of claim 5 wherein the means for removing for phase K includes means for sensing a predetermined non-zero current supplied by the output terminal of phase Kto phase Kofthe load after the frequency and phase lock has occurred, whereby current continues to flow through the silicon controlled rectifier switch until the next zero crossing of the voltage at the power line terminal of phase K occurs, and means for activating the first switch means for phase K in response to said next zero crossing.

8. The apparatus of any of claims 5 to 7 including a relay contact in parallel with the bilateral silicon controlled rectifier switch of phase K, and means for closing all of the relay contacts after all of the bilateral silicon controlled rectifier switches have been forward biased and all of the first switch means have been effectively opened.

9. The apparatus of claim 1 wherein the means for controlling the application of pseudo-sinusoidal power from phase Kto phase K of the load includes a second switch in series between phase K of the load and the output terminal for phase K, and means for effectively closing and opening the first switch means for phase K substantially simultaneously with opening and closing of the second switch for phase K, respectively, the first switch means and second switch for phase K being effectively opened and closed after the frequency and phase lock has occurred so that there is substantially no break in the currents supplied to phase Kofthe load bythe power line and output terminals of phase K.

10. The apparatus of claim 9 wherein the means for controlling includes means for effectively closing and opening the first switch means and second switch for phase K when no currents flow through them.

11. The apparatus of claim 1 wherein the first switch means for phase K includes a bilateral silicon controlled rectifier switch in series between phase K of the load and the power line terminal for phase K and means for selectively applying and removing forward bias to and from control electrodes means for the bilateral silicon switch.

12. The apparatus of claim 11 wherein the means for applying for phase K includes means for sensing a zero crossing of the voltage at the power line terminal of phase K which occurs after the frequency and phase lock has occurred and simultaneously with the removal of pseudo-sinusoidal power of phase K from phase K of the load.

13. The apparatus of claim 11 wherein the means for removing for phase K includes means for sensing a predetermined non-zero current supplied by the power line terminal of phase Kto phase Kofthe load after the frequency and phase lock has occurred, whereby current continues to flow through the silicon controlled rectifier switch until the next zero crossing of the voltage at the power line terminal of phase K occurs and means for applying the pseudosinusoidal power of phase K to phase K of the load in response to said next zero crossing.

14. The apparatus of any of claims 11 to 13 including a relay contact in series with the bilateral silicon controlled rectifier switch of phase K, and means for closing all of the relay contacts before any of the bilateral silicon controlled rectifier switches are forward biased and for opening all of the relay contacts after all of the silicon controlled rectifier switches have been back biased.

15. The apparatus of claim 1 wherein the means for controlling the application of pseudo-sinusoidal power from phase Kto phase K of the load includes a first bilateral silicon controlled rectifier switch in series between phase K of the load and the output terminal for phase K, means for selectively applying and removing forward bias to and from control electrode means of the first bilateral silicon switch, the first switch means for phase K including a second bilateral silicon controlled rectifier switch in series between phase K of the load and the power line terminal for phase K, and means for selectiveiy applying and removing forward bias to and from control electrode means for the second bilateral silicon switch.

16. The apparatus of claim 15 wherein the means for applying for the first bilateral silicon controlled rectifier switch for phase K includes means for sensing a zero crossing of the voltage at the power line terminal of phase K which occurs after the frequency and phase lock has occurred and simuS- taneously with opening of the first switch for phase K, the means for applying for the second bilateral controlled rectifier switch for phase K including means for sensing a zero crossing of the voltage at the power line terminal of phase K which occurs after the frequency and phase lock has occurred and simultaneously with the removal of pseudosinusoidal power of phase K from phase Kofthe load.

17. The apparatus of claim 15 wherein the means for removing for the first bilateral silicon controlled rectifier switch for phase K includes means for sensing a predetermined non-zero current supplied by the output terminal of phase Kto phase K of the load after the frequency and phase lock has occurred, whereby current continues to flow through the first silicon controlled rectifier switch until the next zero crossing of the voltage at the power line terminal of phase K occurs, means for activating the first switch means for phase K in response to said next zero crossing, the means for removing for the second bilateral silicon controlled rectifier switch for phase K including means for sensing a predetermined non-zero current supplied by the power line terminal of phase Kto phase Kofthe load after the frequency and phase lock has occurred, whereby current continues to flow through the second silicon control led rectifier switch until the next zero crossing of the voltage at the power line terminal of phase K occurs, and means for applying the pseudosinusoidal power of phase K to phase K of the load in response to said next zero crossing.

18. The apparatus of any of claims 5 to 17 including a first relay contact in parallel with the first bilateral silicon controlled rectifier switch of phase K, and means for closing all of the first relay contacts after all of the first bilateral silicon controlled rectifier switches have been forward biased and all of the first switches have been effectively opened, a second relay contact in series with the second bilateral silicon controlled rectifier switch of phase K, and means for closing all of the second relay contacts before any of the second bilateral silicon controlled rectifier switches are forward biased and for opening all of the second relay contacts after all of the silicon controlled rectifier switches have been back biased.

19. The apparatus of any of claims 1 to 7 or 9 to 13 wherein the means for controlling includes means for activating the first switching means and the application of the pseudo-sinusoidal power to the different phases of the load in sequence.

20. The apparatus of any of claims 1 to 7 or 9 to 13 wherein the means for controlling includes means for activating the first switching means and the application of the pseudo-sinusoidal power to the different phases of the load in sequence so that for each phase K the current through the first switching means has the same amplitude at the time power from power line terminal K is decoupled from load phase K and the pseudo-sinusoidal current initially applied to phase K of the load has the same amplitude, substantially equal to the current ampli tude through the first switching means at the time of decoupling.

21. The apparatus of any of claims 1 to 7 or 9 to 13 wherein the means for controlling includes means for activating the first switching means and the application of the pseudo-sinusoidal power to the different phases of the load in sequence so that for each phase K the current through the first switching means has a zero amplitude at the time power for power line terminal K is decoupled from load phase K and the pseudo-sinusoidal current initially applied for each load phase K has a zero amplitude.

22. The apparatus of any of claims 1 to 7 or 9 to 13 wherein the means for controlling includes means for activating the first switching means and the application of the pseudo-sinusoidal power to the different phases of the load in sequence so that the pseudo-sinusoidal current for phase K at the time it is decoupled from phase K of the load has substantially the same amplitude as the current supplied by the power line terminal for phase K to phase Kofthe load immediately after decoupling of the pseudo-sinusoidal current for phase K from phase Kofthe load.

23. The apparatus of any of claims 1 to 7 or 9 to 13 wherein the means for controlling includes means for activating the first switching means and the application of the pseudo-sinusoidal power to the different phases of the load in sequence so that the pseudo-sinusoidal current for phase K at the time it is decoupled from phase K of the load and the current supplied by the power line terminal for phase Kto phase K of the load immediately after decoupling of the pseudo-sinusoidal current for phase K from phase K of the load have zero amplitude.

24. Apparatus for controlling the application of power to an N phase load according to claim 1 substantially as hereinbefore described with reference to the drawings.