GB2071892A - Production codes on articles - Google Patents

Abstract

A glass container having moulded on the base thereof, incorporated in the base stippling (2), a production code indicative of the mould cavity number. The code is in n binary bits constituted by a series of n sequential groups, each group relating to a different bit in the code, each group containing two marks having no significance to the value of the group bit and either a further mark substantially equally spaced from the two marks or a gap, depending on the value of the group bit (1 or 0 respectively). As illustrated in Figure 1, reading clockwise, the first and last 5 marks are ordinary stipple marks. Ignoring these and reading 0 for a gap, 1 for a mark gives: (010)11(0)11(1)11(0)11(1)11(1)11(0)11(0). (010) is a start read flag and the 7-bit code, from the values in the other parentheses, is 0101100 (least significant bit to the left). This equals mould cavity 26. <IMAGE>

Description

SPECIFICATION Production codes on articles This invention relates to production codes appearing on articles, such as on glass bottles.

Many articles of commerce are produced on machines, several of which may be working in parallel and supplying their products onto a common production line. These machines may on occasion develop defects and provide products with faults onto the production line. Since these machines often work at high speed, a large number of faulty products may be on the production line, divorced from the defective machine, before the latter is remedied. In the past much manual labour has been employed to inspect products on such lines and to remove the faulty articles.

As industry becomes more sophisticated, products are now often coded with various marks to enable the machine on which they were produced to be readily-identified. Apparatus has been developed in some industries for automatically reading these codes to enable corrective action over faults to be speedily taken.

An example is the production of glass bottles, where a large number of glass bottle moulding machines are simultaneously supplying moulded bottles onto a conveyor which subsequently transports them to a lehr for annealing. It is common practice to mark the moulds in some manner so that the bottles they produce are unique - typically each mould cavity includes an area which moulds a cavity, or mould number onto the bottle base. This number (or other code if employed) is normally provided as a marking on the bottle base which is in addition to the normal ring of stippling present around the periphery of the base of such bottles.

Cavity numbers can be coded onto the base of glass containers by incorporating the code in the stippling itself. For example, using a binary notation, the presence of a stippling mark may be interpreted as a "1" and the absence of such a mark (from a position where one would otherwise expect such a mark to be) as a "0", and a code built up in this fashion.

It is not easy to read such codes automatically without error and at a speed compatible with the container-forming production line. Reading is typically accompiished electro-optically, and normally requires relative movement of the container and an elecro-optical detector (e.g. a phototransistor) so that the detector scans the code whereafter the results of the scan are processed electronically and decoded to provide the decimal cavity number.

One difficulty with such systems is the need to provide a reference clock which can be employed to determine whether or not, at any instant in time, a stippling mark ought to be expected. Any error in the clock generation leads to faulty code detection.

The present invention is concerned with an improved form of production code for use on articles such as glass containers which minimises the chance of faulty code detection arising, inter alia, from faulty reference clock generation.

According to the invention there is provided an article bearing an n-bit production code thereon, said n-bit code being constituted by a series of sequential marks which may be arranged into n sequential groups, each group relating to a different bit in the code, each group containing at least two marks having no significance to the value of the bit to which it relates and either a further mark substantially equispaced from said at last two marks or a gap, depending on the value of the bit associated with that group.

Preferably the code is surrounded at either end by code start and code finish flags which may be provided by unique combinations of marks not found elsewhere in the code.

Preferably the article is a glass container and the code incorporated in the stippling on the container base.

Such a code may be read by the apparatus described in our earlier Application No. 8008479 which comprises light beam detection means responsive to light from a source of illumination and which has been reflected or refracted from a production code on an article, means responsive to the light beam detection means for providing a code signal each time the light intensity detected exceeds a predetermined level, reference clock generation means, means for storing an indication whether or not a code signal has been detected within a predetermined period of time provided by said reference clock generation means, means for resetting the reference clock generation means in the event of a code signal being so detected, means for receiving and decoding a proportion of said indications to provide a representation of said production code, and means for enabling said receiving means to receive and decode said proportion only when a different proportion of said stored indications satisfies a predetermined logical combination.

Preferably the light beam detection means is a linear photodiode array camera arranged to scan an area of the article on which the code marks have been placed. Relative movement is provided between the code marks and the camera (e.g. by rotating the article or camera), and the motionproducing mechanism employed to generate the reference clock for use in decoding the code marks correctly. The reference clock is reset to zero each time a code mark is positively detected by the camera and this prevents any clock errors from accumulating.

Preferred features of the invention will now be described with reference to the accompanying drawings, given by way of example, wherein: Figure 1 illustrates the base of a glass container wherein the stippling includes a binary mould cavity number therein, and Figures 2 to 4 are schematic diagrams of an apparatus which may be employed to detect and decode the type of production code illustrated in Figure 1.

Referring to Figure 1, the base of a glass container is illustrated with a seven bit binary code 0011010 incorporated in the stippling 2, corresponding to decimal 26 and hence to the information that this container originated from mould cavity no.26 in the container-forming machine. Only stippling on the right-hand half of the base (as viewed) has been shown. The code is read as follows. Consider the base of the container to be divided into successive identical sectors. If a stipple mark is present in a sector at the circumference then read "1", but if a stipple mark is absent, read "0". In other words, for each of the equispaced stipple marks a "1" may be read and a "0" interjected at each of the gaps such as at G.Thus, reading the code clockwise from 12 o'clock provides the following sequence: 1111101011011111011111111011011111 The first and last five "1's may be ignored as ordinary stipple marks not being part of the seven bit code. The 010 combination is a start code read flag since it is arranged that this combination is unique within the stipple markings. After the 010 combination every third bit is selected to construct the seven bit code. Moreover, to read a code validly, it is mandatory that the two bits between each selected third bit be "11". The seven bit code is read with least significant bit first.Thus, representing the above code by excluding the first and last five "1's and placing the start code read flag and the seven bit code itself in parentheses provides: (010)11(0)11(1)11(0)11(1)11(1)11(0)11(0) Assembling this seven bit code in the usual binary notation with the least significant bit to the right provides 0011010, i.e. decimal 26.

The apparatus employed to detect and decode codes such as just described is shown schematically in Figure 2 whereas the relevant electronic circuitry is illustrated in Figures 3 and 4.

Referring to Figure 2, each container to be inspected is passed through a detecting and decoding station where it rests upon a support plate 4 provided with a slit 6 which is obliquely illuminated from below with light from a light source 8. A line scan photodiode array camera 10 (obtainable from Integrated Photomatrix Ltd Dorchester, Dorset) views vertically down through the neck of the container and is focussed upon the base of the latter.

In the absence of stippling marks, the camera 10 will view a low level of light intensity, but stippling marks will refract light from source 8 vertically upwards so that the stippling marks will be seen by the camera as bright areas of refracted light.

At the detecting and decoding station each container is rotated through 360D (for example by contrarotating belts). Although the specific rotating means have been omitted from Figure 2 for clarity, the motor driving the rotating means is shown schematically at 12 and the speed of rotation of its drive shaft 14 is electronically monitored by means of a shaft encoder 16.

The camera 10 includes a linear array of 128 photodiodes which are sequentially scanned at high speed. The camera provides a number of output signals: a start scan pulse signal SS (a pulse being supplied each time a scan of the 128 photodiodes commences), a clock pulse signal CK (synchronous with the scanning of each photodiode), and a video output signal. The video output signal is an analog signal representative of the light intensity received by the scanned (sequentially interrogated) photodiodes. This analog signal is converted to digital form by comparing it to a preset level in a level detector, so providing "on" signals above the level and "off" signals below the level. These onloff signals are termed herein squared video signals AV.

The level detector is set to provide "off" signals in the absence of refracted light from stippling marks being seen by the camera. An "on" signal thus indicates that the relevant photodiode is viewing refracted light from a stippling mark, In processing the camera outputs to detect and decode the code in the stippling, a number of parameters are preset in the electronic circuitry.

Referring to Figure 1, the field of view for the linear array of 128 photodiodes may be represented as extending along the slit 6 between the numbers 1 and 128. A large number of these photodiodes are redundant for code detecting and decoding since only those within the window area W need be employed. A first parameter which is chosen in the electronic circuitry is the uppermost and lowermost (in number) out of the 128 possible photodiodes which are to be employed.

A second parameter which is present is the number of adjacent (i.e. consecutive) photodiodes in the window which, in any one scan, must sense a high light intensity (AV high) to satisfy the criterion that a true stippling mark has been seen. For example, a minor blemish on the container base may cause a light spot on, say, one or two photodiodes which one would not wish determined as a stippling mark. Thus, one selects the minimum number of photodiodes selcted from those within the window which must have AV high before actuating a "stippling present" signal. This parameter essentially sets the distance along the slit for which AV must be high to actuate the "stippling present" signal.

A third preset parameter is the number of consecutive scans of the photodiode array for which the "stippling present" signal must exist. The parameter is also a means of avoiding minor blemishes being sensed as stippling marks and essentially sets the minimum time for which AV must be high within the window before being decoded as a stippling mark.

The electronic circuitry employed to process the outputs of the camera 10 is illustrated in Figure 3, where only the more important components are illustrated for clarity. A pair of thumbwheel stores 20 are preset with the sequence number of the lowermost and uppermost diodes in the array of 128 which are to be employed for code detection. This is the first parameter described above and, in the example given, setting numbers 10 and 20 in the thumbwheel stores will ensure that diodes only from 10 to 20 are employed for code detection.

A continuous series of "1 "s are clocked by the CK signal from camera 10 through a shift register 22 and the latter is cleared by the SS signal from camera 10.

The states of the shift register stages are compared to the numbers held by thumbwheel stores 20, and a pulse output is provided at 24 which commences at the lowermost diode number preset (10 in our example) and terminates at the uppermost number preset (20 in our example).

The pulse from 24 is supplied to an AND gate 26, a a second input of which receives a AV signal from camera 10. AND Gate 26 is connected to a second AND gate 28 which has AV and CK inputs at two other terminals. The output of AND gate 28 is employed to clock a shift register 30 which has a continuous series of "1"s clocked therethrough.

Shift register 20 is cleared by SS signals from camera 10 and the output stages are each compared to a preset number held in thumbwheel store 32.

This latter store is preset with the second parameter described above - the number of consecutive diodes which sense a high light intensity in any one scan before a "stippling present" signal is actuated. The comparison output is stored in a flip-flop 34, which is in the "1" state if the preset number of diodes in any one scan is achieved, but which is otherwise in the "0" state.

A further shift register 36 has a continuous series of"1"s clocked through by the SS signals from camera 10 and is cleared by the Q output of flip-flop 34. The output stages of shift register 36 are compared to a number preset in a thumbwheel store 38. This latter store is preset with the third parameter described above - the number of consecutive scans for which a "stippling present" signal must exist before it is considered to be a true stipple marking.

When a "stippling present" signal is set byflip4lop 34 (Q= 0), shift register 36 advances a "1" for each scan and if this occurs for a sufficient number of scans corresponding to the number preset in thumbwheel store 38 then an output signal is generated which is termed herein the "Decision" signal. The latter is high when the preset number of photo-' diodes within the window W have AV high for the preset number of scans; otherwise it is low. A high "Decision" signal indicates that a stippling mark has been detected by the camera 10.

A further output signal which is generated from the camera output and from the first parameter described above (the window photodiodes) is a "Zero scan pulse" signal. The latter signal is simply a single output pulse which is given whenever AV remains low throughout the scan of the photodiodes in the selected window. Such a pulse arises, therefore, when no photodiode in the selected window has AV high in any one scan.

Referring now to Figure 4, the "Decision" and "Zero scan pulse" signals relevant to the diode array camera are shown functionally as inputs at 62 and 64 respectively. The Decision signal 62 is employed to clear a JK flip4lop 66 whereas th Zero scan pulse signal 64 clocks this flip-flop and also supplies one input to an AND gate 68. The J and K inputs to flip-flop 66 are permanently held high and low, respectively. The second input to AND gate 68 is supplied from the8output of flip-flop 66 which is also connected to the input of a 24 bit serial input/parallel output shift register 70.

The shaft encoder 16 is coupled to the clock input of an 8 bit serial input/parallel output shift register 72, the input stage of which is tied to the positive supply rail. The Q output of flip-flop 66 is connected to the clear input of shift register 72. A single pole switch 74 can take any one of the eight outputs from shift register 72 for supply to an OR gate 76, the other input of which is from the AND gate 68. The output of OR gate 76 is employed to clock shift register 70 and to supply an input to an AND gate 78 which is part of a delay circuit 80 to be described in more detail below.

The 24 stages of shift register 70 are taken either to a seven-way latch 82, a fourteen-input AND gate 84, a two input NOR gate 86 or a two input AND gate 88. The connections are as follows: latch 82 - stages 1,4,7,10,13,16 and 19.

AND gate 84 - stages 2,3,5,6,8,9,11,12,14,15,17,18, 20and21.

NOR gate 86 - stages 22 and 24.

AND gate 88 - stage 23 and the output of NOR gate 86.

The output of AND gate 88 supplies a second input to AND gate 78 and also to a further AND gate 90. A second input to this latter gate is provided from the delay circuit 80. The AND gates 84 and 90 supply inputs to an AND gate 92, whose output enables the seven-way latch 82. The seven outputs of latch 82 are provided to a BCD decoder 94 whose decimal output is employed to drive a digital display 96. The latch 82 outputs are also connected to seven respective light-emitting diodes 98. Finally the delay circuit 80 is clocked from a master oscillator 100.

The circuit shown in Figure 4 functions as follows.

For the purpose of illustration, it will be assumed that a glass container with the coding illustrated in Figure 1 is being scanned by the diode array camera.

The container is thus being rotated clockwise so that the successive stippling marks are illuminated and viewed by the camera. Simultaneously with the provision of the "Decision" and "zero scan pulse" signals from the camera, the shaft encoder 16 is independently providing pulses to clock shift register 72. Assume that the camera is viewing an area of the container base which does not contain stippling, for example at the point "X" in Figure 1.

As the camera rapidly scans at this point X the absence of a video signal at the camera will provide a positive zero scan pulse 64 for each scan of the photodiode array. The absence of stippling will also dictate a low Decision signal 62. Under this circumstance, flip-flop 66 will be clocked on each scan but its high J input will cause the 0 output to remain high and the output of AND gate 68 to remain low (Q being low).

The shaft encoder 16 meanwhile is clocking shift register 72. If it is assumed that the fourth stage of the latter is coupled to OR gate 76 through switch 74, then when the first bit is clocked down to stage 4 by the shaft encoder, the zero on the Q output of flip-flop 66 is clocked into the first stage of shift register 70.

Assume now that the container has rotated so that the stippling mark adjacent X in Figure 1 is just being detected by the camera. In this condition the Zero scan pulse signal 64 is low for each scan since a video signal is now present. Initially the Decision signal 62 remains low since insufficient diodes (of the diode array) for an insufficient number of scans exist activated. Flip-flop 66 remains static but shaft encoder continues to clock shift register 72. When the stipple is fuliy detected by the diode array camera, the Decision signal 62 goes high which clears flip-flop 66. The low state of the 0 output provided at clearance also clears shift register 72 (the latter clears upon a low signal at its clear input).

This situation remains until the stippling mark fully clears the detecting area of the camera as the container is rotated. At this stage, the Decision signal 62 will have returned to a low output, but the Zero scan pulse signal 64 will once more clock flip-flop 66.

The first of these clock pulses, together with the high Q output of flip-flop 66 resulting from its previous clearance by the Decision signal enable AND gate 68 and OR gate 76 to clock a "1" into the shift register 70. The flip-flop 66 changes state causing 0 to revert high, and removes the clearance from shift register 72. This allows the latter to continue clocking bits through its successive stages.

The camera is now viewing the container base at the position Y, between the first two stippling marks.

The Decision signal 62 is low but since the bottle continues to rotate the shaft encoder continues to clock bits through shift register 72. However, before the first bit reaches stage 4, the container will have rotated further to place the second stippling mark within the camera field of view, causing Decision to go high and place another "1" into shift register 70.

It will thus be appreciated that the switch 74 is set to a particular stage of shift register 72 so that normally a bit would not reach that selected stage when there are no gaps in the stippling. If a gap does exist in the stippling (e.g. at G in Figure 1) then the bit does reach the selected stage of shift register 72 and a zero is clocked into shift register 70. The shift register 72/switch 74 combination act as a timesetter for the circuit, within which time to expect a stippling mark to be present.

The circuit operates to place a zero into shift register 70 in the absence of stippling marks, to place a one in the register for each stippling mark, and to place a zero in the register in the presence of a gap in the stippling.

Returning to the code illustrated in Figure 1, once the container has rotated approximately 1500, all 24 bits of the stippling code (including the 010 start code read flag and the mandatory 11 bits between each bit of the seven bit mould cavity code) will be held by shift register 70. The start code read flag will be in stages 22 to 24, and the mandatory "11 "s in those stages leading out to fourteen input AND gate 84. The seven bit mould cavity code will be in those stages leading out to seven-way latch 82.

The 010 start code read flag in stages 22 to 24 enables gates 86 and 88, and provides a high input to gates 78 and 90. This situation will have arisen from the moment the 010 has been clocked down to stages 22 to 24, and the combination of 010 sending AND gate 88 output high together with the clock pulse provided also to AND gate 78 will enable the latter and trigger delay circuit 80. The delay circuit, after a short delay obtained by reference to the fast running master oscillator 100, provides an output pulse to AND gate 90. The second input to AND gate 90 is already high as are all the inputs to AND gate 84. AND gate 92 is thus enabled, and this in turn enables latch 82 so that the seven bit mould cavity code is set in the latter.The purpose of employing the delay circuit 80 to control the timing of code entry into latch 82 is to allow the shift register stages to settle before latch enable.

The seven bit binary code held by latch 82 is decoded by decoder 94 and displayed at 96 as a decimal indication of the cavity number decoded.

Simultaneously the LED's 98 provide a visual display of the binary code held by latch 82.

It will therefore be appreciated that a code is detected and decoded from the container base only if 010 is present in stages 22 to 24 and all of the stages leading to gate 84 contain "1"s. The absence of any one of these conditions will prevent decoding.

This arrangement provides a high degree of security to ensure correct decoding. If desired this security can be increased, for example by extendiny the length of shift register 70 and making it mandatory that the seven bit code is followed by, say,0 or 00.

The stages holding 0 or 00 could provide outputs (after inversion) into AND gate 84.

An advantage of the apparatus as described is that the code is essentially self-clocking. The clock for the code is derived from the shaft encoder, but the clock is effectively reset after each stippling mark is detected or if the shift register 72 provides a high output through switch 74. Any timing errors in generating the clock do not therefore accumulate as the code is being read.

Claims (7)

1. An article bearing an n-bit production code thereon, said n-bit code being constituted by a series of sequential marks which may be arranged into nsequential groups, each group relating to a different bit in the code, each group containing at last two marks having no significance to the value of the bit to which it relates and either a further mark substantially equally spaced from said at least two marks or a gap, depending on the value of the bit associated with that group.

2. An article according to claim 1 wherein the code is provided at one or both ends of the said sequence by a code start flag and/or a code finish flag, which flags are provided by unique combinations of marks not found elsewhere in the code.

3. An article according to claim 1 or 2 when a glass container and wherein the code is incorporated in the stippling on the container base.

4. An article according to any of claims 1 to 3 wherein the code is binary with said further mark representing one of 1 or 0 and said gap representing the other of 1 or0.

5. An article according to claim 4 wherein said at least two marks consist of two marks, one equallyspaced each side of said further mark or gap, as the case may be.

6. An article according to claim 5 wherein a code start flag consisting of a gap, a mark, and a further gap is provided.

7. An article bearing an n-bit production code thereon substantially as herein described with reference to the accompanying drawings.