GB2068696A - Signal discriminating circuit - Google Patents

Abstract

A circuit for discriminating between tone and speech signals applied to a telephone answering machine includes a squaring circuit 1 converting incoming signals into a train of pulses, each having a duration equal to that of the positive-going portion of a corresponding cycle of the signal. A period integrator 3 provides an output voltage whose magnitude increases each time a pulse is applied thereto, by an amount proportional to the duration of the pulse. A threshold detector 13 detects when the output voltage reaches a predetermined value. A period/voltage converter 5 generates a train of pulses each having a voltage Vn representing the period of a corresponding pulse from the squaring circuit. Pulses bVn from attenuator 17 are compared at 15 with previous pulses Vn{1, from sample store 21. If the incoming signal is a speech signal, bVn sometimes falls below Vn{1, and the output of the comparator provides a voltage for resetting the period integrator before the threshold voltage is reached. <IMAGE>

Description

SPECIFICATION Improvements in discriminating circuits This invention relates to circuits for discriminating between alternating electrical signals of constant or substantially constant frequency and signals of varying frequency.

Telephone answering machines are required to sense and act upon tone signals, i.e. alternating electrical signals of constant or substantially constant frequency and amplitude, which are applied to the machine via a telephone line from an exchange or a remote subscriber. Such tone signals have frequencies within the audio range. The machine must therefore include circuits which discriminate between tone signals and speech signals, which have continually varying frequencies within the same range as the tone signals.

It is desirable for the discriminating circuits in a telephone answering machine to be capable of detecting a wide range of tone frequencies and for them to detect tone signals which persist for a few seconds only. The circuits should also be capable of detecting bursts of tone signal which are separated by long periods of silence, 'say greater than 800ms, or by short periods of silence, say less than 200ms.

One kind of discriminator relies for its operation on the periods of silence which occur in speech signals. This kind of circuit cannot be used universally, since some telephone systems employ tone signals accompanied by periods of silence which range from 1 OOms to 1.5 seconds. The discriminator would falsely detect such tone signals as speech.

A second kind of discriminator distinguishes between the continuously varying peak voltages of speech signals and the constant or substantially constant voltage of tone signals. With this kind of circuit, increased complexity is required in the form of an automatic level controller to cope with a wide range of tone signal voltages (approximately 30dB).

This must not distort any of the voltage peaks, and is therefore complex.

Finally, there are circuits which rely on frequency measurements i.e. on counting the number of times that a signal changes polarity within a predetermined interval of time. The count should be constant for a tone signal. However, this kind of circuit has the disadvantage that there is a high probability of successive intervals of time in a speech signal including the same number of polarity changes, in which case a speech signal is wrongly detected as a tone signal.

Integration of many intervals can reduce the error rate, but this extends the total time of the measurement. The circuit is also complex.

According to the present invention, a circuit for discriminating between an alternating electrical signal of constant or substantially constant frequency and a signal of varying frequency comprises means for generating a train of electrical signals each having an electrical parameter whose magnitude represents the time taken by an alternating input signal to undergo a small predetermined number of changes in polarity, means for comparing the magnitudes of the electrical parameters of two signals in the train and for generating an output signal representing a comparison between two signals whose electrical parameters have the same magnitude, and hence are derived from an input signal of constant or substantially constant frequency, or two signals whose electrical parameters have different magnitudes, and hence are derived from an input signal of varying frequency.

Suitably, the circuit further comprises means for generating a first electrical signal having an electrical parameter whose magnitude increases in accordance with the number of cycles of an input signal applied to the circuit, means for generating a predetermined output when the magnitude of the electrical parameter of the first signal reaches a predetermined value, and means for applying the said output signal from the comparing means to the means for generating the predetermined output, whereby the said means for generating the predetermined output is re-set if the said output signal represents two signals within a predetermined period whose electrical parameters have different magnitudes, derived from an input signal of varying frequency.

The circuit may further comprise means for generating a second electrical signal if there is a break in the input signal which persists for a predetermined interval of time, and means for applying the second electrical signal to the means for generating the predetermined output, whereby the said means for generating the predetermined output is re-set.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block schematic drawing of a circuit in accordance with the invention; Figures 2 and 3 show waveforms of electrical signals associated with the circuit of Figure 1; Figure 4 is a modification of the circuit of Figure 1; Figure 5 shows in more detail the circuit of Figure 1; Figure 6 is a further modification of the circuit of Figure land Figure 7 shows in more detail the circuit of Figure 6.

Figure 1 of the drawings is a block schematic drawing of a circuit according to the invention for discriminating between tone and speech signals applied to a telephone answering machine, via a telephone line.

At the input to the circuit of Figure lisa squaring circuit 1 for converting any tone or speech signal on the line into positive-going pulses of square waveform. The square-wave pulses from the squaring circuit 1 are used to drive a period integrator 3, a period/voltage converter 5, a sample enable pulse generator 7, a silence reset delay 9 and a 20ms reset enable delay 11.

The period integrator 3 is adapted to generate an integrated output signal representing the pulses from the squaring circuit 1 applied thereto. A threshold detector 13 is coupled to the output of the period integrator 3.

The period/voltage converter 5, the sample enable pulse generator7 and associated circuits are designed to distinguish between incoming tone and speech signals. To this end an output of the converter 5 is coupled to a non-inverting input of a com parator 15 via an attenuator 17. The output of the converter 5 is also coupled via a sample switch 19 to a sample store 21, whose output is connected to an inverting input of a comparator 15. The sample enable pulse generator7 generates sample pulses for opening the sample switch 19.

An output from the comparator 15 is connected to a first input of an integrator reset gate 21. Connected to a second input of the gate 21 is an output from the reset enable delay 11.

An output from the gate 21 is connected to a first input to a reset gate, which has a second input connected to an output from the silence reset delay 9.

An output from the gate 23 is connected to a resetting input to the period integrator 3.

In use, the squaring circuit 1 at the output to the circuit of Figure 1 converts any tone or speech signal on the telephone line into positive-going pulses of square waveform, each pulse having a duration equal to the duration of the corresponding positivegoing portion of a cycle of the tone or speech signal.

Figure 2(a) shows the voltage waveform of a typical speech signal applied to the circuit and Figure 2(b) shows the resulting square wave pulses from the squaring circuit 1. In Figure 3(a) there is shown the voltage of waveform of bursts of a tone signal of constant or substantially constant signal. At the end of each burstthere is a short "ringing out" period, where the tone signal has a considerably reduced amplitude and lower frequency. Figure 3(b) shows the resulting square wave pulses from the squaring circuit 1. The amplitude ofthe tone signal is below the threshold of the squaring circuit 1 during the "ringing out" period and, as shown in Figure 3(b), there are then no square wave pulses.

The period integrator3 generates an output voltage which increases during each interval of time for which a square wave pulse is applied thereto from the squaring circuit 1. Each increase in voltage from the integrator3 is proportional, or substantially proportional, to the duration of the associated square wave pulse. During the interval of time between each pair of pulses there is an insignificant decrease in the output voltage from the period integrator. In the result,the output voltage of the integ rator3 increases in the manner shown in Figures 1 and 2(e) until it reaches a predetermined threshold voltage or is re-set, as hereinafter described.

If the threshold voltage is reached, the output of the threshold detector 13 is switched from a logic 0 to a logic 1. As hereinafter described, the fact that the output voltage from the integrator 3 has reached the threshold voltage means that the integrator has received from the squaring circuit 1 a large number of successive square wave pulses of the same duration. This in turn means that a tone signal, rather than a speech signal, is present at the input to the squaring circuit 1.

As mentioned above, the period/voltage converter 5, the sample enable pulse generator 7 and associ ated circuits serve to distinguish between incoming tone and speech signals. To this end, the period/voltage converter 5 is adapted to convert each square wave pulse from the squaring circuit 1 into a voltage pulse whose maximum amplitude is proportional to the duration of that pulse. Figure 2(c) shows the voltage pulses from the converter5.

The attenuators 17 gives an output equal to a fraction p (equal to 0.98) of each pulse from the converter 5, and this output is applied to the non-inverting input to the comparator 15. The voltage in the sample store 21 is at any time proportional to the maximum voltage of the last preceding pulse from the converter 5, as shown in Figure 2(d). Accordingly, at the time when the nth pulse from the converter 5 is applied to the non-inverting input to the comparator 15, the voltage in the sample store 21, which is proportional to the maximum magnitude of the (n - 1 )th pulse, is applied to the inverting input. The voltages applied to the comparator 15 are therefore Vn and Vn - 1, whereVn and Vn - 1 are the maximum voltages of the nth and (n - 1) th pulses, respectively.At the output of the comparator there is a logic 0 if the voltage Vn remains less than Vn - 1, which is the case for incoming tone signals. There is a logic 1 at the output of the comparator 5 if the voltage p Vn becomes greater than Vn -1,which occurs if there is a speech signal at the input to the present circuit.

The output of the comparator 5 is applied to the first input to the integrator reset gate 21.

Referring nowto Figure 3(a) of the drawings, contact bounce may result in a fractional period of spurious frequency at the beginning of each burst of a tone signal. It is to avoid detection of this fractional period as a part of a speech signal that the reset enable delay 11 is provided. This delay 11 provides an output voltage, shown in Figure 3(c), which is normally a logic 0 but which is switched to a logic 1 approximately 20ms afterthe beginning of an incoming speech ortone signal. The output voltage from the delay 11 is applied to the second input to the integration reset gate 27.

As long as one of the inputs to the gate 27 is a logic 0,theoutputofthegate is also a logic O. This output is applied to the first input of the reset gate 23, whose output is likewise a logic 0. There is therefore no resetting voltage applied to the period integrator 3.

If more than 20ms have elapsed since the beginning of an incoming tone or speech signal and if there is then a change in the period of that signal so ThatpVn is greaterthan V, -1, both inputs to the integrator reset gate 27 are at a logic 1. This is the situation when there is a speech signal atthe input to the present circuit. It results in the output of the gates 27 and 23 moving to a logic 1 voltage so that a resetting voltage is applied to the period integrator 3. The resetting voltage causes the output of the integrator 3 to fall to zero, and the output of the threshold detector 13 to remain at zero, which is the condition corresponding to detection of an incoming speech signal. The voltages on the sample store 21 when there is an incoming speech signal are shown in Figure 2(d). The resulting output voltages from the integrator 3 are shown in Figure 2(e).

If more than 20ms have elapsed since the begin ning of an incoming signal and the period of that signal remains constant pV is less than Vn - 1 and the outputs of the gates 27 and 23 remain at a logic 0.

This is the situation when there is a tone signal at the input to the circuit. There is then no resetting input applied to the integrator 3 and the output voltage of the integrator increases to a value sufficient to switch the output of the threshold detector 13 to a logic 1.

The silence reset delay 9 gives an output voltage which is normally a logic 0. However, if the incoming signal includes a period of silence which persists for more than 5 secs., the output of the delay 9 is switched to a logic 1. This output is applied to the second input to the reset gate 23, causing the output of the gate to switch to a logic 1 to cause resetting of the integrator 3. Such a period of silence is found in speech signals, not in tone signals.

Figure 5 of the drawings shows in more detail the circuit of Figure 1.

Referring to Figure 5, the squaring circuit 1 includes a high input impedance operational amplifier IC1 (a) which is operated as a comparator. At the in puts to the amplifier IC1 (a) are d.c. biasing resistors R2, R3, R4 and R5, which are arranged to provide a biasing voltage 7.5 volts on the inverting input and a voltage of approximately 7.46 volts (i.e. 43mV more negative) on the non-inverting input. This results in a quiescent output from the amplifier IC1 (a) of 0 volts, which is the negative power rail.

An incoming tone or speech signal is applied via the resistor R1 and the blocking capacitor C1 to the non-inverting input of the amplifier IC1 (a). As soon as a positive-going part of a cycle of the signal exceeds the threshold of 43mV, the output of the amplifier is switched to 15 volts, which is the positive power rail. A portion of this output voltage is fed back via the resistor R6 to the non-inverting input of the amplifier ICl (a), changing the non-inverting threshold voltage to 28mV. This means that the positive-going voltage at the input has to fall below 28mV before the output returns to 0 volts.

These threshold voltages are near to the zero crossing parts of a 300mV peak input tone or audio signal so that the squaring circuit produces positive-going square wave pulses each having a duration equal to the positive-going part of a corresponding cycle of an input signal. The negative going part of each cycle has no effect on the amplifier output.

The period integrator 3 includes a capacitor C6 which is charged via a resistor R20 and a blocking diode D4 during each square wave pulse from the squaring circuit 1. In the interval time between each pulse there is an insignificant discharge of the capacitor C6 via the resistors R19 and R20. Although the time constant of the integrator 3 is 250ms, the charging current is only present for 50% of the time and the time to reach the threshold voltage of the threshold detector 13 is doubled.

The threshold detector 13 has a high input impedance of approximately 20MQ A CMOS gate external to the circuit of Figure 5 is employed.

The resistor R19 serves as the silence reset delay 9 of Figure 1 in that if the output of the squaring circuit 1 remains at 0 volts for, say, 5 secs., the capacitor C6 has sufficient time to discharge via the desistors R19 and R20.

The sample store 21 is a capacitor C5. In the circuit of Figure 5 the capacitor C5 has a value of 0.1,u F, but this is not critical. A restriction on the maximum value of the capacitor C5 is that charge must be transferred to and from it quickly. With the circuit of FigureS, the maximum possible rate of charges is approximately 6,aS per volt. When the sample switch 19 is open, the leakage paths provide a resistance in parallel with the capacitor C5 of approximately 3,500 M ohms. The time constant is approximately 6 minutes.

The period/voltage converter 5 includes a capacitor C2 which is charged via a resistor R7 during each square wave pulse from the squaring circuit 1 and is discharged via the resistor7 and a resistor8 and diode D1 in the intervals between pulses. The voltage developed across the capacitor C2 during each square wave pulse is approximately proportional to the duration of the pulse. The time taken for the capacitor C2 is discharge is considerably shorter than the duration of pulses applied thereto from the squaring circuit 1.

The capacitor C2 is connected to a non-inverting input of a voltage follower lCl (b).

Two resistors R15 and R16 form the attenuator 17 which couples the period/voltage converter 5 to the non-inverting input to the comparator 15. The magnitudes of the resistors 15 and 16 are such that a fraction p equal to 0.98, of the voltage Vn appearing at the output of the voltage follower IC1 (b) is applied to the comparator 15. At the time when this voltage p Vn is applied to the non-inverting input of the comparator 15 the sample switch 19 is closed. The voltage on the capacitor C5 in the sample store 21 is then proportional to the voltage generated by the period/voltage converter 5 during the previous, (n 1 )th pulse i.e., Vn - 1. This voltage Vn - 1 is applied to the inverting input of the comparator 15.

The sample switch 19 is a p.n.p. transistor TR1 which is operated in the forward mode for charging the capacitor 5 in the sample store 21 and in the reverse mode for discharging the capacitor. In the reverse mode, the roles of the emitter and collector ofthetransistorTR1 are interchanged. The large difference between the current gains in the two modes does not affect the performance of the circuit, the important characteristics being the forward and reverse dynamic resistances. With a BC 559 p.n.p.

transistor having an I.B. of 600y A, the forward dynamic resistance is about 40 ohms and the reverse dynamic resistance is about 25 ohms. If the capacitor C5 is 0.1,uF, the time constant is 4yS for charging and 2.5us for discharging. When the transistor TR1 is cut off, the collector leakage current is very small (0.3mA at 6 volts). This represents a resistance of 20,000 M ohms.

The reverse emitter-base breakdown voltage of the transistorTR1 is approximately 5 volts and a blocking diode D3 is connected to the base of the transistor in order to avoid such breakdown. When the transistor TR1 conducts in the forward direction, the voltage then present at the output of the voltage follower lCl (b) is transferred to the capacitor C5.

This transfer takes place during a pulse from the sample enable pulse generator 7.

Included in the pulse generator 7 are biasing resis tors R12 and R13 which apply a d.c. bias of approxi mately 10 volts to the base of the transistor TR1 in the sample switch 19. This bias is sufficient to cut off the transistor in the quiescent condition. A capacitor C4 and a resistor R14 form a differentiator for positive-going square wave pulses from the squar ing circuit 1. A pulse generated by the rising edge of each square wave pulse is shunted by a diode D2 and has no effect on the sample switch 19.A negative-going pulse generated by the falling edge on each square wave pulse is applied to the base of the transistor via the diode D3 and turns on the transistor for the duration of the pulse (S.SiLS). It will be appreciated that this negative-going pulse occurs after the associated square wave pulse from the squaring circuit 1 has terminated, and hence after the voltages p Vn and Vn - 1 have been compared by the comparator 15.

The comparator 15 includes a differential amplifier IC1 (d) for comparing the voltages p Vn and Vn - 1 applied thereto in the manner described above. If the frequency of an incoming signal is constant, as in the case of a tone signal, Vn is equal to Vn -1 and pVn is less than Vn - 1. The output of the amplifier IC1 (d) is then at zero volts. If the frequency of the incoming signal begins to decrease, which is the case during a speech signal, p Vn soon becomes greater than Vn 1. The output of the amplifier IC1 (d) then moves to the voltage of the positive rail. The period/voltage converter 5 has a slope of approximately 550 Cr.S S per volt.To make p Vn greater than Vn - 1, the period needs to change from t to t/ss, i.e. from 2ms to 2ms/.99 = 2.02ms. This represents a frequency change from 500to 495Hz i.e. 5Hz in 2ms or 2.5 KHz per second.

A pair of resistors R17 and R18 and a diode D5 form the integrator reset 27 of Figure 1. A transistor TR2 and resistors R21 and R22 form the reset circuit 23.

Assuming the diode D5 is non-conductive, a positive voltage at the output of the comparator 15 results in a small positive voltage being applied to the base of the transistorTR2. The transistorTR2 then conducts and the capacitor C6 in the period integrator 3 discharges via the resistor R21 and the emitter-collector circuit of the transistor. The period integrator3 is thus reset.

As described above, the reset enable delay 11 ensures that the period integrator 3 can only be reset when an incoming signal has persisted for 25ms.

The delay 11 includes a differential amplifier IC1 (c) having an inverting input which is maintained at about 5 volts by biasing resistors R10 and R11. In the quiescent condition, the non-inverting input is at zero volts. The output of the amplifier IC1 (c) is then at zero volts so thatthe diode D5 conducts and pro vides a shunt across the output from the comparator 15. When a tone signal or speech signal is applied to the circuit, square wave pulses from the squaring circuit 1 are applied via a resistor R9 to a capacitor C3 connected to the non-inverting input to the amplifier IC1 (c). The capacitor C3 begins to charge up and after 20ms the voltage on the capacitor reaches 5 volts.The output of the amplifier then assumes a positive voltage, reverse biasing the diode D5 and removing the shunt from the output of the com parator 15. If a positive voltage subsequentily appears at the output of the comparator 15, a voltage is applied to the transistor TR2 to re-set the period integrator 3 in the manner described above.

In using the circuit described above, the interference signal due to ringing out, shown in Figure 3(a), can be troublesome if a high pass filter precedes the circuit. To overcome this problem the modified circuit of Figure 4 can be employed. In the circuit of Figure 4 a peak detector 29 is provided at the input to the circuit. The detector 29 provides a positive pulse which rastas for an interval of time during which the signal magnitude exceeds a predetermined ratio of the previous peak of positive going cycles of an incoming tone or speech signal. The positive pulse is applied to the integrator reset gate 27, where it enables resetting of the period integrator3. An additional modification to improve discrimination can be made by driving the period integrator from the added peak detector 29.

Figure 6 is a further modification of the circuit of Figure l,this modification being designed to avoid fractional period/relay bounce and ringing out interference.

In the circuit of Figure 6 a pulse rate counting circuit 30 replaces the reset enable delay 11 and the integrator reset gate 27 of Figure 1. This pulse rate counter circuit is made up of a pulse shaper 31, a pulse integrator 33 and athreshold detector35 which are connected between the output of the comparator 15 and the first input to the reset gate 23.

The pulse shaper is designed to give a pulse of predetermined width in response to each pulse at the output ofthe comparator 15. Each ofthe pulses of predetermined width causes an increase in the output voltage of the integrator 33. Finally, the threshold detector 35 gives a logic 1 output to reset the period integrator 3 if the output voltage of the pulse integrator 33 exceeds a predetermined value (say, four) within a predetermined reset period of 500ms.

If a speech signal is applied to the circuit of Figure 6, there will be many pulses (i.e., more than four) swithin the preset period of 500ms. Accordingly, at least one reset output is produced to reset the period integrator in each preset period. If a tone signal is applied to the circuit, the number of fractional periods due to relay bounce and the number of errors due to ringing out at the end of the tone bursts do not exceed fourwithinthe reset period of 500ms.

The period integrator is not therefore reset.

Figure 7 shows in more detail the circuit of Figure 6.

The circuits of Figure 1 to 7 can be formed by a micro processor or microcomputer instead of the discrete circuits shown in Figures 5 and 7.

The circuits can be used to distinguish music sign alps from speech signals.

In the circuits described above the period/voltage converter 5 generates a voltage pulse whose max imum amplitude is proportional to the duration of a pulse from the squaring circuit 1. Each pulse from the squaring circuit has a duration equal to the duration of the positive going portion of a cycle of an incoming tone or speech signal i.e., the interval of time between one change in polarity of the incoming signal and the next succeeding change in polarity.

The circuit can be modified to produce pulses each of which has a duration equal to the time between one change in polarity of an incoming signal and the next but one change i.e., the time for one cycle of the incoming signal. Alternatively, the duration of each pulse can extend over three or more changes in polarity.

Further, in the above circuits the period/voltage converter 5 provides pulses each having a maximum amplitude representing the duration of a part of the cycle of an incoming signal. Instead, a signal having some other electrical parameter, such as phase, representing the duration of a part of a cycle of an input signal could be produced.

It is not essential to generate a pulse for every positive- or negative-going part of an incoming signal. For example, alternate positive-going excursions could be ignored.

Claims (4)

1. A circuit for discriminating between an alternating electrical signal of constant or substantially constant frequency and a signal of varying frequency comprises means for generating a train of electrical signals each having an electrical parameter whose magnitude represents the time taken by an alternating input signal to undergo a small predetermined number of changes in polarity, means for comparing the magnitudes of the electrical parameters of two signals in the train and for generating an output signal representing a comparison between two signals whose electrical parameters have the same magnitude, and hence are derived from an input signal of constant or substantially constant frequency, or two signals whose electrical parameters have different magnitudes and hence are derived from an input signal of varying frequency.

2. A circuit as claimed in Claim 1, further comprising means for generating a first electrical signal having an electrical parameter whose magnitude increases in accordance with the number of cycles of an input signal applied to the circuit, means for generating a predetermined output when the magnitude of the electrical parameter of the first signal reaches a predetermined value, and means for applying the said output signal from the comparing means to the means for generating the predetermined output, whereby the said means for generating the predetermined output is re-set if the said output signal represents two signals within a predetermined period whose electrical parameters have different magnitudes, derived from an input signal of varying frequency.

3. A circuit as claimed in Claim 1 or 2, further comprising means for generating a second electrical signal if there is a break in the input signal which persists for a predetermined interval of time, and means for applying the second electrical signal to the means for generating the predetermined output, whereby the said means for generating the predetermined output is re-set.

4. Acircuitfor discriminating between an alternating electrical signal of constant or substantially constant frequency and a signal of varying frequency, the circuit being constructed, arranged and adapted to operate substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawings.