GB2068690A - Data transmission system for digital controllers - Google Patents

Abstract

A system for data communication among a plurality of digital processors via a data bus wherein any one of the processors may act as a master station to control the data bus to exchange data with another processor and can then transfer control of the data bus to another processor requiring control of the bus, so that the other processor can exchange data via the bus. If a master station signal fails to appear on the bus for more than a predetermined period of time, any of the processors may take control in accordance with a predetermined priority system.

Description

SPECIFICATION Data transmission system for digital controllers This invention relates to data transmission systems for digital processors and more particularly, to a data transmission system for data communication between a plurality of processors containing microcomputers for process control.

in most industrial settings, direct digital control (DDC) systems have replaced analog systems for controlling processing loops because the digital systems are generally more flexible and more accurate than the analog systems. Also, unlike an analog system, a digital system may be centrally monitored and controlled.

By incorporating microprocessors, the process control in the DDC systems has become more distributed. In a typical distributed DDC system, a single microprocessor controls only eight to thirty-two of the process loops. Distributed DDC systems provide greater control and increased safety and reliability over the conventional DDC systems which were managed by a single central computer.

Distributed DDC systems have recently met with some criticism. There are demands that these systems be interchangeable with conventional analog equipment and those demands have not been met Also, in conventional distributed DDC systems, the failure of one processor can halt the operation of many loops.

The conventional DDC systems have other disadvantages. Since the control loops are usually monitored and serviced by the microprocessor in a timeshared manner, the period of time that a loop must wait between microprocessor servicing is fixed and irreducible. With the emergence of high-speed control systems having short loop times and requiring fast responses, the conventional distributed DDC's are becoming unsuitable.

One avenue for improvement of distributed DDC systems has appeared since the cost for microprocessors has now dropped to a low enough level to allow the use of one microprocessor to control a single loop in a digital control system. The major obstacle to using a single processor to control a single loop is the difficulty in communicating among the several independently operating loops. Communication between the control loops is vital for control systems employing cascade control, sequence control, ratio control, etc.

Figure 1 shows a decentralized DDC system involves ing cascade control. Processors 1 and 2 each control separate process loops. A manipulated variable "cascades" from processor 1 to processor 2. That variable is applied to the analog input terminal of processor 2 and used as a set point value for that loop.

Both controllers have analog-to-digital (AID) converters to change data from a sensor (ag., flowme- ter, thermometer, etc.) into a form acceptable for the memory and the central processor unit (CPU). The CPU in processor 1 uses the converted sensor data (also called a process variable) to compute the manipulated variable which is applied, through a digital to analog (D/A) converter, into the AID converter of processor 2.

This system in Figure 1 has, among other problems, a lack of flexibility because the hardwire connections between the processors is fixed. In addition, communication between the processors in such a system requires either an AID and DIA converter for each processor or converters which are timeshared by all the processors in the system.

Figure 2 illustrates a different type of distributed DDC system. Each loop processor 21 contains a microcomputerto control a single loop and communicate with the master station 22. The master station, which is provided with a console, controls data communication of the system by sending out interrupt signals to the processors at predetermined time intervals.

In this system, any data transfer between processors involves the master station. This aspect of the system is inefficient because each data transfer between two processors involves two steps. The first processor sends data to the master station and then the master station routes that data to the second processor.

Another, perhaps more serious problem is that if the master station ever fails, all data transmission between processors ceases.

This invention seeks to provide a data transmission system for digital processors in which the above described difficulties of conventional data transmission systems are eliminated, and in which the transmission of data can be effected among the processors with greater efficiency and reliability by reducing the burdon of the processor acting as the master station.

The invention further seeks to provide a data transmission system for digital controllers in which the master station is not permanently assigned to a particular digital processor, thereby mitigating the effect on the system of the failure of a processor.

According to the invention there is provided a data transmission system comprising a plurality of data processors, each of the data processors being capable of digital communication with every other data processor, a digital data bus coupled to each of the data processors for digital communication among the data processors, and data control means in each of the data processors for taking control of the data bus from another of the data processors, for digitally communicating with any other of the data processors through the data bus, and for passing control of the data bus to any other of the data processors.

The method of this invention of transmitting digital data between a plurality of data processors connected to a data bus comprises the steps of giving control of the data bus to one of the data processors, that data processor which for the time being has control of the data bus, being called the current master station, allowing the current master station to communicate digitally with any other data processor over the data bus, having the current master station select one of the data processors to be the next master station to have control of the data bus, and pas sing control of the data bus to the next master station.

Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Figures 1 and 2 are diagrams of conventional data transmission systems for digital processors; Figure 3 Is a block diagram of the data transmission system of this invention; Figure 4 is a block diagram of one type of loop processor according to the present invention; Figure 4A is a block diagram of a different embodiment of a loop processor according to the present invention; Figure 5 is a flow chart describing the polling sequence of the current master station; Figure 6 is a diagram showing the timing of a system of loop processors according to the present invention; Figures 7 and 8 are detailed block diagrams of loop processors according to the present invention;; Figure 9 is a detailed block diagram of a loop processor according to the present invention; Figure 10 is a diagram of a data transmission format which can be used in the present invention; and Figure 11 is a detailed block diagram of the data transmission section of the loop processor in Figure 8.

A preferred embodiment of a data transmission system is represented in Figure 3. The data transmission system includes a plurality of data processors 3-1 to 3-n each of which is capable of digital communication with every other processor. The system also includes a digital data bus 32 coupled to each of the processors for digital communication between the processors.

Data processors 3-1,3-2... 3-n each operate as a DDC (direct digital control) device and each processor controls a single loop.

Figure 4 shows the configuration of a processor40 in the data transmission system of this embodiment of the present invention. Each processor includes data control means for taking control of the data bus from another of the plurality of data processors, for digitally communicating with any other of the plurality of data processors through the data bus, and for passing control of the data bus to any other of the plurality of data processors.

As herein embodied, the data control means includes a data transmission section 41 which is coupled to the data bus and which, among other things, acts as an interface between the internal data bus 47 and the external data bus. The data control means also includes central processing unit (CPU) 42 which controls the data communication functions of processor 40. In the preferred embodiment, CPU 42 includes a microprocessor.

Processor 40 contains, in addition to the above components, memory 43, analog-to-digital (AID) converter 44, and digital-to-analog (D/A) converters 45. All the elements in processor 40 are coupled to internal data bus 47.

The data transmission system in Figure 3 includes of a number of processors similar to processor 40 in Figure 4, coupled to a data bus. At any given time, one of the processors 3-1 to 3-n has control of data bus 32. The processor in control of the bus is called the current master station and the other processors are called slave stations. Only the current master station can initiate the transmission of data to or from another processor; the slave processors can only respond the master station's requests.

In the system of Figure 3, if controller 3-1 required data from processor 3-3, processor 3-1 would need to become the master station to acquire that data. To become the master station, processor 3-1 must receive control of the data bus from the processor currently acting as master station.

When the current master station completes its data transfer, it asks the other processors whether they wish to become the master station. When asked, processor 3-1 would respond affirmatively and the current master station would give control of the data bus to processor 3-1.

As master station, processor 3-1 requests, via data bus 32, that processor 3-3 send the desired data. At some time later, processor 3-1 receives the data from processor 3-3 via bus 32.

When the data transfer is complete, processor 3-1 loses its rightto be the master station because that processor no longer needs to control data bus 32. To determine which processor should be the next master station, processor 3-1 asks the other processors whether they wish to be the next master station.

The processors are polled sequentially. In Figure 3, if processor 3-1 is the master station, the polling sequence is 3-2,3-3, . . 3-n. If processor 3-7 is the master station, the sequence is 3-8,3-9... 3-n, 3-1,..

.3-6. The particular sequence is not important as long as no processor which needs to transfer data is foreclosed from becoming the master station.

Figure 5 shows a diagram of the preferred method for the current master station's polling of the slave stations to determine the next master station.

According to the method, the current master station asks the next processor in sequence whether it wants control of the data bus (Step 501). The master; station first determines whetherthe processor just polled has replied (Step 502). If it has, the master station next determines whether that processor wants control of the data bus (Step 503), and if it does, control of the data bus is transferred to that processor which then becomes the new master station (Step 504).

If the polled processor does not want control of the data bus, the master station must then determine whether all of the other processors have been asked (Step 505). If not, the master station resumes polling the processors and follows the above steps with the next processor in sequence.

If all the processors have been asked, then the master station waits a predetermined period of time, e.g., one second, before asking the processors again wether they want control (Step 506). Instead of repeating the polling sequence when no processor wants control of the data bus, this system could be designed to have the master station forcibly shifted to another processor. This would tend to distribute the burden of being the master station more equally among the processors in the system.

In Step 502, if the current master station received no reply from the polled processor, that processor is then asked a second time whether it wants control of the data bus (Step 507) and the master station again determines whether there was a reply (Step 508). If there is a reply this time, then that reply is analyzed in step 503 as previously described.

If there was no replytothe second inquiry, a third and final inquiry is made to the processor (Step 509).

If the processor replies to this third inquiry then that reply is analyzed in Step 503. If to this third inquiry there is still no reply (Step 510), the master station records the fact that this processor is inactive and the master station no longer questions this processor (Step 511).

By registering a processor's failure to reply to three successive inquiries, the master station will not waste time in the future by questioning inactive or inoperative processors. In this regard, the system of the present invention is dynamic and self-correcting.

A non-responding processor is polled three times because when it is polled, the processor may be in the middle of a loop control operation and have disabled its interrupt lines. The length of time that the processor's interrupts are disabled, however, should not be greater than the time amount of time required for three successive inquiries from the master station.

The processors attempt to respond to a master station query except when they are prohibited from being interrupted, e.g., during their process control.

This is true when the master station requests the transmission of operational data (i.e. manipulated variables) from the processors as well as when the master station is selecting the next master station.

After registering a processor's failure to reply to three consecutive inquiries, the master station determines whether all the processors have been polled (Step 505). If not, then the polling is repeated with the next processor in sequence (Step 501), and if all the processors have been asked, then the master station waits a predetermined period of time (Step 506) before resuming the polling process (Step 501).

The processors in this system thus comprise data control means for requesting control of the data bus from the master station for receiving control of the data bus from the master station for digitally communicating with another processor, for asking each of the rest of the processors for replies indicating whether they request control of the data bus, and if processor fails to reply, for asking the nonresponding processor at most two more times for a reply and upon failing to receive a reply from that processor for recording that non-responding processor is inoperative in order to refrain from asking non-responding processor further, and fortransfer- ring control of the data bus to the first processor which responds with a request for control of the data bus.In Figure 4 this data control means includes CPU 42.

In the system of the present invention, if the processor acting as the current master station fails, another processor must take control of the data bus and become the master station. The other processors are aware that the master station has failed when they have not detected any master station signals on the data bus for some predetermined period of time, e.g.,four seconds. Typically, in the preferred embodiment, signals from the master station to the slave stations appear on the data bus every .1 to .2 seconds. If there is a period of bus inactivity much longer than .2 seconds, it is apparent that the current master station has failed, and another processor must take the initiative and become the master station.

There is a danger of a number of processors becoming master stations simultaneously. To avoid this, each process is assigned a priority by virtue of its programmed no-signal detection time, the time that the processor detecting no master station signals will wait before becoming the master station. In the preferred embodiment, processor 3-1 becomes the master station if it detects no signal for 4.1 seconds; processor 3-2 waits 4.2 seconds, etc.

Different means can be used to avoid the problem of having multiple master stations in response to the failure of the current master station. Whichever means is used, it must ensure that one but only one processor becomes the master station.

in a preferred embodiment of this invention the processor acting as master station must transmit many signals to the other processors both for data transfer and for determining the next master station.

To relieve much of the burden of this communication, the processors in the system can be provided with a second microprocessor which is dedicated to data bus transmission. A processor with such a provision is seen in Figure 4A.

Thus each of the processors in this system can comprise data transfer means for digitally communicating with another processor in the data transmission system. In Figure 4A, processor40' has, as part of its data transmission section 41', a second microprocessor 46 which handles all the data communication between processor awo and the other processors. Microprocessor 46 is connected to CPU 42', memory 43, AID converter 44 and DIA converters 45 through data bus 47'.

It will be recalled that, in accordance with a preferred feature of the invention, each of the processors can comprise master station means for requesting control of the bus from the master station, for receiving control of the bus from the master station, for asking each of the rest of the data processors for replies indicating whether their request control of the data bus, and if a processor fails to reply, for asking that non-responding processor at most two more times for a reply, and upon failing to receive a reply from the non-responding processor for recording the non-responding processor as inoperative in order to refrain from asking that non-responding processor further, and for transferring control of the data bus to the first processor which responds with a request for control of the data bus.In Figure 4A, the master station means includes CPU 42'.

The present invention also envisages systems similar to the ones described which are designed to minimize processor interruptions. The processors in one such system do not operate independently, but instead, the control of all the loops is synchronous with respect to the data transmission timing. Figure 6 shows the timing of one such system.

To maintain synchronism, each processor has the same unit operation period which is the basic repeat- ing frame of time for processor operation. The unit operation period comprises a data transmission subperiod, a control processing subperiod and a margin period, as shown in Figure 6. In the preferred embodiment, the unit operation period is 200 milliseconds and the data transmission subperiod lasts for the first several tens of milliseconds (e.g.,the first 40 milliseconds) of the unit operation period.

In the preferred embodiment, every 200 mii- liseconds, atthe beginning of a unit operation period, the master station applies a global address signal to the other processors via the data bus. The slave stations use the global address signal to adjust their own timing, any corrections in timing being referred to as the "margin period." The first several tens of milliseconds after receipt of this signal are used by the slave stations only for data transmission between the processors: no loop control is carried out during this time. Accordingly, when the master station requires a data transfer, the slave stations need never be interrupted and also data transfer is achieved in a relatively short time.

Figure 7 is a detailed block diagram of a processor 50 of this invention. Processor 50 is a one-loop processor which does not mean that control system in the processor corresponds to only one process variable, but the term "one-loop processor" also includes control systems which correspond to related process variables.

In processor 50, microprocessor 61 carries out process control on a regular basis. If microprocessor 61 is actively carring out process control it cannot be interrupted. At other times, microprocessor 61 can be interrupted by interrupt signals IRQ1 -4 whose functions will be described later.

To control the process loops, microprocessor 61 must have access to certain loop parameters. A sensor70, which measures signals such as process variables, is selected by multiplexor 62 to be inputted to AID converter 63. The output of converter 63 passes through l/O port 64 and internal data bus 69 into either memory 65 or microprocessor 61 to be used in computing manipulated variables.

Manipulated variables in memory 65 are outputted via data bus 69 and 110 port 66 into DIA converter 67, which connects to an operation terminal (not shown). Manipulated variable data is latched in I/O port 66 until the next value is provided.

In the preferred operation, interrupt timer 68 generates interrupt signal IRQ1 which indicates the beginning of a unit operating period. IRQ1 tells mic roprocessor 61 to store a process variable, e.g., pressure, flow rate, temperature, etc., into a pre determined address in memory. Typically, the pro cess variable's value is compared with a value stored in memory 65. Microprocessor 61 also uses the process variable data to calculate the manipulated van- ables.

if this processor were a slave station in the synchronous system described with reference to Figure 6, this processor would wait until the data transmission subperiod ended before starting the process control operation.

Transmission line 52, which consists of a pair of shielded lines, acts as the data bus between the processors in the system. Processor 50 communicates with line 52 by line interface unit 53. Line interface unit 53 converts the data from the data receiving and transmitting circuits 51 into an electric signal suit able for transmission through line 52 (e.g.,frequency modulation). Line interface unit 53 also provides signal isolation between line 52 and processor 50 and contains the no-signal detection apparatus, which, by interrupt signal IRQ4, notifies the microprocessor 61 of the absence of master station signals on line 52 for more than the allowable period of time.

The data transmitting and receiving circuit 51 accepts information from internal bus 69 in a parallel format and converts that information to a continuous serial data stream for transmission via line 52.

After completing that transmission, circuit 51 sends interrupt IRQ2 to microprocessor 61.

Circuit 51 also accepts serial data streams from line 52 and converts that data into a parallel format compatible with internal bus 69. After the data from line 52 is received, circuit 51 sends IRQ3 interrupt signal to microprocessor 61. The received data is stored in memory 65.

When processor 50 is the master station and requires data from another processor, e.g., for cascade control, microprocessor 61 sends the address of that processor and the type of data required through circuit 51 to transmission line 52, and eventually to the destination processor.

Often, the address or data from memory must be sent to circuit 51 in parts because the transmission word is larger than the width of bus 69. In such a situation, transmitting and receiving circuit 51, after transmitting one part of the data, signals microprocessor 61 via the IRQ2 signal which causes the next part of data to be sent to circuit 51.

If the master station had sent out a processor address with a request for data, the master station would wait some period of time and receive the requested data in the manner described above.

As master station in the synchronous system described with respectto Figure 6, processor 50 would also be responsible for transmitting the global addresses to the slave stations.

Some of the limitations of the system in Figure 7 can be alleviated by the system in Figure 8. Proces sor 50' in Figure 8 also includes a direct memory access (DMA) controller 80 to manage data transfer between data transmitting and receiving circuit 51 and memory 65.

in processor 50', it is unnecessary to have microprocessor 61 actively manage the flow of data between circuit 51 and memory 65. Instead, the DMA controller 80 steals memory cycles (and use of internal bus 69) from microprocessor 61 by methods well-known in the art.

Microprocessor 61 is notified of the data transfer between circuit 51 and memory 65 only at the completion of the DMA transfer. In this manner, data transmission is still possible with processor 50' even while microprocessor 61 is actively involved in loop processing. This sytem also minimizes the costly "overhead" of frequent interrupt processing.

In Figure 8, reference numeral 71 designates a data flow between circuit 51 and memory 65 at the time of the DMAtransfer. At all other times, the microprocessor 61 uses bus 69 and the data flows as designated by reference numeral 72.

Figure 9 shows a more elaborate embodiment for the processor of this invention. Analog multiplexer MPX selects one of the following inputs to be con verted to a digital signal by AID converterADC: pro- cess variable PV, auxiliary inputs All -Al4 (used, e.g., for cascade control, ratio control, etc.) or manipuiated variable MV. The digital signal from ADC is inputted to the CPU or one of the RAMs through I/O portAl/AO and the internal data bus.

The four analog output channels, SV (set point variable) MV (manipulated variable), KPV (correction process variable) and AO (analog output) connect to the internal data bus through D/A converters DAC and the Al/AO switch. The MV channel also has a V/i (voltage to current) conversion circuit for providing either a voltage output of 0-5.12 VDC or a current output of 4-20 mADC, and the MV channel has a manual control circuit 82 which allows the MV signal to be controlled independently of the processor, (e.g.,when the processor has failed and cannot carry out automatic control).

Digital inputs Dl1 and Dl2, which are of the novoltage contact-type, pass via the DO/DI (digital output/digital input) switch and the internal data bus into the CPU orthe RAMs. Digital outputs D01-D03, which are used for sequence control and alarm generation, are outputted from the CPU through the internal data bus, I/O port DO/DI and the DO buffer.

D01 -D03 are open-collector transistor outputs.

In the embodiment shown in Figure 9, the CPU 81 comprises a microprocessor model 8085A made by Intel Co. The system PROM (programmable readonly memory) contains the control algorithms for the microprocessor as well as the procedures necessary for communicating with the other processors. Part of the PROM is designated as a system PROM for storing system parameters and linkage data.

Process variables and other data are stored in the RAM (random access memory), which is supported by backup capacitor 86 to maintain the RAM's proper operation when power to the processor is momentarily interrupted. For long term protection, a battery can be added across the capacitor.

The data linkage interface 83 connects the processorto the data bus (not shown) and ultimately to the other processors. The data link interface also manages the format of the data used on the bus.

In the preferred embodiment, the system containing the processor in Figure 9 uses a high-level data link control (HDLC) format, also referred to as International Standard ISO 3309, which is shown in Figure 10.

The format contains two flags: HDLC frame start flag and HDLC frame end flag. The start flag identifies an address or control field, thus signalling the start of a transfer error check. The end flag informs the station receiving the data that the immediately preceding 16 bits are a cyclic redundancy check (CRC) code (used for error detection in the received data).

The address field contains the identification code for the controller. The information field's length is unspecified, but it is always a multiple of eight bits.

A master station takes about 350 microseconds to transmit data to another processor using the frame in Figure 10. The receiving processor takes about 1 millisecond to act on this data and then the processortakes another 350 microseconds to return one frame of an answer to the master station. The master station in turn processes that answer for another mil lisecond.

Consequently, the communication between one master station and one processor requires about 2.7 msec. If 16 processors are in the data transmission system, it takes about 40.5 milliseconds for the master station to communicate with the fifteen other processors.

The master station asks the other processors whether or not they want to transmit data or whether or not they want to become the master station. This inquiry operation is carried out with the signals in the control one-byte part. Both the signal indicating whether or not any one processor wants to become the master station and the data transmission signal are transmitted with the control one-byte part to the master station from the controller.

Figure 11 is a detailed block diagram of part of a processor which will be used to demonstrate the data transmission mechanism of the processor in Figure 8. CPU 101, corresponding to microprocessor 61 in Figure 8, includes a microprocessor model 8085A made by Intel Co. The clock pulses for CPU 101 are provided by clock pulse generator 114. System timer 68, which generates the IRQ1 synchronizing interrupt, also works off clock pulse generator 114.

DMA controller 102, corresponding to controller 80 in Figure 8, is a model AM9517 made by Advance Micro Devices, Inc. Transmission controller 103, part of the data transmitting and receiving circuit 51, is a model 2652 made by Signetics Co. and interruption controller 104 is a model 8259A manufactured by Intel Co. The interruption controller allows the CPU to accept more than one request signal.

Memory 105, corresponding to memory 65 in Figure 8, includes a RAM and a PROM. The RAM contains process variables and data, and the PROM con tains instructions.

Decoder 106 selects the above-described system units 101,102,103,104, and 105 in response to address signals A8-A15 from either CPU 101 or DMA controller 102.

Address latch circuits 107 and 108 hold the ADO-AD7 signals. Latch 107 is controlled by the ALE (address latch enable) signal from CPU 101 and it holds the ADO-AD7 signals for output to lines AO-A7, the low address signals, when high address signals A8-A15 are provided by the CPU. Address latch cir cuit 108, controlled by the ADSTB (address strobe) signal from DMA controller 102, holds the ADO-AD7 signals for output to lines A8-A15, the high address signals, when the low address signals are provided directly from DMA controller 102.

Read/write control circuit 109 receives the RD (read control), WR (write control), and lO/M (10/Memory select) signals from the CPU and con verts them to bus control signals to READ, 10 WRITE, MEMORY WRITE, and MEMORY READ which are wired-or-connected to the respective outputs of DMA controller 103.

The transmitting and receiving circuit, circuit 51 in Figure 8, comprises transmission controller 103, 1/O port 111 and address control circuit 112. In response to signals from CPU 101, I/O port 111 places transmission controller 103 in either a send state or a receive state by activating either the T x E (Transmit- ter enable) or the R x E (Receiverenable) inputsto controller 103.

When the CPU wants controller 103 to read or write, address control circuit 112 switches three of the lower address signals on lines AO-A7 and the Transmission Controller Chip Select signal from decoder 106 to controller 103. Circuit 112 switches address signals to the transmission controller 103 according to whether DMA controller 102 is perform- ing a read or a write operation.

Interrupt controller 104 manages the priority and the identification of the interrupt signals IRQ1 -IRQ4 for CPU 101, and sends to the CPU the call instructions and the jump destination addresses for the interrupt processing routines corresponding to the interrupt signals. Interrupt controller 104 also sup plies the INTR or interrupt request signal to CPU 101 receives the INTA or interrupt acknowledge signal from the CPU.

When the processor in Figure 11 wants to send data to another processor, either during the transfer of operational data or during the determination of the next master station, CPU 101 outputs a transmission command causing I/O port 111 to raise the transmitter enable signal T x E to a logical "I" level.

Signal T x E indicates to transmission controller 103 that data is to be transmitted. Controller 103 then signals DMA controller 102 by applying output signal T x BE to DMA controller input DREO1.

Transmission controller 103 receives the data to be transmitted from memory 105 via DMA transfer.

For a DMA transfer, DMA controller 102 provides signal HREQ to CPU 101 to request use of the bus.

When the CPU finishes the present instruction cycle, it sends out signal HACK to acknowledge to the DMA controller that it can use the bus.

The address signals A0-A7 contain the address of the data to be transmitted. The address signals are sent to the RAM and decoder 106 generates the RAM Chip Select signal. Signals DACK0 and DACK1 from DMA controller 102 tell address control circuit 112 to send the proper signals to controller 103. In this embodiment, DACK stands for DMA Acknowledge.

DACKO corresponds to DMA channel 0, the data reception channel, and DACK1 corresponds to DMA channel 1, the data transmission channel.

Transmission controller 103 outputs the data from itsT x SO terminal to line interface 153, using transmitter clock T x C supplied by the interface.

Line interface 153, corresponding to line interface unit 53 in Figure 8, passes the data in proper form to transmission line 52. Transmission line 52 consists of a twisted pair of lines.

Atthe completion of the data transmission, con troller 103 signals CPU 101 with the IRQ2 signal.

To receive data from another processor, the CPU, which has been notified of the presence of such data by interrupt IRQ3 from controller 103, sends a com- mand which causes I/O port 111 to apply the data reception preparation signal, also called the receiver enable signal, R x E to transmission controller 103.

The received data is read into controller 103 using receiver clock R x C. When the data from another processor is received, transmission controller 103 sends the reception data read request R x DAto DMA controller 102 input DREQO. The received data is stored in memory 105 through DMA transfer. The method of DMAtransfer is the same as described above except the data is transferred to rather than received from memory 105.

The above method of transferring information is used when the processor is the master station and is either initiating the transfer of some data, like a manipulated variable, or is polling the other processors.

That same method of data transfer is also used when the processor is the slave station and is responding to the data transfers or inquiries by the master station. In the preferred embodiment of the system of this invention, all the processors have a data transmission system similar to the one in Figure 11.

In the data transmission system of the present invention, unlike the conventional systems, no particular processor is provided as master station for data transmission. Data transmission is effectively carried out between the processors and the failure of a processor does not cause a failure of the entire system. For the same reason, the operation of the data transmission system does not become suspended when the current master station becomes inoperative.

In the system of the invention, each processor controls its respective process and also transmits and receives data from other control loops when necessary, thereby allowing high-speed cascade control, ratio control, etc. This system is also very flexible as it will operate effectively with different numbers of processors and different processor requirements.

It will be apparent to those skilled in the art that modifications and variations can be made in the data transmission system of the invention without departing from the scope or spirit of the invention. It is intended that the present invention cover the modif cations and variations provided that they come within the scope of the appended claims.

Claims (11)

1. A data transmission system comprising: a) a plurality of data processors, each of said plurality of data processors being capable of digital communication with every other one of said plurality of data processors; b) a digital data bus coupled to each of said plural ity of data processors for digital communication among said plurality of data processors; characterised by c) data control means in each of said plurality of data processorsfortaking control of said data bus from another of said plurality of data processors, for digitally communicating with any other of said plurality of data processors through said data bus, and for giving control of said data bus to any one of said other data processors.

2. The data transmission system in claim 1 wherein said data control means includes a microprocessor.

3. The data transmission system in claim 1 wherein the data control means only communicates with said processors at regular, repeating time periods, said regular, repeating time periods of all of said plurality of processors being the same.

4. A data transmission system according to claim 1 and comprising: a) a digital data bus; b) a plurality of data processors coupled to said data bus for transferring digital data among said data processors by having a selected one of said data processors in control of said bus, said selected processor operating as a master station; c) data transfer means in each of said plurality of data processors for digitally communicating with anotherofsaid processors; and d) master station means in each of said plurality of processors for requesting control of said bus from said selected processor, for receiving control of said bus from said selected processor, for asking each of the rest of said plurality of data processors for replies indicating whether each of said data processors is requesting control of said data bus, and if a non-responding processor fails to reply, for asking said non-responding processor at most two more times for said reply, and upon failing to receive said reply from said non-responding processor for recording said non-responding processor as inoperative in order to refrain from asking said nonresponding processor further, and for transferring control of said data bus to the first of said processors which responds with said requestforcontrol of said data bus.

5. A data transmission system according to claim 1 and comprising: a) a digital data bus; b) a plurality of data processors coupled to said data bus for transferring digital data among said data processors by having a selected one of said data processors in control of said bus, said selected processor in control of said bus operating as a master station; and c) data control means in each of said plurality of data processors for requesting control of said data bus from said selected processor, for receiving control of said data bus from said master station, for digitally communicating with another of said processors, for asking each of the rest of said plurality of data processors for replies indicating whether each of said data processors is requesting control of said data bus, and if a non-responding processor fails to reply, for asking said non-responding processor at most two more times for said reply and upon failing to receive said reply from said non-responding processor for recording that said non-responding processor is inoperative in order to refrain from asking said non-responding processor further, and for transferring said control of said data bus to the first of said processors which responds with said request for control of said data bus.

6. A method of transmitting digital data between a plurality of data processors connected to a data bus, comprising the steps of: a) giving control of said data bus to a selected one of said plurality of data processors; b) allowing said selected processor to communicate digitally with any other of said plurality of data processors over said data bus; c) having said selected processor select another one of said plurality of data processors to have the immediately succeeding control of said data bus; and d) giving said next selected processor control of said data bus.

7. The method of claim 6 wherein said step of allowing said master station to transfer data further includes the sub-steps of: applying a global address signal to said plurality of data processors; and transferring said digital data only during a data transmission period, said data transmission period occurring at a fixed time relative to said global address signal.

8. A method for transmitting digital data by each data processor coupled to a data bus which is always in control of a selected one of said data processors acting as a master station, said data bus being used for transmitting digital data to every other data processor on said data bus, the method comprising the steps of:: a) requesting control of said data bus when asked by said selected processor; b) receiving control of said data bus from said selected processorto become said master station; c) communicating via said data bus with any other of said data processors on said data bus; d) asking each of said data processors on said data data bus for a reply indicating whether each of said data processors requests control of said data bus; e) asking a non-responding processor at most two more times for said reply and when failing to receive any reply recording that said non-responding processor is inactive or inoperative to refrain from asking said non-responding processor further; and fl transferring said control of said data bus to the first of said processors which replied with a request for said control of said data bus.

9. A method of transmitting digital data between a plurality of data processors connected to a data bus, the said method being in accordance with any one of claims 6 to 8, in which any one of the data processors may take control of the bus, if a master station signal does not appear on the bus for a predetermined period of time, each of the processors beings arranged to wait for a different predetermined period of time before taking control.

10. A data transmission system substantially as herein described with reference to Figures 3 to 11 of the accompanying drawings.

11. A method ofdatatransmission as claimed in any one of claims 6 to 9 and substantially as herein described.