GB2068168A - Bipolar transistor - Google Patents
Bipolar transistor Download PDFInfo
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- GB2068168A GB2068168A GB8002703A GB8002703A GB2068168A GB 2068168 A GB2068168 A GB 2068168A GB 8002703 A GB8002703 A GB 8002703A GB 8002703 A GB8002703 A GB 8002703A GB 2068168 A GB2068168 A GB 2068168A
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- layer
- heavily doped
- conductivity type
- groove
- epitaxial layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Abstract
A bipolar transistor is formed in a body of semiconductor material having a heavily doped layer 10 of one conductivity type and thereon an epitaxial layer 12 of the opposite conductivity type, the layer 10 being on a supporting layer 11, by forming a a groove 14 which encircles parts of the layers 10 and 12, which parts are electrically isolated from the remainder of the semiconductor material, providing a base contact region 16__, by introducing impurity into all the surface portions of the semiconductive material to form heavily doped material of said opposite conductivity type, and subsequently providing a collector contact region 25 of said one conductivity type at where the layer 10 defines a groove portion, the collector contact region possibly extending to the surface of the epitaxial layer, whilst simultaneously providing an emitter 24. Such transistors are suitable for integrated circuits. <IMAGE>
Description
SPECIFICATION
Bipolar transistors
This invention relates to bipolar transistors, and in particular to bipolar transistors suitable to be embodied within monolithic semiconductor integrated circuit devices.
Advantageous forms of bipolar transistors suitable to be embodied within monolithic semiconductor integrated circuit devices each requires only a few processing steps to be performed in its manufacture, and in particular requires only a few photolithographic etching steps, each employing a mask.
Further, it is desirable that the bipolar transistors each occupies only a small area of the contact-bearing surface of the body in which it is formed.
The fewer the processing steps required to manufacture a bipolar transistor and/or the smaller the area of the contact bearing major surface of the body occupied by the bipolar transistor, the better the manufacturing yields of the bipolar transistor.
In an integrated circuit device a bipolar transistor may be required to be isolated individually, or to be isolated together with other circuit elements, within the semiconductor material of the body of the device. It is essential for a bipolar transistor in accordance with the present invention to be adjacent to, and to include, at least part of the means to isolate the bipolar transistor within the semiconductor material. Further, for convenience, in this specification and the accompanying claims, only bipolar transistors each individually isolated within the semiconductor material from other circuit elements will be referred to, but a bipolar transistor in accordance with the present invention can include only part of the means to isolate it within the semiconductor material, if it is to be isolated together with other circuit elements of the integrated circuit device.
It is an object of the present invention to provide a novel method of manufacturing a bipolar transistor suitable to be embodied within monolithic semiconductor integrated circuit device, the method having high yields associated therewith.
It is another object of the present invention to provide a novel bipolar transistor construction suitable to be embodied within monolithic semiconductor integrated circuit devices, and, for example, being capable of having high manufacturing yields associated therewith.
According to the present invention a method of manufacturing a bipolar transistor comprises providing a body, with semiconductor material of the body at least including a heavily doped layer, with a resistivity value at most equal to 0.2 ohm-cm., and of one conductivity type, and an epitaxial layer on the heavily doped layer, the epitaxial layer being initially wholly of said opposite conductivity type and having a resistivity value at least equal to 10 ohms-cms., the heavily doped layer.being provided on a supporting layer of the body, the epitaxial layer being remote from the supporting layer, in either possible order, forming a groove to extend through both the epitaxial layer and the heavily doped layer, and to encircle parts of both of the layers electrically isolated from the remainder of the semiconductor material, and introducing impurity characteristic of said opposite conductivity type into all the surface portions of the semiconductor material adjacent to the then major surface of the body at least including the surface of the epitaxial layer remote from the heavily doped layer, subsequently introducing impurity characteristic of said one conductivity type both selectively into a part of the surface portion of the epitaxial layer remote from the heavily doped layer and encircled by the groove, to provide an emitter, and simultaneously and selectively into where a surface portion of the groove encircled part of the heavily doped layer defines a portion of the groove, to provide a collector contact region, the groove encircled part of the heavily doped layer comprising the bulk of the collector, and the parts of the epitaxial layer of said opposite conductivity type, and encircled by the groove, comprising the base, the introduced impurity characteristic of said opposite conductivity type providing heavily doped material, with a resistivity value at most equal to 0.1 ohm-cm., at least at the surface of the base remote from the heavily doped layer, and within the base and surrounding the emitter, at least the portions of the base contiguous with the bulk of the heavily doped layer comprising unmodified portions of the epitaxial layer, part of the heavily doped material at the surface remote from the heavily doped layer comprising a base contact region, during, and/or subsequent to, the introduction of the impurity characteristic of said opposite conductivity type into the semiconductor material, providing a layer of passivating material on the surfaces of the semiconductor material both within the groove, and of the groove-encircled part of the epitaxial layer remote from the heavily doped layer, and providing contacts, extending through apertures in the passivating layer, to each of the collector contact region, the base contact region, and the emitter.
The method of manufacturing a bipolar transistor and referred to above is advantageous in that only a few constituent steps are required.
In particular, usually only four photolithographic etching steps, each employing a mask are required in the manufacture of the transistor; in forming the groove; when introducing impurity characteristic of said one conductivity type into the emitter and collector contact regions; in forming the aperture in the layer of passivating material for the base contact, and possibly also in forming the apertures for the emitter and collector contacts; and in forming the contacts from an initially continuous metal layer. The ability to use only four masks in manufacturing the transistor ensures that the method is especially advantageous. A bipolar transistor construction provided by such a method is also advantageous in that it is capable of occupying only a small area of the contact-bearing surface of the semiconductor material.
Usually, but not essentially, such a bipolar transistor comprises part of an integrated circuit device embodied within the semiconductor material, other circuit elements being embodied within the integrated circuit device in addition to the bipolar transistor, the bipolar transistor being required to be isolated from the other circuit elements within the semiconductor material. Whether included in an integrated circuit device, or not, a bipolar transistor construction in accordance with the present invention is also advantageous by including appropriate isolation means within a structure occupying only a small area of the contact-bearing surface of the semiconductor material, the isolation means comprising the groove coated with the passivating material.
The surrounding of the emitter of said one conductivity type, by the heavily doped material of said opposite conductivity type, is advantageous in that it causes the gainbandwidth product of the transistor to be greater than otherwise would be the case.
Usually the impurity characteristic of said opposite conductivity type is introduced after the formation of the groove, and into all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, heavily doped material of said opposite conductivity type being provided at the surface of the base exposed by the groove.
Irrespective of when the impurity characteristic of said opposite conductivity type is introduced, the provided supporting layer may be of semiconductor material of said opposite conductivity type, and the provided groove extends into part of the supporting layer; and when the impurity characteristic of said opposite conductivity type is introduced after the formation of the groove, and into all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, heavily doped material of said opposite conductivity type is provided at the portion of the supporting layer exposed by the groove.A supporting layer of semiconductor material either comprises a substrate part of the body; or is included in a substrate part, the remainder of the substrate part being either of semiconductor material or of electrical insulating material. The heavily doped layer may be formed by introducing impurity characteristic of said one conductivity type into a surface portion of a substrate part at least partially of semiconductor material.
It is important to provide any semiconductor circuit element of the device, such as a bipolar transistor circuit element, with a construction such that there are only low leakage currents across surface portions of reverse biassed P-N junctions of the circuit element, for example, such low leakage currents each only being of the order of 10 pico-amperes for a P-N junction reverse biassed with a potential difference of 5 volts associated therewith.
An NPN bipolar transistor construction in accordance with the present invention is advantageous also in this respect, when surface portions of the N + type collector of said one conductivity type are contiguous with surface portions of the P + type material, these P + type surface portions being provided at the surface of base exposed by the groove, and possibly also at the portion of the supporting layer exposed by the groove. The provision of the heavily doped P + type material prevents the inadvertent inversion of these surface portions to N conductivity type, beneath the passivating layer.
The passivating material may be of silicon oxide, especially when the semiconductor material is of silicon.
Any possible extension of the collector contact region into the supporting layer, if the supporting layer is of semiconductor material, may be of no consequence.
It is convenient to refer to surface portions of the semiconductor material exposed within the groove, when the groove is provided, as being exposed by the groove, even though, subsequently, the surface portions are coated with passivating material.
The surface portions of the epitaxial layer referred to as being remote from the heavily doped layer are not considered to be within the groove.
The epitaxial layer referred to above comprises the semiconductor material on the heavily doped layer, any material of said one conductivity type caused by the transfer of impurity from the heavily doped layer to the contiguous portions of the epitaxial layer during an epitaxial deposition process step being considered to be part of the heavily doped layer. Thus, the epitaxial layer includes modified semiconductor material comprising the emitter, any part of the collector contact region extending into the epitaxial layer from the heavily doped layer, and the heavily doped material of said opposite conductivity type, except any heavily doped material at the portion of a supporting layer of semiconductor material exposed by the groove, which latter heavily doped material is considered to be part of the supporting layer.
The groove may be formed in any convenient way, for example, by an anisotropic etching process step.
Impurity introduced into the semiconductor material during the manufacture of the bipolar transistor may be introduced in any convenient manner, for example, by diffusion, and/ or by ion impingement process steps.
The provided supporting layer may be of electrical insulating material, instead of semiconductor material, and comprises a substrate part of the body, upon which supporting layer at least one epitaxial layer of semiconductor material is deposited. The provided supporting layer may be of sapphire, and the provided semiconductor material may be of silicon. The provided groove may not extend into part of such a supporting layer of electrical insulating material.
Whether the provided supporting layer is of semiconductor material or of electrical insulating material, the heavily doped layer of said one conductivity type may comprise a first epitaxial layer deposited upon the supporting layer, and the epitaxial layer of said opposite conductivity type upon the heavily doped layer comprises a second epitaxial layer. Alternatively, only the epitaxial layer, of said opposite conductivity type may be deposited upon the supporting layer, and subsequently there is an initial introduction of impurity characteristic of said one conductivity type, to form a heavily doped layer intermediate between the supporting layer and the remaining, then unmodified parts of the sole epitaxial layer, these remaining, then unmodified, parts being considered as the epitaxial layer of said opposite conductivity type referred to above.The initial introduction of impurity characteristic of said one conductivity type is additional to the introduction of such impurity referred to above.
Alternatively, only one epitaxial layer, of said opposite conductivity type, is deposited upon a portion of electrical insulating material of the substrate part of the body, and subsequently there is an initial, additional, introduction of impurity characteristic of said one conductivity type, to form a heavily doped layer spaced from both the electrical insulating material and the surface of the sole epitaxial layer remote from the electrical insulating material, a supporting layer of semiconductor material, and considered to be of the substrate part of the body, comprising the remaining, then unmodified, parts of the sole epitaxial layer between the heavily doped layer and the electrical insulating material, the remaining, then unmodified, parts of the sole epitaxial layer remote from such a supporting layer being considered as the epitaxial layer of said opposite conductivity type referred to above.
Usually the heavily doped layer and the epitaxial layer are both of uniform thickness, although not necessarily of the same thickness.
The provided collector contact region may extend to, and along part of, the surface of the epitaxial layer remote from the heavily doped layer. In such an arrangement the provided collector contact exclusively may be on the part of the collector contact region at the surface of the epitaxial layer remote from the heavily doped layer.
The passivating layer on the surfaces of the body may be formed in any convenient way.
In one such way, before the introduction of the impurity characteristic of said one conductivity type, a continuous layer of passivating material is formed on all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, (possibly, after the formation of the groove, the impurity characteristic of said opposite conductivity type being introduced, in a diffusion process step, and the continuous layer of passivating material being formed at least partially during this diffusion process step), and apertures are formed through the passivating material, the impurity characteristic of said one conductivity type being introduced through these apertures into surface parts of the semiconductor material selected by the formation of the apertures, to form the emitter and the collector contact region, the remaining parts of the passivating material acting as the barrier to the introduction of the impurity into the parts of the semiconductor material covered thereby. The impurity characteristic of said one conductivity type may be introduced into the semiconductor material in a diffusion process step. The apertures formed in the passivating material for the introduction of the impurity characteristic of said one conductivity type may comprise the apertures through which the emitter and collector contacts extend, if any passivating material is formed within these two apertures during the formation of the emitter and the collector contact region, such passivating material being removed before the formation of the contacts.
Alternatively, and if passivating material is formed within these two apertures, possibly during the formation of the emitter and the collector contact region, such additional passivating material may be only partially removed to form the apertures for the emitter and collector contacts, possibly simultaneously with the formation of the aperture in the passivating layer for the base contact.
According to another aspect the present invention comprises a bipolar transistor manufactured by any one of the methods referred to above.
According to still another aspect the present invention comprises a method of manufacturing an integrated circuit device including a bipolar transistor, the method comprising at least all the constituent process steps of any one of the methods of manufacturing a bipolar transistor referred to above.
The provided supporting layer, the heavily doped layer and the epitaxial layer may extend throughout the body, comprising constituent laminae of a wafer shaped body.
Remote from the bipolar transistor, parts of the heavily doped material of said opposite conductivity type, and/or surface parts of the semicondutor material of said one conductivity type, where required to comprise parts of other circuit elements within the device, may be provided by introducing impurities, respectively, characteristic of said opposite conductivity type, and characteristic of said one conductivity type, simultaneously with the introduction of such impurities into the bipolar transistor, in the same process steps, the impurity characteristic of said opposite conductivity type being introduced into all the surface portions of the semiconductor material adjacent to the then major surface of the body at least including the surface of the epitaxial layer remote from the heavily doped layer, and the impurity characteristic of said one conductivity type being introduced selectively into appropriate surface parts of the semiconductor material. A plurality of grooves may be provided, each groove extending through both the epitaxial layer and the heavily doped layer, and encircling parts of both of the layers electrically isolated from the remainder of the semiconductor material of the body.
In an integrated circuit device manufactured by any such method the isolation means associated with the bipolar transistor conveniently may not be considered as inlcuding the whole of the associated groove, but instead the associated groove comprising part of common isolation means shared by adjacent circuit elements, the groove being intermediate between the bipolar transistor and other circuit elements.
According to yet another aspect the present invention comprises an integrated circuit device manufactured by any one of the methods of manufacturing an integrated circuit device, and referred to above.
The present invention will now be described by way of example with reference to the accompanying drawing which is a section of a bipolar transistor comprising one embodiment in accordance with the present invention.
The illustrated NPN bipolar transistor is formed on a wafer-shaped silicon semiconductor body with a substrate part initially wholly of P conductivity type, and having a heavily doped N + type layer 10, of uniform thickness, and formed by an initial diffusion of a donor impurity into one major surface of the substrate part, the unmodified region of the substrate part comprising a P type supporting layer 11. An epitaxial layer 12, of uniform thickness, is then deposited on the N + type layer 10, the epitaxial layer 12 being initially wholly of P + conductivity type.
In a known anisotropic etching step a 'V' section groove 14, square shaped in plan, is formed in the semiconductor body, to extend through both the epitaxial layer 12 and the
N + type layer 10, and into the supporting layer 11, the groove to encircle parts of these layers. The encircled parts of the layers 10 and 12 are electrically isolated from the remainder of the semiconductor body by the groove 14, and by the P-N junction between the P type supporting layer 11 and the N + type heavily doped layer 10. This process step comprises a photolithographic etching step, and employs a mask. Any resist employed in the anisotropic etching step is removed from the semiconductor body. The surfaces of the semiconductor body within the groove 14 are exposed by the groove.
In a non-selective diffusion process step an acceptor impurity is introduced into all the thus exposed surface portions of the semiconductor material adjacent to the then major surface of the body including the surface of the epitaxial layer 12, remote from the heavily doped layer 10. Thereby, these surface portions become heavily doped P + type material 16, where initially these surface portions were of P conductivity type, and either of the epitaxial layer 12 or of the supporting layer 11. The surface portions of the heavily doped layer 10 remain of N conductivity type.
During this diffusion process step a continuous layer of passivating material 18 is formed on the surfaces of the semiconductor body within the groove 14, and of the epitaxial layer 12 remote from the N + type layer 10.
In a second photolithographic etching step, employing a mask, and in a known manner, apertures 20 and 21 are provided through the layer of passivating material 18. A donor impuity is then diffused through the apertures 20 and 21, and selectively into the surface parts of the semiconductor body so exposed, the remaining parts of the passivating layer 18 comprising a barrier to prevent diffusion of i impurity therethrough. In the diffusion process step an N + type emitter 24 is formed beneath the aperture 20 in the passivating layer 18, and adjacent to a part of the surface of the epitaxial layer 12 remote from the N + type layer, and encircled by the groove. Further, an N + type collector contact region 25 is formed simultaneously beneath the aperture 21 in the passivating layer 18, and at a portion of the groove encircled part of the
N + type layer defining a portion of the groove. The collector contact region 25 extends into the epitaxial layer 12, and into the supporting layer 11. The groove encircled part of the N + type layer comprises the bulk of the collector.
The parts of the epitaxial layer 12 encircled by the groove 14 and of P conductivity com prise the transistor base.
After these diffusion process steps the heavily doped P + type material 1.6, in addition to being at the surface of the base remote from the N + type layer, at the surface of the base exposed by the groove, and at the portion 16' of the supporting layer 11 exposed by the groove, both is within the base, surrounding the emitter 24 as indicated at 16", and surrounding the parts of the collector contact region 25 extending into the epitaxial layer 12 and the supporting layer 11, as indicated at 16"'.
The portions of the base contiguous with the bulk of the N + type layer 10 comprise unmodified portions of the epitaxial layer 12.
Subsequently, any passivating material formed in the apertures 20 and 21 in the passivating layer 18 is washed out, employing a suitable solvent.
In a third photolithographic etching step, employing a mask, and in a known manner, a third aperture 26 is provided in the passivating layer, to expose a part of the surface of the base remote from the N + type layer. The exposed part of the base is of heavily doped material and comprises a base contact region 16"".
Alternatively, any additional passivating material formed in the apertures 20 and 21 in the passivating layer 18, when the emitter 24 and the collector contact region 25 are formed, is only partially removed to form apertures for the emitter and collector contacts, such extra passivating material possibly being removed in the same process step as the formation of the aperture 26 in the passivating layer exposing a portion of the base contact region 16"".
An initially continuous layer of resist material (not shown) is provided on the passivating layer 18, and within the apertures 20, 21 and 26. In a fourth photolithographic etching step, employing a mask, apertures are etched in the layer of resist material at least where emitter, collector and base contacts are required, these apertures exposing the apertures 20, 21 and 26 in the passivating layer. An initially continuous metal layer is then provided on the layer of resist material and within the apertures formed therein. The remaining parts of the resist material are removed, by employing known lift-off techniques, and the resist material carries with it the contiguous parts of the metal layer.The parts of the metal layer remaining comprise at least emitter, collector and base contacts, respectively, 27, 28 and 29, and the contacts respectively extending through the apertures 20, 21 and 26 in the passivating layer.
Alternatively, the emitter, collector and base contacts are formed by providing an initially continuous metal layer on the passivating layer, and within the apertures in the passivating layer. In a fourth photolithographic etching step, employing a mask, at least emitter, collector and base contacts are formed from the metal layer.
The bipolar transistor structure provided in the manner described above also includes means to isolate the bipolar transistor within the semiconductor body, the isolation means comprising the groove 14 coated with the passivating material.
In a particular embodiment of a bipolar transistor in accordance with the present invention, the heavily doped N + type layer 10 has a resistivity value of 0.01 ohm-cm., and in any such arrangement is required to have a resistivity value at most equal to 0.2 ohm-cm.
The epitaxial layer 12 initially is wholly of material having a resistivity value of 1 ohmcm., and in any such arrangement is required to have a resistivity value at most equal to 10 ohm-cms. The heavily doped P + type material 16 provided by the non-selective diffusion process step has a resistivity value of 0.01 ohm-cms., and in any such arrangement is required to have a resistivity value at most equal to 0.1 ohm-cms.
The N + type layer 10 has a thickness of two microns.
The epitaxial layer 12 has a thickness of two microns.
It is not essential that the N + type layer and the epitaxial layer have the same thickness, nor that either is of a uniform thickness.
Such an isolated bipolar transistor construction is advantageous in that it occupies only a small area of the contact-bearing major surface of the semiconductor body, the area being encircled by the part of the groove in the supporting layer 11, i.e. a part of this area being considered tio be within the groove.
Further, the bipolar transistor is advantageous, requiring only a few processing steps to be performed in its manufacture, and in particular requiring only four photolithographic etching steps, each employing a mask. The ability to use only four masks in manufacturing the transistor ensures that the method is especially advantageous.
The fewer the processing steps required to manufacture a bipolar transistor, and/or the smaller the area of the contact-bearing major surface of the semiconductor body occupied by the bipolar transistor, the better the manufacturing yields of the bipolar transistor.
The surrounding of the emitter 24 by the heavily doped P + type material 16" is advantageous in that it causes the gainbandwidth product of the transistor to be greater than otherwise would be the case.
In addition, because surface portions of the
N + type collector 10 and 25 are encircled by surface portions 16 and 16' of the heavily doped P + type material there are only low leakage currents across surface portions of the
P-N junctions associated with the collector.
Because of the provision of the heavily doped
P + type material there is prevented the inadvertent inversion of these surface portions to
N conductivity type, beneath the passivating
layer. Such a low leakage current is of the order of 10 pico-amperes for a P-N junction reverse baissed with a potential difference of
5 volts associated therewith.
Usually the passivating material is of silicon oxide, especially when the semiconductor material is of silicon.
The supporting layer 11 may be provided on another substrate part, the other layer being either of semiconductor material or of electrical insulating material.
Modifications of the method of manufacturing a bipolar transistor, other than those described above, are possible. Such modified methods usually will be advantageous, requiring only a few processing steps, and, in particular, requiring a few photolithographic etching steps, each employing a mask, and/ or being capable of providing bipolar transistors each occupying a small area of the contact-bearing major surface of the body in which it is formed.
The substrate part of the body, when comprising the supporting layer, may be wholly of electrical insulating material. With such an arrangement it is not essential for the groove to extend into the supporting layer, but merely that the groove extends through both the epitaxial layer and the heavily doped N + type layer.
In any such arrangement the electrical insulating material may be of sapphire and the semiconductor material, of the body, may be of silicon.
The N + type layer 10 may not be of semiconductor material of the substrate part of the body, irrespective of whether the supporting layer is of semiconductor material, or not. Thus, the N + type layer 10 may comprise an epitaxial layer deposited upon the supporting layer. The heavily doped N + type layer may comprise a first epitaxial layer, and the P - type epitaxial layer, referred to above, comprises a second epitaxial layer deposited upon the heavily doped N + type layer.Alternatively only a single, P - type layer may be deposited upon the supporting layer, and subsequently there is an initial additional introduction of a donor impurity, to form the heavily doped N + type layer intermediate between the supporting layer and the remaining, then unmodified, parts of the sole epitaxial layer, these remaining, then unmodified, parts being considered as the P - type epitaxial layer, referred to above, upon the heavily doped N + type layer.
Alternatively, only a single P - type epitaxial layer is deposited upon a portion of electrical insulating material of the substrate part of the body, and subsequently there is an initial, additional, introduction of the donor impurity, to form the heavily doped N + type layer spaced from both the electrical insulating material and the surface of the sole epitaxial layer remote from the electrical insulating material. The supporting layer is of semiconductor material, and although considered to be of substrate part of the body, comprises the remaining, then unmodified, parts of the sole epitaxial layer between the heavily doped layer and the electrical insulating material.
The remaining, then unmodified, parts of the sole epitaxial layer remote from such a supporting layer are considered as the P - type epitaxial layer, referred to above, upon the heavily doped N + type layer.
The introduction of an acceptor impurity into the then exposed surface portions of the epitaxial layer 12, in a non-selective diffusion process step, may be before the formation of the groove 14. Thus, the heavily doped P + type material 16 is not provided at the surface portions of the base exposed by the groove, nor surrounding the collector contact region 25 within the epitaxial layer, nor is the heavily doped P + type material 16' at the portion of a supporting layer 11 exposed by the groove.
The groove may be formed in any convenient way, for example, by electron bombardment, and the groove so provided may not be 'V'-shaped in section.
The heavily doped P + type material 1 6, and/or the N + type layer 10, and/or the
N + type surface parts, comprising the emitter 24 and the collector contact region 25, instead of being formed in a diffusion process step may be formed in any convenient way, for example, by ion impingement.
The passivating layer may be formed in any convenient way. Thus, for example, the passivating layer is provided only partially in a diffusion process step. Irrespective of the order of the groove etching step, and the formation of the heavily doped P + type material, in the method of manufacturing the transistor, a continuous layer of passivating material is required on the surface of the body including the surface of the P - type epitaxial layer remote from the N + type layer before the formation of the contacts, and usually before the formation of the emitter and the collector contact region. A provided passivating layer may be thickened at any stage in the manufacturing process, and/or, if apertured at any stage in the process may be reformed as a continuous layer.
The collector contact region 25 may extend to, and along part of, the surface of the epitaxial layer 12 remote from the N + type layer 10; and the collector contact 28 exclusively may be on the part of the collector contact region at the surface of the epitaxial layer remote from the N + type layer.
The conductivity types of each constituent part of the transistor may be reversed, in order to provide a PNP transistor.
Such bipolar transistors are particularly suit able to be embodied with monolithic semiconductor integrated circuit devices, in each such device there being embodied other circuit elements than the bipolar transistor, the bipolar transistor being isolated from the other circuit elements within the semiconductor body by the isolation means comprising the groove 14 coated with the passivating material 18. The isolation means associated with the bipolar transistor conveniently is not considered as including the whole of the associated groove 14. Instead the associated groove 14 comprises part of common isolation means shared by adjacent circuit elements, the groove 14 being intermediate between the bipolar transistor and the other circuit elements.
At least one bipolar transistor in accordance with the present invention, and of such an integrated circuit device, may be required to be isolated together with other circuit elements within the semiconductor body, the bipolar transistor being adjacent to, and including, only a part of the isolation means, comprising a groove coated with passivating material, to isolate the circuit elements within the semiconductor body. However, each such bipolar transistor is considered to have a construction in accordance with the present invention.
Usually any such integrated circuit device is formed in a wafer shaped semiconductor body, with all the constituent layers extending throughout the body, and comprising laminae, and the layers are not provided only in the parts of the semiconductor body in which the transistor is required. Additional grooves, to the groove 14 associated with the bipolar transistor, may be provided, each additional groove also extending through the epitaxial layer 12 and the N + type layer 10, and encircling parts of these layers electrically isolated from the remainder of the semiconductor material of the body. Remote from the bipolar transistor, there are provided parts of the heavily doped P + type material 16, and/or surface parts of the body of N + type. Such parts are provided where required to comprise parts of other circuit elements within the device.The impurities required to form these parts usually are introduced into the semiconductor material simultaneously with, and in the same process steps as, the introduction of the impurities into the bipolar transistor.
Hence, an acceptor impurity is introduced into all the surface portions of the semiconductor material adjacent to the then major surface of the body at least including the surface of the epitaxial layer remote from the N + type layer, and a donor impurity is introduced selectively into appropriate surface parts of the semiconductor material.
It is not essential that an integrated circuit device having a bipolar transistor in accordance with the present invention is formed in a semiconductor body in which the heavily doped layer and the epitaxial layer extend throughout the body.
An integrated circuit device having a bipolar transistor in accordance with the present invention may require to be manufactured by a method having more constituent process steps than are required for the manufacture of the bipolar transistor alone.
Claims (22)
1. A method of manufacturing a bipolar transistor comprising providing a body, with semiconductor material of the body at least including a heavily doped layer, with a resistivity value at most equal to 0.2 ohm-cm., and of one conductivity type, and an epitaxial layer on the heavily doped layer, the epitaxial layer being initially wholly of said opposite conductivity type and having a resistivity value at least equal to 10 ohm-cms., the heavily doped layer being provided on a supporting layer of the body, the epitaxial layer being remote from the supporting layer, in either possible order, forming a groove to extend through both the epitaxial layer and and the heavily doped layer, and to encircle parts of both of the layers electrically isolated from the remainder of the semiconductor material, and introducing impurity characteristic of said opposite conductivity type into all the surface portions of the semiconductor material adjacent to the then major surface of the body at least including the surface of the epitaxial layer remote from the heavily doped layer, subsequently introducing impurity characteristic of said one conductivity type both selectively into a part of the surface portion of the epitaxial layer remote from the heavily doped layer and encircled by the groove, to provide an emitter, and simultaneously and selectively into where a surface portion of the groove encircled part of the heavily doped layer defines a portion of the groove, to provide a collector contact region, the groove encircled part of the heavily doped layer comprising the bulk of the collector, and the parts of the epitaxial layer of said opposite conductivity type, and encircled by the groove, comprising the base, the introduced impurity characteristic of said opposite conductivity type providing heavily doped material, with a resistivity value at most equal to 0.1 ohm-cm., at least at the surface of the base remote from the heavily doped layer, and within the base and surrounding the emitter, at least the portions of the base contiguous with the bulk of the heavily doped layer comprising unmodified portions of the epitaxial layer, part of the heavily doped material at the surface remote from the heavily doped layer comprising a base contact region, during, and/or subsequent to, the introduction of the impurity characteristic of said opposite conductivity type into the semiconductor material, providing a layer of passivating material on the surfaces of the semiconductor material both within the groove, and of the groove-encircled part of the epitaxial layer remote from the heavily doped layer, and providing contacts, extending through apertures in the passivating layer, to each of the collector contact region, the base contact region, and the emitter.
2. A method as claimed in claim 1 in which the impurity characteristic of said opposite conductivity type is introduced after the formation of the groove, and into all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, heavily doped material of said opposite conductivity type being provided at the surface of the base exposed by the groove.
3. A method as claimed in claim 1 or 2 in which the supporting layer provided is of semiconductor material of said opposite conductivity type, and the provided groove extends into part of the supporting layer, when the impurity characteristic of said opposite conductivity type is introduced after the formation of the groove, and into all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, heavily doped material of said opposite conductivity type being provided at the portion of the supporting layer exposed by the groove..
4. A method as claimed in claim 1 or claim 2 having the provided supporting layer of an electrical insulating material upon which at least one epitaxial layer of semiconductor material is deposited.
5. A method as claimed in claim 4 in which the provided supporting layer is of sapphire, and the provided semiconductor material is of silicon.
6. A method as claimed in claim 4 or claim 5 in which the provided groove does not extend into part of the supporting layer.
7. A method as claimed in any one of the preceding claims in which the heavily doped layer of said one conductivity type comprises a first epitaxial layer deposited upon the supporting layer, and the epitaxial layer of said opposite conductivity type upon the heavily doped layer comprises a second epitaxial layer.
8. A method as claimed in any one of the preceding claims in which the provided collector contact region extends to, and along part of, the surface of the epitaxial layer remote from the heavily doped layer.
9. A method as claimed in claim 8 in which the provided collector contact exclusively is on the part of the collector contact region at the surface of the epitaxial layer remote from the heavily doped layer.
10. A method as claimed in any one of the preceding claims in which, before the introduction of the impurity characteristic of said one conductivity type, a continuous layer of passivating material is formed on all the surface portions of the semiconductor material both exposed by the groove, and of the epitaxial layer remote from the heavily doped layer, and apertures are formed through the passivating material, the impurity characteristic of said one conductivity type being introduced through these apertures into surface parts of the semiconductor material selected by the formation of the apertures, to form the emitter and the collector contact region, the remaining parts of the passivating material acting as a barrier to the introduction of the impurity into the parts of the semiconductor material covered thereby.
11. A method as claimed in claim 10 with the apertures formed in the passivating material for the introduction of the impurity characteristic of said one conductivity type comprising the apertures through which the emitter and collector contacts extend.
12. A method as claimed in claim 10 or claim 11 in which, after the formation of the groove, the impurity characteristic of said opposite conductivity type is introduced, in a diffusion process step, and the continuous layer of passivating material is formed at least partially during this diffusion process step.
13. A method of manufacturing an integrated circuit device including a bipolar transistor, and comprising at least all the constituent process steps of a method of manuafacturing a bipolar transistor as claimed in any one of the preceding claims.
14. A method as claimed in claim 13 in which the provided supporting layer, the heavily doped layer and the epitaxial layer extend throughout the body, comprising constituent laminae of a wafer shaped body.
15. A method as claimed in claim 14 in which, remote from the bipolar transistor, parts of the heavily doped material of said opposite conductivity type, and/or surface parts of the semiconductor material of said one conductivity type, where required to comprise parts of the other circuit elements within the device, are provided by introducing impu, rities, respectively, characteristic of said opposite conductivity type, and characteristic of said one conductivity type, simultaneously with the introduction of such impurities into the bipolar transistor, in the same process steps, the impurity characteristic of said opposite conductivity type being introduced into all the surface portions of the semiconductor material adjacent to the then major surface-of the body at least including the surface of the epitaxial layer remote from the heavily doped layer, and the impurity charteristic of said one conductivity type being introduced sefectively into appropriate surface parts of the serpicon- ductor material.
16. A method as claimed in claim 14 or claim 15 in which a plurality of grooves are provided, each groove extending through both the epitaxial layer and the heavily doped layer, and encircling parts of both of the layers electrically isolated from the remainder of the semiconductor material of the body.
17. A bipolar transistor manufactured by a method as claimed in any of claims 1 to 12.
18. An integrated circuit device manufactured by a method as claimed in any one of claims 13 to 16.
19. A method of manufacturing a bipolar transistor substantially as described herein with reference to the accompanying drawing.
20. A bipolar transistor substantially as described herein with reference to the accompanying drawing.
21. A method of manufacturing an integrated circuit device substantially as described herein with reference to the accompanying drawing.
22. An integrated circuit device substantially as described herein with reference to the accompanying drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8002703A GB2068168B (en) | 1980-01-26 | 1980-01-26 | Bipolar transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8002703A GB2068168B (en) | 1980-01-26 | 1980-01-26 | Bipolar transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2068168A true GB2068168A (en) | 1981-08-05 |
| GB2068168B GB2068168B (en) | 1983-08-17 |
Family
ID=10510920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8002703A Expired GB2068168B (en) | 1980-01-26 | 1980-01-26 | Bipolar transistors |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2068168B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296403A (en) * | 1990-01-31 | 1994-03-22 | Research Development Corp. Of Japan | Method of manufacturing a static induction field-effect transistor |
-
1980
- 1980-01-26 GB GB8002703A patent/GB2068168B/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5296403A (en) * | 1990-01-31 | 1994-03-22 | Research Development Corp. Of Japan | Method of manufacturing a static induction field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2068168B (en) | 1983-08-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |