GB2063023A - Code translator - Google Patents

Abstract

When messages sent via a transmission line in a ternary line code have to be translated into a binary code, the code translator has to be able to detect code violations. The ternary coded message is made up of three-element ternary words each of which corresponds to a four-bit binary word, and four different ternary alphabets are used, choice between the alphabets to be used for each word being dependent on the need to keep disparity as low as possible. To detect code violations, the translator uses a logic circuit (LS) implemented with a PROM. This receives the ternary words from line error shift register (SR1, SR2) and a buffer memory (Z1), and supplies the binary words to an output via another buffer memory (Z2) and another shift register (SR3). The logic circuit (LS) determines, under control of the received ternary word and outputs (01-02) from the buffer memory (Z2) dependent on a previous word, the indication as to the alphabet to which the ternary word being dealt with belongs. If the received ternary word is found not to correspond to the predicted code alphabet an error indication is given. <IMAGE>

Description

SPECIFICATION Code translator This invention relates to a code translator for translating signals coded in a restricted disparity ternary code into binary-coded signals, the binary/ternary coding being based on different alphabets, with error-checking means and means for word synchronization.

A code translator of this kind is known, for example, from "Telecom Report 2" (1979), supplement "Digital-Überwachungstechnik", page 102. This code translator, referred to there as "MMS-43 decoder", reconverts the line code, mostly a ternary code, into binary signals at the end of a digital transmission path.

A code translator of the same kind but for a different code from the 4B3T code group is disclosed in British Patent No. 1250924 (D.B.Waters et al 3-2).

In the so-called 4B3T codes, the binary digital signals to be transmitted are combined into 4-bit binary words which are translated into 3-digit ternary words according to a specific rule. Steps are taken to see that the consecutive disparity of the transmitted signals, also referred to as "consecutive digital sum" or "accumulated disparity", does not exceed a predetermined value In the MMS-43 code, a special type of the 4B3T code, this is done by translating the applied binary word into a 3-digit ternary word according to one of four different code alphabets depending on the disparity of the previously translated ternary word.

To check for code errors at the receiving end, known decoders continuously compute the "consecutive digital sum" by adding the word disparities of the received ternary words and inferring, from given criteria, code errors caused either by transmission errors or by an out-of-synchronism condition of the decoder. Such an adder for determining consecutive disparity requires a considerable amount of circuitry.

Accordingly an object of the invention is to provide a code translator of the above kind whose circuit is simpler than that of the known code translator.

According to the present invention there is provided a code translator for translating signals coded in a restricted-disparity ternary code into binary-coded signals, the binary/ternary coding being based on the use of different alphabets, with error-checking means and means for word synchronization, wherein the error-checking means predetermine the code alphabet to be expected forthe next ternary word on the basis of the ternary word just received and of the designation of a predetermined code alphabet, and wherein the error-checking means produces an error signal if the ternary word is not contained in the predetermined code alphabet.

An embodiment of the invention will now be described with reference to the accompanying drawing, which is a block diagram of a code translator embodying the invention.

In a receiving generator (not shown), ternary signals arrriving on the transmission line are split up into the positive components T+ and negative components T- in the known manner. At the same time, the line clock LT iS derived.

For serial-to-parallel conversion, the positive components T+ and the negative components T- are entered into three-stage shift registers SR1 and SR2, respectively, under the control of the line clock LT. If a digit of a received ternary word has the value 0, both T+ and T- are also 0, while a pulse of the line clock LT advances the two shift registers SR1 and SR2. The received ternary word appears at the parallel output of the two shift registers in binary representation, the first ternary digit being represented by TO, the second by T1, and the third by T2. If, for example, the first digit has the value "+" then TO+ = 1 and TO = 0. TO+ and TO must never be 1 at the same time; the same applies to T1 and T2.The following example is to explain this representation of a ternary word in more detail: T2+ Ti+ TO+ T2- T1- T0- + = O = 1 0 0 0 1 0 The ternary word so represented is fed, in parallel form and under the control of the word clock, from the parallel outputs of the shift registers SR1 and SR2 into a buffer memory Z1 whose parallel outputs are coupled to inputs A7 to A2 of a logic circuit LS. The word clock applied to the clock input CZ of the buffer memory Z1 is obtained by dividing the line clock LT by 3, because a word consists of three digits. The division is performed in a divider T, whose input is fed with the line clock Latvia a clock-shift unit TP.The clock-shift unit, which is controlled by a clock-shift signal, as will be explained later, shifts the phase of the word clock appearing at the output of the divider T by one period of the line clock if the code translator determines that the word synchronization is not correct, i.e., if it determines that at the receiving end, the serial ternary digits are being arranged in groups of three in a wrong assignment. The criteria for detecting a wrong word synchronization are provided by the logic circuit LS as will be explained below.

After a pulse of the word clock, a particular combination of binary digits is applied to the parallel inputs A7 to A0 of the logic circuit LS until the occurrence of the next pulse of the word pulse.

The binary digits of the inputs A7 to A2 are delivered by the parallel outputs of the buffer memory Z1 while the binary digits Al and A0 are the logic output signals 02 and 01 of the logic circuit arrangement LS, delayed by one work-clock period in a buffer memory Z2. The parallel outputs 08 and 03 of LS provide the binary word for the ternary word at the input of the translator according to the code used. The binary word, like the 2-bit word at the outputs 02 and 01, is written into the buffer memory Z2 on the occurrence of the next pulse of the word clock, and the outputs Q8 to Q1 of this memory Z2 provide the binary digits which appeared at the correspondingly numbered outputs 08 to 01 of the logic circuit LS.From the outputs Q8 to Q5, the 4-bit binary word is applied to the parallel inputs B3 to BO of a four-stage shift register SR3 for parallel-to-serial conversion, and transferred into this shift register on the occurrence of the next word-clock pulse at the set input PS of this shift register. Under the control of the bit clock, which is derived from the word clock by quadrupling the frequency of the latter in a frequency multiplier FV and applied to the shift input S of the shift register SR3, the 4-bit binary word is read out of the shift register in serial form, so that the binary data bit stream BS is obtained.

The signal appearing at the output 03 of LS, and hence at the output Q3 of Z2 is an error signal KF. As will be explained below, this error signal is produced whenever it appears to the code translator at the receiving end that the applied ternary word to be translated does not conform to the rules of construction of the code used, i.e., that the code has been violated. Such code errors may be due either to transmission errors on the line, so that the transmitted code arrives falsified, or to the word clock of the code translator or decoder at the receiving end being out of synchronism with the word clock of the coder at the transmitting end. It is possible to distinguish between digital transmission zrors and a loss of synchronization based on the rate of occurrence of code-error signals. This is done in the unit labeled "error rate detector".If the error rate exceeds a predetermined value, an out-of-synchronization condition is assumed.

The error rate detector then delivers a clock shift signal which causes the word clock to be shifted in phase by one line-clock period in the clock-shift unit TP, as mentioned above. To accomplish this phase shift of the word clock by one line-clock period, the clock-shift unit TP eliminates one clock pulse from the clock-pulse train applied to the divider T. The error rate counted in the error rate detector is passed through a bus to an error-rate display and displayed there.

As far as described above the novel code translator is essentially the same as known translators, including that disclosed in our above-mentioned Patent. The essential difference lies in the fact that the novel code translator has no adder for determining the so-called accumulated disparity or the "consecutive digital sum", and no other circuit units dependent thereon.

As a comparison between the input signals and the output signals of the logic circuit LS shows, the error signal KF is only produced in response to the applied ternary word and to a two-bit word (A1, A0) which was produced (02,01) one word-clock period earlier by the logic circuit LS itself.

The operation of the logic circuit LS will now be explained with the aid of Tables and examples. The explanation is based on the code known as "MMS-43 code", but the invention is also applicable to other codes and limited neither to the MMS-43 code nor the group of 4B3T codes.

The MMS-43 code, which belongs to the group of 4B3T codes, has four code alphabets S1, S2, S3 and S4, which are used successively to encode the next binary word according to a given rule, depending on the ternary word being transmitted.

The coding according to the four code alphabets is shown in Table I.

TABLE I Binary Word Ternary word in the code alphabet S1 S2 S3 S4 0 0 0 0 + 0 + 0 - 0 0 - 0 0 - 0 0001 0 - + 0 - + 0 - + 0 - + 0010 + - 0 + - 0 + - 0 + - 0 0 0 1 1 0 0 + 0 0 + 0 0 + - - 0 0100 - + 0 - + 0 - + 0 - + 0 0101 0 + + - 0 0 - 0 0 - 0 0 0 1 1 0 - + + - + + - - + - - + 0 1 1 1 - + 0 - 0 + - 0 + - 0 + 1000 + 0 0 + 0 0 + 0 0 0 - 1001 + - + + - + + - + - - 1010 + + - + + - + - - + - 1011 + 0 - + 0 - + 0 - + 0 1100 + + + - + - - + - - + 1101 0 + 0 0 + 0 0 + 0 - 0 1 1 1 0 0 + - 0 + - 0 + - 0 + 1111 + + 0 0 0 - 0 0 - 0 0 To explain the rule of construction of the code, the term "word disparity" should be introduced. The word disparity gives the sum of numerical values which are assigned to the ternary digits of a ternary word as follows: + = +1 0 # 0 - # -1 Thus, the ternary word + + -,for example, has the word disparity + 1.

It can be seen from Table I that, aside from the zero disparities; (a) S1 contains only positive disparities, (b) S2 contains a slight majority of positive disparities, (c) S3 contains a slight majority of negative disparities, and (d) S4 contains only negative disparities.

To limit the line disparity, coding at the transmitting end is performed according to the following rule, which must be explained to understand the decoder at the receiving end.

The rule of construction can be expressed as: Sn+1 .= D(Wn) +Sn, where Sn is the designation of the code alphabet by which the applied binary word is encoded into a ternary word Wn, D(Wn) is the word disparity of the ternary word Wn, and n+1 is the code alphabet according to which the next binary word has to be encoded.

If, for example, the code alphabet S2 is on, and the binary word 0 1 0 1 has to be encoded, the latter is translated into the ternary word - 0 0, and the next binary word will be encoded according to alphabet S1, because the transmitted ternary word - 0 0 has the word disparity -1. If, for example, the binary word 11 0 0 has to be encoded, the ternary word + + + will be transmitted, and the next ternary word will be taken from the code alphabet S4. Thus the line disparity always remains restricted.

At the receiving end, the decoder must not only convert the received ternary word back to the binary word but also detect code errors. The only way to do this is to check whether the received ternary word conforms to the rule of construction of the code; if it does not, this points to an error.

In the present arrangement, the alphabet according to which the next ternary word is to be coded is determined by the decoder, particularly by the logic circuit LS, on the basis of the applied ternary word and the alphabet turned on, and whenever a received ternary word is not contained in the predetermined alphabet, the decoder delivers an error signal KF.

The relations underlying this logic will now be explained with the aid of Table II.

TABLE II Disparity Ternary Code alphabets Binary word word S1 (Sn) S2 (Sn) S3 (Sn) S4 (Sn) word D = +3 + + + S4 S4 (KF) S4 (KF) S4 (KF) 1 1 0 0 ( + + # S3 S3 (KF) S3 (KF) S3 (KF) 1 1 1 1 ( D = +2 ( + # + S3 S3 (KF) S3 (KF) S3 (KF) 0 0 0 0 ( ( # + + S3 S3 (KF) S3 (KF) S3 (KF) 0 1 0 1 ( + + - S2 S3 S3 (KF) S4 (KF) 1 0 1 0 ( ( + # # S2 S3 S4 S4 (KF) 1 0 0 0 ( ( + - + S2 S3 S4 S4 (KF) 1 0 0 1 ( D = +1 ( # + # S2 S3 S4 S4 (KF) 1 1 0 1 ( ( # # + S2 S3 S4 S4 (KF) 0 0 1 1 ( ( - + + S2 S3 S3 (KF) S4 (KF) 0 1 1 0 ( + # - S1 S2 S3 S4 1 0 1 1 ( ( + - # S1 S2 S3 S4 0 0 1 0 ( ( # + - S1 S2 S3 S4 1 1 1 0 ( D = # ( # # # S1 S2 S3 S4 0 0 0 0 ( ( # - + S1 S2 S3 S4 0 0 0 1 ( ( - + # S1 S2 S3 S4 0 1 0 0 ( ( - # + S1 S2 S3 S4 0 1 1 1 ( + - - S1 (KF) S2 (KF) S2 S3 1 0 1 0 ( ( # # - S1 (KF) S1 S2 S3 1 1 1 1 ( ( # - # S1 (KF) S1 S2 S3 0 0 0 0 ( D = -1 ( - + - S1 (KF) S1 S2 S3 1 1 0 0 ( ( - # # S1 (KF) S1 S2 S3 0 1 0 1 ( ( - - + S1 (KF) S2 (KF) S2 S3 0 1 1 0 ( # - - S2 (KF) S2 (KF) S2 (KF) S2 1 0 0 0 ( D = -2 ( - # - S2 (KF) S2 (KF) S2 (KF) S2 1 1 0 1 ( ( - - # S2 (KF) S2 (KF) S2 (KF) S2 0 0 1 1 D = -3 - - - S1 (KF) S1 (KF) S1 (KF) S1 1 0 0 1 This Table is in essence a rearrangement of Table I, and, also, contains the above-explained rule of construction of the MMS-43 code.It shows to which code alphabet a received ternary word belongs, and specifies that alphabet in the individual columns which is expected for the next ternary word when a particular ternary word (which specifies the row) is received and when a particular alphabet (which specifies the column) is on. In addition, it contains for each ternary word the binary word unambiguously assigned thereto.

Aternaryword is contained in an alphabet if the column for this binary word, which column is designated by this alphabet, contains no designation KF.

For example, the ternary words with zero disparity (D=O) are contained in each alphabet, while the ternary words with the disparities D=+3 and D=+2 are contained only in 81, and the ternary words with D=-2 and D=-3 are contained only in S4.

Different examples will now illustrate the operation of the logic circuit arrangement LS.

Example 1 If the decoder has turned on the code alphabet S2, for example, i.e., it expects the received ternary word to be coded according to 82, and if the word + + - is received, the decoder detects no error, because + + - is contained in S2 (cf. Table I), and it expects the next word to be coded according to S3. The binary word 1 0 1 0 will be delivered.

Example 2 If the decoder has turned on the code alphabet S3 and receives the ternary word + + +, it delivers an error signal (KF), because this word is not in S3. It turns on S4 as the alphabet for the next ternary word; this is based on the assumption that the ternary word +++ was transmitted correctly, so that the coder had definitely turned on the alphabet S1 during this word. This predetermination on the basis of a ternary word occurring only in a single code alphabet is safe. If the next word is not in the alphabet thus predetermined, the error then detected indicates either that the word + ++ + was a wrongly received word or that the next word was received wrongly.

The occurrence of words found only in a single alphabet and thus permitting safe predetermination forms the basis for the detection of code errors by the logic circuit embodying the invention.

Example 3 Let us now consider the case where the predetermination may not be safe.

Assume that the decoder has turned on S3, and that the ternary word - + is being received.

This word - + + is not in S3 (cf. Table I), so that an error signal (KF= 1) is delivered. With regard to the predetermination of the next code alphabet, the decoder faces the problem of not "knowing" from which alphabet the coder has taken the received word. It may have been S1 or S2 (Table I). Assuming that it was S2, the decoder remains on S3, which is expected for the next word if - + + was received, starting from S2.

It is thus clearly apparent from Table II which output signals are delivered by the logic circuit arrangement LS in response to which input signals. Thus it is obvious that this logic circuit arrangement can be implemented in a simple manner using simple logic elements, such as AND and OR gates.

Alternatively, the logic circuit arrangement can be implemented with a programmable read-only memory (PROM).

The designations of the code alphabets can be represented in binary notation as follows: Al A0 (02) (01) S1: 0 1 S2: 1 0 S3: 1 1 S4: 0 0 where Al, A0 are the inputs of LS for the two-bit word for the predetermined code alphabet, and 02, 01 are the outputs of L8 for the two-bit word for the code alphabet predetermined for the next ternary word. In the event of a code error, an error signal with the logic level KF=1 appears at the output 03 of LS.

The following shows an example of a binary representation of input and output signals of the logic circuit arrangement LS: Input: received binary word Code alphabet 81 Binary representation Binary representation T2+ T1+ T0+ T2- Th ~ T0- A7 A6 A5 A4 A3 A2 Al A0 0 1 1 1 0 0 0 1 Output: binary word AL KF Code alphabet S2 Binary representation 08 07 06 05 04 03 02 01 (B3) (B2) (B1) (BO) 0 1 1 0 0 0 1 0 The signal AL is an alarm signal which is produced (AL=1 ) if the binary representation of the ternary word is contradictory, e.g., if T2+ and T2- are simultaneously at logic 1, i.e., in a condition which must not occur, as mentioned above.

Finally, it should be noted that, as already indicated for Example 2, the reception of words with an extreme disparity +3, +2, -3, -2, i.e., words to be clearly assigned to one particular code alphabet, forms the basis for the detection of code violations by the logic circuit LS of the decoder. Only by such words can the receiver be unambiguously informed of the respective valid code alphabet, so that it can detect code violations. In other words, such words bring about the agreement between the code alphabet expected by the decoder and the code alphabet actually used by the coder. A prerequisite to this is, however, that these words do not result from a transmission error. If these words result from a transmission error, the agreement does not occur so that - either immediately or during one of the next words - a code error is detected.

The prerequisite to the fact that the words to be clearly assigned to a single code alphabet are received at a sufficient rate is fulfilled if, at the transmitting end, the binary signals are scrambled before being converted to ternary words, so that these words occur frequently enough to permit reliable statements to be made about the frequency of code violations during the conversion into the binary code.

Claims (6)

1. A code translator for translating signals coded in a restricted-disparity ternary code into binary-coded signals, the binary/ternary coding being based on the use of different alphabets, with error-checking means and means for word synchronization, wherein the error-checking means predetermine the code alphabet to be expected for the next ternary word on the basis of the ternary word just received and of the designation of a predetermined code alphabet, and wherein the error-checking means produces an error signal if the ternary word is not contained in the predetermined code alphabet.

2. A code translator as claimed in claim 1, and wherein the error-checking means is a logic circuit whose inputs are fed with a received ternary word with the designation of the predetermined alphabet in parallel form, and whose outputs deliver, in parallel form, the binary word for the ternary word, together with the designation of the alphabet expected for the next ternary word and with an error signal which indicates whether or not a code error was detected.

3. A code translator as claimed in claim 2, wherein the ternary word to be translated into the binary code is fed to the inputs of the logic circuit arrangement in binary representation, and wherein the logic circuit checks whether the binary representation is contradictory, and produces an alarm signal if a forbidden binary-value combination of the individual bits occurs.

4. A code translator as claimed in claim 2 or 3, wherein the logic circuit is implemented with a programmed read-only memory.

5. A code translator as claimed in any one of the preceding claims, and wherein the means for word synchronization counts the rate of occurrence of the error signals produced and, when a predetermined threshold is exceeded, shifts the phase of the ternary-word clock by one period of the line clock.

6. A code translator substantially as described with reference to the accompanying drawing.