GB2060319A - Power feed arrangements and circuits and components suitable therefor - Google Patents

Abstract

A power feed arrangements for use with another like arrangement in feeding power from opposite ends of a transmission path. Signal-sending means (21) sends along the transmission path (L1) a signal indicating that a power supply generator in the arrangement shortly to feed power to the transmission path. Signal-receiving means (24) receives a similar signal from the like arrangement and responds by causing its generator to feed power to the transmission path. A monitoring circuit (20A) compares the output of the arrangement with a desired value and stops the generator feeding power if the actual output does not attain a value within a predetermined range of the desired value within a predetermined time interval. The power supply generator may include two or more switched-mode power converters (7, 8, 9, 10) and have an output which is adjustable over a range. A lower part of the range is provided by adjustment of one converter, the other(s) producing no output, a higher part by adjustment of the other (or next) converter with the first converter producing a fixed proportion of its full output, and soon. <IMAGE>

Description

SPECIFICATION Power feed arrangements and circuits and components suitable therefor This invention relates to power feed arrangements for communication systems and to circuits and components suitable for use in such power feed arrangements. The communication systems may be signal-transmitting cables having repeaters for compensating for attenuation of the signal and the power fedd may be for energizing the repeaters, the energizing current flowing along the same cable as the signals.

British Patent Specification No. 1,370,672 describes a power feed arrangement for communication systems. This prior arrangement is concerned with feeding power to a coaxial cable system wherein the current flow across a short circuit is limited to 50 milliamps for the safety of personnel maintaining the system. To enable relatively high currents along the line to be developed while at the same time ensuring that short circuit currents can be limited, generators are arranged backto-back such that two opposed current flow loops are set up from either end of the system when a short circuit occurs.The following procedure is used at start-up in the prior arrangement: On starting up a start signal is sent from the near end to the far end, and the near end generator is energized and feeds into a dummy load; on receipt of the start signal the far end generator is energized and feeds into a dummy load, and an acknowledge signal is sent to the near end; when both the start signal and acknowledge signal have been detected at both ends a further signal is set which causes both generators to be connected to line.

This start-up procedure is satisfactory as regards operation and safety but the dummy loads and mechanical relays associated with them add significantly to the cost of the arrangement.

DC-DC power converters are suitable for use as constant current feed generators in the prior arrangement but a difficulty is that at low load power converters tend to become inefficient. A further difficulty arises with a switched mode DC to DC converter used as a constant current source when running at low output voltage (compared to full output voltage). This is because such a converter has a relatively fixed voltage step up or step down ratio, matched to the maximum output voltage required, and for lower voltages the converter must be switched on for only part of each cycle so that the average output voltage is as required. Firstly the output waveform is harder to smooth because it starts as a series of relatively short pulses of power, each far greater than the average output power, separated by intervals of no power at all.By comparison, at high output power, the powers of the pulses is not so great in proportion to the output power and there is more nearly a continuous flow of power. Secondly, because the converter is capable of much greater voltage than is required at low output, any slight variation in the signal controlling the voltage will produce a burst of excess voltage which as a proportion of the required voltage is much greater at low output than at medium or high output. Special attention is then required to ensure that the whole control system is not unstable. This problem does not arise with constant voltage output as a change in load produces a change in current and change of pulsewidth only needs to make up for slightly increased current consumption.

Transformers and inductors used in such DC-DC converters can critically affect the performance (especially efficiency) of the feed generators and it is therefore important to provide wound components of high efficiency.

According to a first aspect of the invention, there is provided a power feed arrangement for use in conjunction with another like power feed arrangement in feeding power from opposite ends of a transmission path cdnnecting two terminal stations, the power feed arrangement including: a power supply generator, signal-sending means to send by way of the transmission path a signal indicating that the generator is shortly to feed power to the transmission path, signal-receiving means to receive from the transmission path the signal sent by the signal-sending means of a like arrangement and operative to respond to the received signal by initiating the feeding power to the transmission path by the generator, and a monitoring circuit operative to compare the output of the generator with a desired value of output and operative to stop the generator feeding power to the transmission path if the actual output does not attain a value within a predetermined range of the desired value within a predetermined time interval. The monitoring circuit may also stop the generator output when it ceases to be maintained within a predetermined range of the required value for longer than a predetermined time.

The signal-sending means may be actuable by, separately, a start signal from a manually-operable switch and a signal from the signal-receiving means.

A monostable multivibrator triggered by the manually-operable switch may be provided to define the said predetermined time interval.

The power feed arrangement may further include a second signal-receiving means to detect the signal sent by the signal-sending means of the one power feed arrangement and a logic circuit can be provided to inhibit initiation of power feeding in the absence of detection of the last-mentioned signal by the second signal-receiving means.

The, or each, signal-receiving means and the monitoring circuit may have a respective delay circuit associated therewith.

According to a second aspect of the invention, there is provided a power supply arrangement including first and second switched-mode power converters, wherein the output of the power supply arrangement is taken from both converters and is adjustable over a range, a lower part of the range being provided by adjustment of the first converter with the second converter arranged to contribute no power and a higher part of the range being provided by adjustment of the second of the converters with the first converter producing a fixed proportion or all of its full output. The lower and higher parts of the range may overlap.

N power converters may be provided, N being an integer greater than two, and the range divided into N parts, the lowest part of which is provided by adjustment of a first converter with the other converters contributing no power, the second part of which is provided by adjustment of a second converter with the first converter producing a fixed proportion or all of its full output, the third part of which is provided by adjustment of a third converter with both the first and second converters producing fixed proportion or all of their full output, and so on.

There may be overlaps between parts of the range, and if so the control circuit for adjusting the output power of the arrangement would have filtering to avoid instability, particularly near the boundary between two parts of the range. In an overlap region the lower converter has a greater sensitivity to control than the upper converter due to the use of a non-linear ramp so that the output of the upper converter changes little between the start of the overlap region and its end when the lower converter is producing its full output.

The arrangement is particularly advantageous in the case where the power supply arrangement is arranged as a constant current generator. The switched-mode power supply circuits may each have a respective control circuit. A common source of drive waveform may be provided to define the times at which power is switched on and off at full pulse width operation. Each control circuit may include a comparator circuitto compare the instantaneous value of a signal derived from the output of the arrangement with the instantaneous value of a repetitive signal to define that instant at which power is to be switched if the particular power supply circuit is to operate at less than full power.

The signal may comprise a ramp waveform which may be non-linear and have an initial portion of steep slope, relative to the remainder of the ramp. The ramp may alternatively have an inverse exponential characteristic. The ramp generator may employ a resistance-capacitance (RC) network to generate the inverse exponential characteristic. Each ramp waveform may include a periodic component derived from a common ramp generator superimposed on a direct component peculiar to the particular comparator circuit. Three or more comparator circuits may be provided and arranged so that the range of operation of one overlaps the range of operation of the next.

A resistive potential divider circuit may be used to generate the direct components.

The drive waveform may be derived from a clock pulse generator and the control circuit include means a charge a capacitance means of an RC network in response to a waveform derived from the clock pulse generator, thereby to produce an inverse exponential ramp waveform.

Each power converter may include a transistor switching circuit and the means to drive the transistors may include a monostable multivibrator arranged to define an OFF period for each switching cycle to ensure that the bases of the transistors are discharged.

The power supply arrangement may be a DC-DC converter in which each power converter circuit has a respective output transformer connected to a respective rectifier circuit and the outputs of the rectifier circuits are connected in series and/or parallel to provide a desired output.

Resistance means may be connected in series with the output of the arrangement and used to provide a feedback signal to comparator circuits so that the power supply arrangement operates as a substantially constant current generator.

According to a third aspect of the invention, an inductive component comprising a winding on a magnetic core is characterised in that the winding comprises spirally wound conductive strip material.

The strip may be spirally wound on a coil former, the width of the strip being substantially equal to the available winding width of the former.

The inductive component may be a transformer having another winding of wire, the overall width of the other winding being substantially equal to the width of the strip.

The strip winding may be insuiated by means of an enamel coating or by means of a strip of insulating material such as paper.

Connection may be made to the strip by means of wires arranged transverse to the longitudinal axis of the strip and projecting beyond the strip, the wires being soldered across the width of the strip.

Two strips may be joined and placed to form a bifilar winding.

By way of example only, an illustrative embodiment of the invention will now be described with reference to the accompanying drawings, in which: FIGURE 1 is a block schematic diagram of a power feed arrangement for a communication system; in one example four such arrangements are used together.

FIGURE 2 is a circuit diagram of a ramp generator and comparators used in the power feed arrangement; FIGURE 3 shows the output waveform of the ramp generator; FIGURE 4 is the circuit diagram of a power converter used in the power feed arrangement; FIGURE 5 is a schematic illustration of a winding used in a transformer in the power feed arrangement; FIGURE 6 is a block schematic diagram of part of control logic of the power feed arrangements; and FIGURE 7 shows waveforms relating to the control logic.

Referring to Figure 1, a power feed arrangement or equipment for a communication system is illustrated. Four such power feed equipments are to be used to feed coaxial cables in place of GEA, PF1A; GEA', PF2A; GEB, PF1B; and GEB', PF2B described in British Patent Specification 1,370,672.

Certain parts of the power feed equipment of Figure 1 are, however, common to its associated power feed equipment as will be explained hereafter. The reader should study Specification 1,370,672 for further information on the intended application of the present power feed arrangement.

A coaxial cable L1 is shown being fed by the power feed equipment and has inner and outer conductors C and D respectively.

A control logic circuit 1 is provided to control the operation of the power feed equipment, particularly start-up in association with the other three power feed equipments mentioned above.

The power feed equipment includes four identical power converters 2, 3, 4 and 5 having their outputs serially connected. The power converters 2, 3, 4 and 5 are used for DC-DC conversion and are controlled by drive pulses from respective steering logic circuits 7, 8, 9 and 10. The steering logic circuits are identical and each comprises a pair of NAND gates. Each steering logic circuit receives an output from a respective one of four comparators 11, 12, 13 and 14 and receives outputs from a common drive logic circuit 6. An error amplifier 1 5 has its output commonly connected to the noninverting inputs of the comparators 11, 12, 1 3 and 14, to the inverting inputs of which a ramp generator and a 2-microsecond delay circuit 1 6 has its output commonly connected.The ramp generator and delay circuit 1 6 is under control of a clock circuit 1 7. A connection is provided from the ramp generator 1 6 to the drive logic circuit 6.

The outputs of the power converters 2, 3, 4 and 5 are connected to a smoothing circuit 18 and in which they are serially-connected after smoothing. The output of the smoothing circuit is connected through a current monitoring network 20 and a combining circuit 19 to the conductors of the cable L1.

The combining circuit 1 9 is provided to permit power and tones to be connected to the cable L1 without the power converters shorting out the tones or the power destroying the circuits used to generate the tones. The current monitoring network 20 comprises a serially-connected resistor (shown schematically) and the voltage drop across this resistor is connected as an input signal to the error amplifier 1 5. The error amplifier 1 5 also receives the output of a reference voltage source 25, the two inputs to the error amplifier being connected in parallel but in opposite senses. A power separating filter (not shown) is used to combine or separate the traffic signal and the power feed to or from the line.

The current monitoring network 20 is connected to a current monitor circuit 20A arranged to receive a reference input from a voltage reference circuit 20B.

An oscillator 21 is provided to generate a control tone and is connected to the combining circuit 1 9 and is under the control of the control logic circuit 1. A detector 23 for locally-generated control tone has its input connected to the combining circuit 1 9 and its output connected to the control logic circuit 1. A further detector 24, for remotely-generated control tone, is similarly connected.

A more detailed description of some parts of the arrrangement will be given shortly but first a brief discussion of the operation of the arrangement will be given.

As mentioned above, the control logic circuit controls the start-up procedure of the power feed arrangement. In use, a first control tone is initially sent from the rear end to the far end of the communications system, on receipt of this signal an acknowledge control tone is returned. These tones are then normally sent continuously thereafter. On receipt of the acknowledge signal a timing procedure is started and the current generators, which are permanently connected to the cable, are then energized.

The timing is arranged so that the generators are energized at the same instant. If either generator does not produce the required current within 100 milliseconds the respective means sending the tone is inhibited causing both generators to be de-energized simultaneously.

Control of the DC-DC conversion is operative to maintain a constant current feed to the cable and output power is controlled by varying the ON/OFF switching ratio in each power converter separately. The number of power converters in operation at any instant is adjusted according to the power demand.

Referring now to Figure 2, the ramp generator 16 and comparators 11, 12, 13 and 14 are shown in more detail, component values and type numbers being marked in the drawing. The ramp generator 16 comprises an integrated circuit monostable multivibrator 1C1 having the output of the clock 17 applied to its B input. The Q output of multivibrator IC1 is connected to one end of a resistor R1 and to the cathode of a diode Dl. The anone of diode D1 is connected to one end of a resistor R2 and to one end of a resistor R3. The other ends of resistors R1 and R2 are connected to earth and the other end of resistor R3 is connected to one end of a capacitor C1. The other end of capacitor C1 is connected to earth. The Q output of IC1 is also connected to the drive logic circuit 6.

The monostable multivibrator IC1 is employed to provide 2 microsecond wide pulses at the clock frequency to switch off those power transistors in the power converters 2, 3, 4 and 5 which are conducting and ensure that their bases are discharged. This arrangement ensures that the power transistors are OFF for at least 2 microseconds in each half-cycle. These pulses are taken from the Q output of the multivibrator IC1 and utilised in the drive logic 6. The Q output of the multivibrator IC1 is also used to generate a ramp for controlling the ON/OFF ratio of the power converters.After a trigger pulse is received at the B input of multivbrator IC1 from the clock circuit 1 7, the Q output changes from earth potential to -5 volts for 2 microseconds during which time the capacitor C1 is charged through the diode D1 and resistor R3. At the end of 2 microseconds the Q output reverts to earth potential and the capacitor C1 discharges through resistors R2 and R3. Figure 3 shows the waveform of the potential across capacitor C1 and the clock period is marked as T.During each 2 microsecond pulse from IC1 the capacitor C1 is charged to approximately4 volts and thereafter the capacitor discharges with an expotential decay characteristic towards zero volts until the capacitor is charged again by the next 2 microsecond pulse.

The output of the error amplifier 1 5 is commonly connected to the non-inverting inputs of comparators 11, 12, 13 and 14 which each comprise a type Lem311 differential amplifier. Seven resistors R4, R5, R6, R7, R8, R9 and R10 are connected in series in the order given and --10 volts is applied to the free end of resistor R10. Capacitors C2 and C3 are connected to earth from respectively the junction of resistors R4 and R5, and the junction of resistors R9 and R10. The capacitors C2 and C3 are provided to keep electrical noise from the power supply out of the ramp waveform.The seriallyconnected resistors define a potential divider chain and the inverting inputs of comparators 11, 12, 13 and 14 are connected respectively to the junction of resistors R5 and R6, the junction of resistors R6 and R7, the junction of resistors R7 and R8, and the junction of resistors R8 and R9. Each of the four inverting inputs has added to the DC potential it receives from the potential divider chain the ramp waveform from capacitor Cl, respective AC-coupling capacitors C4, C5, C6 and C7 being used for this purpose. Although specific values are shown for the resistors of the potential divider it is to be understood that these are merely typical values and that the actual values are selected to space the tapped potentials equally with a spacing or offset related to the ramp waveforms.Let it be supposed that the ramp waveform as coupled by the capacitors C4, C5, C6 and C7 produces at the inverting inputs a ramp of peak-to-peak amplitude R volts and that the potential offset from one tap to the next is A, then A is chosen to be less than R so that there is about a 10% overlap of operation between one comparator and its immediate neighbour. For example, in practice R might equal 3 volts and A could be chosen as 2.7 volts.

If the mean d.c. potential at the inverting input of comparator 14 is P and the a.c. component of the ramp waveform at any one of the inverting inputs is r then the potentials at the inverting inputs of comparators 14, 13, 12 and 11 are, of course, respectively P + r, P + A + r, P + 2h + r, P + 3h + r.When any one of the comparators receives at its non-inverting input a signal from the error amplifier of higher potential than the potential at its inverting input, the output of that comparator acts upon the associated steering logic to drive the associated power converter when the control signals from drive logic 6 permit.Conversely when any one of the comparators receives at its non-inverting input a signal from the error amplifier of lesser potential than the potential at its inverting input, the output of that comparator acts upon the associated steering logic to disable the associated power converter. At full output power, the drive logic circuit 6 defines the ON and OFF current switching times but partial output power is obtained by switching OFF at some instant earlier than the full power OFF time. This instant is the instant at which the inputs of the comparator become equal.

For example, if the signal from the error amplifier 1 5 is, say, R P +2h + 2 then it will be seen that (i) comparator 14 enables power converter 5 to be driven at full power because R P + 2h + 2 is always greater than P + r.

(ii) comparator 13 enables power converter 4 to be driven at full power because R P +2h + 2 is always greater than P + A + r (iii) comparator 12 enables the drive to power converter 3 when R P+2A± > P+2A+r 2 but disables the drive to power converter 3 when R P+2A± < P+2A+r, 2 that is to say converter 3 is driven at partial power, and (iv) comparator 11 disables the drive to power convertor 2 because R P + 2A + 2 is always less than P + 3A + r.

By this means a very wide range of power control is achieved since at one extreme all four power converters can be worked at full capacity and at the other extreme three of the power converters can be disabled and the fourth worked at very low or zero capacity, intermediate power values being possible by working one converter at partial capacity and up to three converters at full capacity. The feedback control arrangement from monitoring network 20 comprising error amplifier 1 5 is arranged to maintain the current fed to the cable L1 constant. Means (not shown) are also provided to monitor the voltage output and control it so as to lie within predetermined limits.

It is to be noted that only as many individual power converters are converting power as is necessary at any instant to supply the demand at the time. This improves efficiency because power converters are either OFF altogether, losing no power, or are fairly well loaded, which is the most efficient part of the operating range. One large power converter or several smaller power converters operating together would be less efficient at low output power because on one hand no losses could be altogether avoided and on the other, no part would be working in the most efficient part of its operating range.

Smoothing the output waveform is easier at lower output voltage in the present arrangement because most of the power converters will be OFF. For example, if only one power converter out of four is needed, the voltage pulses will have a quarter the amplitude and four times the duration of the output of one large converter or several operating together. The output of the present arrangement is nearer to being a continuous flow of power. Stability is also improved because with most of the power converters switched OFF, a slight variation in the control signal does not produce such a big burst of excess voltage as would be the case for one large converter or several operating together. A further advantage is the ease with which control can be implemented which also gives effectively instantaneous switching ON and OFF of the converters as required.A slight overlap is provided at the transition from one part of the range to the next. As one converter approaches its full power the next converter starts to produce power and the outputs of both converters are controlled until the output of the one converter reaches its maximum. This permits the smooth introduction of each additional converter. The ramp used is a nonlinear ramp which in conjunction with the comparators controls pulse width. This improves stability when just one converter is operating because a small variation of control signal produces a smaller variation of output power when the output power itself is small and where a linear ramp would have produced a bigger output variation. When the power is greater, the output variation will inevitably be greater but this is tolerable as it is still broadly in proportion.

The power transistors in any enabled power converter working at full power are switched ON at a time corresponding to the beginning of the ramp waveform and this switching action creates electrical noise which appears as a ripple in virtually all parts of the circuit. Another advantage of using the exponential ramp illustrated is that the ramp has its steepest slope at the time this ripple occurs so that the ripple is less significant than it would be if a linear ramp joining the beginning and end points of the exponential ramp were used.

Figure 4 shows the circuit diagram of any one of the power converters 2, 3, 4 and 5 and its associated steering logic circuit, component values and type numbers being marked in the Figure. The circuit of Figure 4 will be described only briefly.

The steering logic circuit shown in Figure 4 comprise a pair of two-input NAND gates 30 and 31, each NAND gate having one input connected to an output of the drive circuit 6 and its other input connected to both the output of the associated comparator and another output of the drive circuit. The drive circuit 6 includes a bistable which divides the clock frequency by two. The pair of NAND gates 30 and 31 are controlled by the separate Q and 0 outputs to ensure that they are switched alternately and not simultaneously. The drive circuit may also include such other gates as are necessary to provide the 2us off time and other ON/OFF functions.Each NAND gate 30,31 has its output connected to the input of a respective one of two amplifier circuits 32, 33. Each amplifier 32, 33 is connected to drive a respective one of two power transistors 34, 35 by means of a respective one of two coupling transformers 36, 37. The arrangement is such that the power transistors 34 and 35 are turned ON alternately but both are OFF for (at least) the two microsecond period mentioned earlier. The power transistors switch current derived from a DC supply connected to terminals 38 into the primary winding of an output transformer 39 having its secondary winding connected to a bridge rectifier 40 from which the output of the power converter is taken.

The transformers 36, 37 and 39 are conventional as regards the construction of their secondary windings, formers and ferrite cores but each employs a special form of primary winding illustrated diagrammaticaily in Figure 5. Figure 5 shows the construction of a bifilar primary winding for the transfor 39 but the transformers 36 and 37 would be constructed using a single-spiral winding. The primary winding of each transformer is wound over the secondary winding, the secondary winding being of wire taken up the full available width of the former.

Referring to Figure 5, the primary winding 50 comprises copper foil 4 thousandths of an inch thick and of width equal to the winding width of the coil former (not shown) for the transformer 39. The copper foil is enamelled for insulation purposes (although paper insulation could be used as an alternative) and consists of two strips 51, 52 wound in bifilar manner. Each strip 51, 52 consists of ten tightly wound turns but for the purpose of clarity of illustration Figure 5 merely shows two turns very loosely wound. At the beginning and end of each strip the enamel is cleaned off on the outer side and a respective connecting wire 53 is soldered transverse to the strip. The solder is indicated by reference 54 and extends the full width of the strip and each connecting wire projects beyond the strip at each side.

The innermost connecting wire of one strip is connected to the outermost connecting wire of the other to provide a centre-tap of the winding.

The described winding is highly efficient because it utilises the full available width of the coil former and the conductor material is continuous from one side of the former to the other. By this means very good linkage with the magnetic circuit is obtained. The method of connecting the wires 53 gives good current-carrying capacity and the foil itself has a good current-carrying capacity because, although thin, it has sufficient cross-section area by virtue of its width.

Figure 6 shows a part of the control logic circuit 1 associated with the oscillator 21 and detectors 23 and 24. The two power feed equipments at one end of the communications system share a common control logic circuit 1, oscillator 21 and detectors 23 and 24 and the same is true of the two power feed equipments at the other end of the communications system.

The oscillator 21 of the two power feed equipments at one end generates a frequency in the range 4950 to 6450 Hertz and the oscillator of the two powerfeed equipments at the other end generates a frequency in the range 6550 to 8050 Hertz.

The tones produced by the oscillators are used for three purposes which may be used to enable automatic shut-down; a) monitoring the continuity of the cables, b) determining the status of the remote power feed equipments from the near power feed equipments, and c) detecting any low impedance path between an inner conductor and earth.

Referring to Figure 6, a part of the control logic circuit 1 is illustrated and for convenience will be termed the primary logic circuit.

A manually-operated push-button switch S1 is connected to the B input of a monostable multivibrator MS1 having a three-second monostable period. The Q output of multivibrator MS1 is connected to the B input of a second multivibrator MS2 having a three-hundred millisecond monostable period The Q output of multivibrators MS2 is connected to one input of a two-input AND-gate 70 and the Q output of a further monostable multivibrator MS3, having a two-hundred millisecond monostable period, is connected to the second input of the AND-gate. The output of AND-gate 70 is connected to one input of a further two-input AND-gate 71 and to one input of a three-input NAND-gate 72.

An input line 73 carries a logic output signal from the remote detector 24 and is connected to a delay circuit 74. Similarly, an input line 75 carries a logic output signal from the local detector 23 and is connected to a delay circuit 76. The output of delay circuit 74 is connected to the input of a NOR-gate 77 arranged as an inverter. The output of delay circuit 76 is connected to one input of a two-input ANDgate 78 and also to the input of a NOR-gate 79 arranged as an inverter. The output of NOR-gate 77 is connected to the B input of a monostable multivibrator MS4, having a monostable period of one millisecond and also to one input of a three-input NAND-gate 80. The Q output of multivibrator MS4 is connected to the other input of AND-gate 78.

The current monitoring circuit 20A includes a threshold circuit (not shown) to provide a logic output indicating whether the current flowing is, or is not, within a prescribed limit (such as 1 2%) of the desired constant value. A line 82 carries the logic signal -indicating whether the current is within the limit or not and is connected to the delay circuit 81. The output of the delay circuit 81 is connected to another input of the NAND-gate 72. The output of NAND-gate 72 is connected to the A input of a monostable multivibrator MS5, having a one-second monostable period, the Q output of which is connected to another input of the NAND-gate 80. The third and remaining input of NAND-gate 80 is connected to receive the output of NOR-gate 79.

The output of NAND-gate 80 is connected to the other input of AND-gate 71 to the input of a NOR-gate 83 arranged as an inverter and to line 84 connected to drive logic circuit 6.

The output of NAND-gate 71 is connected to a line 85 connected to control the oscillator 21.

The operation of the primary logic control circuit will now be described. Several examples of operation will be given and the logic operation at each end of the communication system set out in time sequence. The first example will be the start procedure and the two power feed arrangements at the end of the communications system in which an operator operates the switch S1 will be termed the "near" end and the other end the "remote" end.

I. LOGIC OPERATION IN TIME SEQUENCE OF START PROCEDURE Initial conditions: lines 73, 75, 82, 84 and 85 all at logic '1' NEAR END 1. Operator closes switch S1 which applies logic '0' to B input of MS 1. When S1 opens on release the B input rises to logic '1' and the Q output changes to logic '1' for three seconds 2 4 output of MS2 changes to logic '0' for three hundred milliseconds in response to logic '1' output of MS1 3. AND gate 70 starts to produce a three hundred millisecond in response to logic '1' output of MS1 4. AND gate 71 applies logic '0' on line 85 to actuate oscillator 21 5. Local detector 23 detects tone from oscillator 21 and applies logic '0' to line 75 6.After one hundred millisecond delay the delay circuit 76 produces a logic '0' output 7. NOR-gate 79 inverts logic '0' from delay circuit 76 and applies logic '1' to NAND-gate 80 8.

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1 3. Tone from far end oscillator detected and remote detector 24 applies logic '0' to line 73 14. After a one hundred millisecond delay the delay circuit 74 produces a logic '0' output REMOTE END Tone from near end oscillator detected and remote detector 24 applies logic '0' to line 73 (in the remote end equipment) After one hundred millisecond delay the delay circuit 73 produces a logic '0' output NOR-gate 77 inverts logic '0' from delay circuit 75 and applies logic '1' to B input of MS4 and to one input of NAND-gate 80 MS4 applies one millisecond logic '1' pulse to AND-gate 78 AND-gate 78 applies one-millisecond logic '1' pulse to B input of MS3 MS3 applies two hundred millisecond logic '0' to AND-gate 70 AND-gate 70 starts to produce two hundred millisecond logic '0' pulse AND-gate 71 appies logic '0' on line 85 to actuate oscillator 21 Local detector 23 detects tone from oscillator 21 and applies logic '0' to line 75 After a one hundred millisecond delay the delay circuit 76 produces a logic '0' output NEAR END 1 5. NOR-gate 77 inverts logic '0' of delay circuit 74 and applies logic '1 ' to NAND-gate 80 already receiving logic '1 ' on its other two inputs 16.NAND-gate 80 applies logic '0' to line 84 to enable drive logic circuit 6 17. Power converters start working 1 8. In under one hundred milliseconds output brought to within acceptable limit of desired value 1 9. Threshold circuit (not shown) applies logic '0' to line 82 20. After one hundred milliseconds, delay circuit 81 applies logic '0' to NAND gate 72 already receiving logic '0' from AND-gate 70 and logic '1 'from NOR-gate 83 21. The three hundred millisecond logic '0' pulse from AND-gate 70 (see 3 above) ceases 22.NAND-gate 80 continues to supply logic 'O' to AND-gate 71 which in turn continues to supply logic '0' to maintain the oscillator actuated, the logic '0' signal on line 84 from NAND-gate 80 continues to maintain the logic drive circuit enabled.

REMOTE END NOR-gate 79 inverts logic '0' of delay circuit 79 and applies logic '1' to NAND-gate 80 already receiving logic '1' on its other two inputs NAND-gate 80 applies logic '0' to line 84 to enable drive logic circuit 6 Power converters start working In under one hundred millliseconds or less output brought to within acceptable limit of desired value Threshold circuit (not shown applies logic '0' to line 82 After one hundred milliseconds, delay circuit 81 applies logic '0' to NAND-gate 72 already receiving logic '0' from AND-gate 70 and logic '1 ' from NOR-gate 83 The two hundred millisecond logic 'O' pulse from MS3 (see 10 above) ceases Identical with 22 from near end.

Figure 7 shows the waveforms on various lines and the output of various elements of Figure 6.

Each waveform is identified by the letter W followed by the reference numeral of the line on element to which it relates and an indication whether the waveform occurs in the near or remote end equipment.

That part of Figure 7 to the left of the broken line A-A relates to the start procedure explained above.

The times for the near end remote power converters to bring their outputs within the acceptable limit are indicated as T1 and T2 respectively. The maximum period allowed for the power feed arrangement to reach their proper working condition is the three hundred milliseconds defined by the start pulse W70 (near) and since the delay circuits take up two hundred milliseconds of this total time it follows that the allowed time for T1 and T2 is up to one hundred milliseconds. An example will now be given of the shut down of the system if T1 exceeds one hundred milliseconds.The switching characteristic of each of delay circuits 74,76, 82 is such that the output changes from logic '1' toO' one hundred milliseconds after the input changes from '1' to '0' but the output changes from '0' to '1' in response to an input change from '0' to '1' within a few milliseconds.

II. LOGIC OPERATION IN TIME SEQUENCE OF START PROCEDURE WITH FAILURE OF CURRENT GENERATORS AT NEAR END TO START NEAR END REMOTE END Steps 1 to 1 6 identical with steps 1 to 1 6 above Steps 1 to 20 identical with steps 1 to 20 above 17,18,19,20.

Power converters fail to operate correctly within one hundred milliseconds and signal on line 82 remains at logic '1' 21. The three hundred millisecond logic '0' pulse from AND-gate 70 ceases 22. NAND-gate 72 receives logic '1' at all No change three inputs and produces logic '0' at its output NEAR END 23. MS5 starts to produce a one second logic '0' pulse 24. NAND-gate 80 produces a logic '1' output which disables the power converters 25. AND-gate 71 applies logic '0' to line 85 which de-actuates the oscillator 21 26. Local detector detects absence of tone and applies logic '1' to line 75, threshold circuit applies logic '1' to line 82 27. Delay circuit 76 produces logic '1' and delay circuits 81 produces logic '1' 28.

29.

30.

31.

32.

33.

34.

REMOTE END No change No change No change Remote detector detects absence of incoming tone and applies logic '1 ' to line 73 Delay circuit 74 applies logic '1' to NOR-gate 77 NOR-gate 77 produces logic '0' NAND-gate 80 applies logic '1' to line 84 disables the power converters AND-gate 71 applies logic '0' to line 85 which deactuates the oscillator 21 Local detector detects absence of tone and applies logic '1' to line 75, threshold circuit applies logic '1 ' to line 82 Delay circuit 76 produces logic '1' and delay circuit 81 produces logic '1' NAND-gate 72 produces logic '0' MS5 produces a one second logic '0' pulse A third example will now be given to illustrate shut-down in the event that after a period of correct operation the output of the power converters in the remote equipment is outside the a!lowable limit.

III. LOGIC OPERATION IN TIME SEQUENCE WITH FAILURE OF POWER CONVERTERS AT REMOTE END DURING OPERATION Normal operating conditions existing before failure: Lines 73, 75, 82, 84 and 85 all at logic '0' NEAR END 1. Normal working 2.

3.

4.

5. Normal working 6. No tone received from remote detector response to ioss of tone and applies logic 1 to line 73 REMOTE END Current Monitor circuit detects current out of tolerance; sends logic 1 to line 82 Delay circuitry 81 checks duration of logic 1 on line 82; sends logic 1 to NAND-gate 72 if condition 1 above persists NAND-gate 72 sends logic 0 to monostable MS5 MS5 triggers and sends logic 0 to gate 80, for at lease one second to ensure system shut-down NAND-gate 80 sends logic 1 to switch off power converters on line 84, and to switch off tone oscillator via and gate 71 and line 85 Local detector responds to loss of tone and applies logic 1 to line 75 NEAR END 7. Delay 74 applies logic 1 to inverter 77 which applies logic 0 to NAND-gate 80 which applied logic 1 to line 84 to switch off power converters 8. AND-gate 71 applies logic 1 to line 85 to switch off the oscillator REMOTE END Delay 76 applies logic 1 to inverter 79 which applies logic 0 to NAND-gate 80 which maintains logic 1 to line 84 to maintain switch off AND-gate 71 maintains logic 1 to line 85 maintaining switch off of oscillator

Claims (14)

1. A power feed arrangement for use in conjunction with another like power feed arrangement in feeding power from opposite ends of a transmission path connecting two terminal stations, the power feed arrangement including: a power supply generator, signal-sending means to send by way of the transmission path a signal indicating that the generator is shortly to feed power to the transmission path, signal-receiving means to receive from the transmission path the signal sent by the signal-sending means of a like arrangement and operative to respond to the received signal by initiating the feeding power to the transmission path by the generator, and a monitoring circuit operative to compare the output of the generator with a desired value of output and operative to stop the generator feeding power to the transmission path if the actual output does not attain a value within a predetermined range of the desired value within a predetermined time interval.

2. A power supply arrangement including first and second switched-mode power converters, wherein the output of the power supply arrangement is taken from both converters and is adjustable over a range, a lower part of the range being provided by adjustment of the first converter with second converter arranged to contribute no power, and a higher part of the range being provided by adjustment of the second converter with the first converter producing a fixed proportion of its full output.

3. An inductive component comprising a winding on a magnetic core characterised in that the winding comprises spirally wound conductive strip material.

4. An arrangement as claimed in claim 1, wherein the signal-sending means is separately actuable by a start signal from a manually-operable switch and a signal from the signal-receiving means.

5. An arrangement as claimed in claim 4, wherein a monostable multivibrator triggerable by the manually-operable switch is provided to define the said predetermined time interval.

6. An arrangement as claimed in any of claims 1, 4 and 5, further including a second signalreceiving means to detect the signal sent by the signal-sending means of the one power feed arrangement, and a logic circuit to inhibit initiation of power feeding in the absence of detection of the last mentioned signal by the second signal-receiving means.

7. An arrangement as claimed in any of claims 1, 4, 5 and 6, wherein the, or each, signal-receiving means and the monitoring circuit have a respective delay circuit associated therewith.

8. An arrangement as claimed in claim 2, wherein N power converters are provided, N being an integer greater than two, the range is divided into N parts, the lowest part of which is provided by adjustment of a first converter with the other converters contributing no power, the second part of which is provided by adjustment of a second converter with the first converter producing a fixed proportion of its full output, the third part of which is provided by adjustment of a third converter with both the first and second converters producing fixed proportions of their full output, and so on.

9. An arrangement according to claim 2 or 8 wherein adjacent parts of the range overlap each other.

1 0. An arrangement as claimed in claim 2, 8 or 9, wherein the power supply arrangement is arranged as a constant current generator.

11. A component as claimed in claim 3, wherein connection is made to the strip material of the winding by means of wires arranged transverse to the longitudinal axis of the strip and projecting beyond the strip, the wires being soldered to the strip across its width.

12. A component as claimed in claim 3 or 11, wherein the width of the strip material is substantially equal to the available winding width of the former.

13. A component as claimed in claim 3, 11 or 12, wherein two strips are joined and placed to form a bifilar winding.

14. An arrangement according to any of claims 2, 8, 9 and 10 including at least one component according to any of claims 3, 11, 12 and 13 with another winding of wire and connected as a transformer.

1 5. An arrangement according to any of claims 1,4, 5, 6 and 7 in which the generator includes an arrangement according to any of claims 2, 8, 9, 10 and 14.