GB2056197A - Lighting control systems - Google Patents

Abstract

In a system for controlling an array of lamps arranged in rows or columns or concentric circles, solid state switches e.g. triacs may be connected in links connecting the live terminals of the lamps to a live bus bar and the neutral terminals of the lamps to a neutral bus bar. Control circuits are provided for selectively closing the switches so as to produce different patterns of illuminated lamps. Where the number of lamps exceeds the number which can safely be connected to the power supply the system is programmed so as to eliminate any possibility of connecting more than the safe number of lamps to the bus bars at any particular time. By switching from one set of lamps to another very rapidly, the visual effect of all lamps being used can be obtained. A pulse generator can be used to run through a programme of lamp connections from a memory. Alternatively the amplitude of an electrical signal derived from an audio source can be used to vary the production of control pulses.

Description

SPECIFICATION Improvements in and relating to lighting control systems Field of invention This invention concerns control systems for lighting and in particular programmable control systems for controlling an array of lighting or environmental lighting to allow changing patterns of light with provision for changing the lighting in response to electrical signals derived from music.

Background to the invention In environments such as discotheques and dance halls and night clubs it has become conventional to provide lighting displays which present a pattern of light which is varied in sympathy with music which is being played. One often selected display is an array of one hundred light bulbs either arranged in ten lines and columns or as an array of ten concentric circles.

Hitherto the array of lamps has been switched by control equipment which has left the neutral connections permanently connected to the lamps and has merely switched the live lines. By doing so, a line of lights has been illuminated and movement of the line has been achieved either in a wave motion up or down or as a vertical line across or back. In the radial array of lamps either a radial line is moved in a circular manner around the array or each of the concentric circles of lights has been illuminated in turn so as to produce what has typically been referred to as a starburst effect in which the concentric circles of light have been illuminated in succession beginning with the innermost circle first and moving outwards.A reverse or inverted starburst effect has been obtained by simply switching the lights in reverse order so that the outermost circle is illuminated first and the innermost circle last.

It is an object of the present invention to provide control apparatus for controlling an array of lights such as that described above not only to produce regular repetitive pattern but also to modify the repetitive pattern in sympathy with a music signal and to provide outputs from such apparatus to enable envrionmental lighting in addition to display lighting to be controlled in a similar manner.

It is another object of the present invention to provide control apparatus of the type previously mentioned which is capable of producing more complex patterns in an array of lights than has hitherto been the case.

The invention According to one aspect of the present invention in a control system for controlling an array of lights arranged in an array of rows and columns or an array of concentric circles, and in which each of the lights has a live and neutral terminal which must be connected to live and neutral bus bars respectively for the light to be illuminated, solid state voltage or current controlled switches are provided in links connecting the live terminals of the lamps to the live bus bar and the neutral terminals of the lamps to the neutral bus bar and control circuits are provided for selectively closing the solid state switches so as to produce any desired pattern of lights in the array.

Preferably the number of lamps which can be so connected at any instant is limited to a given percentage of the total number of lamps in the array and the control circuit is programmed accordingly thereby limiting the current requirements. a visual impression that more of the lamps than the given percentage are illuminated at any instant can be obtained by switching the lamps at a relatively high speed.

According to another aspect of the invention in the circuits controlling the operation of the solid state switches, circuit means is provided for generating a repetitive sequence of electrical signals the repetition frequency of which is controllable so that a given pattern of lights in the array can be moved either from side to the other or from top to bottom or in a circular array either from the centre outwards or from the perimeter inwards or in a radial manner around the circular array, the movement of the pattern being in a series of steps each step corresponding to a fixed pattern of lamps being illuminated in the array and each transition from one step to the next representing the change from one fixed pattern to the next fixed pattern which is typically the same pattern but displaced in space within the array.

Thus rings of light can be made to move radially outwards in the form of starbursts or lines or diagonals can be made to move from one side of an array to the other or from one corner down to -the other or two lines of illumination can be made to move either in tandem or in opposition in the array.

According to another aspect of the present invention, circuit means is provided responsive to a music signal for producing a control voltage in response to some parameter of the music signal, the control voltage serving to control the frequency of the pulse generator producing the sequence of repetitive pulses so that the movement of the pattern of light around the array can be speeded up or slowed down depending on the particular chosen parameter of the music signal. This may for example by the amplitude of the signal or the amplitude of a part of the signal (for example relating to the rhythm of the music or the high frequency content of the music signal).

The control circuit is conveniently programmed so that when the music signal ceases the array of lights ticks over slowly.

According to another aspect of the present invention, the apparatus may include circuit means for generating a sequence of overriding control signals which change the programmed pattern in a cyclic manner so that the particular pattern of light which is moved in sympathy with the music signal is itself changed periodically so that a sequence of different patterns appear each one moving in sympathy with the music signal.

The period of time between the changes of pattern are preferably controllable so that either short periods of time between changes can be selected or longer periods up to many minutes or the pattern changes to the next after a number of sweeps.

According to another aspect of the invention a control system for controlling the operation of a plurality of lamps includes a corresponding plurality of solid state switches and individual control circuits for triggering the solid state switches between conductive and non-conductive states, circuit means for generating switching pulses for feeding to selected ones of the individual control circuits thereby to produce switching of selected ones of the said plurality of solid state switches and thereby cause illumination of selected ones of the plurality of lamps, and further circuit means for controlling the operation of the said first circuit means to modulate the operation of the latter in response to an electrical signal derived from a music signal, an alternating current power supply for the lamps, the said plurality of solid state switches being connected so as to supply alternating current from the said alternating current supply to the lamps according to the control signals supplied thereto and further circuit means which synchronises the generation of the switching signals to ensure that a change in the switching signals occurs only at a zero crossing of the waveform of the alternating current source for the lamps and also only occurs at full cycle periods so that only full cycles of alternating current are supplied to the lamps.

The advantage of the second aspect of the invention is twofold. In the first place the synchronism of the switching of the solid state switches with the zero crossing points of the alternating current supply means that little or no electrical interference is generated by the operation of the solid state switches. Secondly and more importantly, the synchronsim of the switching signals so as to ensure that only full cycles of alternating current are delivered by the solid state switches, the switched outputs from the solid state switches can be supplied to an inductive mode.

According to a preferred feature of this said further aspect of the invention, dimming of the lamps may be achieved by a further circuit means adapted to remove switching signals which would otherwise be supplied to the solid state switches thereby to remove from the switched outputs whole cycles of alternating current beginning and ending at zero crossings of the alternating current waveform so as to leave in full cycle sinewave forms of alternating current albeit spaced by empty fuli-cycle periods. By achieving a dimming action in this manner, so electrical interference is minimised but also more importantly still the dimming facility can be operated even when an inductive load is connected to the switched outputs.

The signal derived from the music signal for modulating the generation of switching signals is preferably formed by amplifying a music signal by an amplifier having a logarithmic input/output function so that the output signal is a logarithmic function of the input signal amplitude and the amplitude changes in the output signal therefore correspond to percentage changes in volume.

Where a 50 or 60 cycle alternating current supply is used for feeding the lamps, a particularly pleasing effect can be obtained by adjusting the circuits so as to remove alternate complete cycles of alternating current from the alternating current to be supplied to the load. When such a signal is supplied to a conventional incandescent lamp, a flickering light output is obtained with the flicker proportional to the frequency of the alternating current supply and with supply frequencies in the range indicated, the flicker is not so pronounced as to be unpleasant and appear to be a switching on and off of the light but produces a shimmering effect in the light output from the lamp.The effect is particularly pleasing when the control circuits cause a considerable number of the lamps in the said plurality of lamps to be illuminated or appear to be illuminated as a result of rapid switching from one group of lamps to another.

According to a still further preferred feature of this aspect of the invention, timing circuit means may be provided for causing an overall change in the pattern of lamps selected for illumination simultaneously as a group and means is provided for adjusting the times at which the changes in the overall pattern occur.

According to a still further preferred feature of this aspect of the invention, the timing circuit may further function so as to change not only the pattern or group of lamps which are to be simultaneously illuminated but also to change the sequence of the electrical signals supplied to the individual control circuits for the solid state switches so as to sequentially vary the sequence of control signals supplied to the individual control circuits so that with each change, the movement of the pattern of lights is changed for example from a mode in which a pattern is swept in one direction through an array of lamps to another mode in which the same pattern is swept in an opposite direction or in a different manner to the array of lamps.

Preferably the timing circuit can be adjusted so as to produce the changes in mode of operation to occur either at relatively short intervals of time or after very long intervals of time such as a fraction of an hour. In the latter mode of operation, the invention may be used to advantage for controlling the lights in an auditorium which may for example be a dance hall or a night club or a discotheque or a restaurant so that in accordance with a pre-programmed sequence, different lights within the auditorium can be automatically switched after intervals of some minutes so that the pattern of lighting and therefore the atmosphere within the auditorium can be changed according to a predetermined programme over a considerable period of time such as a whole evening or night.

Although this said further aspect of the invention has been described with reference to an arrangement in which only one solid state switch is employed for each lamp, it is to be understood that this said further aspect of the invention may be combined with the first mentioned aspect of the invention to allow more complex pattern changes in an array of lamps to be obtained by switching not only the connections between the live bus bar and the lamps but also the neutral bus bar and the lamps.

In a control system constructed in accordance with either the first mentioned aspect of the invention or in accordance with any other aspect of the invention or any combination of such aspects, the means for controlling and switching the current to the lamps is preferably performed by means of solid state switches as specifically mentioned in relation to the said further aspect of the invention and conveniently such solid state switches are Triacs.It will be appreciated that the trigger circuits for the Triacs will have to be at line potential where the Triacs serve to establish connections between the live bus bar and the appropriate terminals of the lamps and to this end a separate power supply is provided for the trigger pulse generating circuits and the latter are electrically isolated from the circuits producing the switching signals which themselves control the trigger pulse producing circuits.According to another aspect of the invention, this electrical isolation is achieved by using optoelectronic devices in which the transfer of information occurs via a modulation of the output of a light emitting diode which is received by a light sensitive semiconductor junction, the link being contained within a single component having input and output circuit for receiving signals for modulating the output of the light emitting diode and delivering electrically isolated signals corresponding to the input signals by appropriate amplification of the output from the light sensitive junction.

The safe working voltage for such devices is determined by their mode of construction and in general the greater breakdown voltage between input and output circuits, the more expensive will be the device. In order to allow relatively cheap devices to be used, voltage regulation of the electricity supply mains is preferably incorporated into a system embodying such devices for electrical isolation so as to limit the maximum voltage spike from the supply mains to say 800 volts. In this way for example 1 500 volt breakdown voltage optoelectronic devices may be used. This voltage regulation is most easily achieved by connecting a voltage dependent resistor across the supply mains input to the system having an appropriate voltage/resistance characteristic for removing excessive voltage spikes.

The invention will now be described by way of example with reference to the accompanying drawings.

In the drawings Fig. 1 is a block circuit diagram of a complete control system for controlling a bank of lights.

Figs. 2 to 11 inclusive are circuit diagrams which should be read in conjunction one with the other of the complete system shown in block circuit diagram forming Fig. 1.

Detailed description of drawings The system shown in Fig. 1 and described in more detail in Figs. 2 to 11 is a so-called 10way chaser. By this is meant a system which is capable of supplying alternating current for operating one or more of ten banks of lights connected to ten outlets in the equipment, each of the outlets being independently controlled by its own solid state switching device and the latter only changing state at the zero crossing point of the waveform of the alternating current which it controls and furthermore being maintained in any switched condition for a whole number multiple of the full alternating current waveform period so that only complete alternating current pulses can be released by the switching device so that inductive loads can be connected to the outlets.

Dealing first with the block circuit diagram of Fig. 1, the live bus bar of a standard alternating current mains supply typically of 240 volts at 50 Hz (10) is connected via a fuse 12 to a neon illuminated on/off switch 1 4. The latter controls the connection of the live bus bar to the primarys of two step-down transformers 1 6 and 1 8 each of which provides an output voltage on its secondary winding of between 8 and 1 6 volts.

A suppression circuit 20 is connected between live, earth and neutral bus bars to remove unwanted voltage spikes and protect the equipment against voltage surges.

The two transformers 1 6 and 18 provide low voltage alternating current for two power supplies 22 and 24 respectively and isolate the two power supplies so that the one can rise to the mains potential if required and the other can remain around earth potential. This allows solid state switching devices to be controlled and powered from a floating supply 22 and allows an earthed supply to be provided for the amplifying and switching circuits for producing trigger pulses which are then supplied via an isolating network to the switching circuits which are at mains voltage.

The switching of the solid state devices is synchronised with the waveform of the alternating current supply 10 and to this end a squarewave generator 26 is provided with signals from the neutral line and is powered from the floating power supply 22 to provide appropriate trigger pulses to an optoisolator circuit 28 (to be described in more detail hereinafter) which then provide isolated square-wave pulses to squarewave receiver 30 which pulses are then used in timing circuits for generating trigger pulses for changing the data which finally appears as control pulses for the solid state switches (to be described).

A standby switch 32 allows the floating power supply to be removed from a Triac gate drive circuit 34 which supplies trigger pulses to a bank of ten Triacs 36. The latter serve as solid state switched junctions between the live bus bar (L) of the mains supply 10 via ten separate fuses in a fuse bank 38 to ten terminals on an output terminal strip 40. The latter includes additional terminals to some of which are connected the earth and neutral bus bars from the power supply 10 and connections from the terminal strip 40 are made to a bank of lights 42 not shown in detail.

Since the Triac gate drive circuit 34 is connected to the floating power supply 22, electrical isolation is needed between the circuit 34 and the control signals which are supplied thereto from the remainder of the circuit and to this end a set of ten opto-isolator circuits shown as a single bank 44 are provided (details of the opto-isolator circuits being shown in more detail later) and opto-LED drive circuits for the ten optoisolators 44 are provided in a bank 46.

Since the unit being described is primarily intended to be connected to one particular bank of lights which for convenience will be considered to be a circular array of ten concentric circles of lamps each circle containing ten lamps, the lamps in each of the circles being equally spaced therearound and aligned with the lamps in the other circles so that when viewed from the centre, the lamps will appear in a series of ten radial rows similar to the spokes of a wheel radiating from the centre of the array.

By connecting the neutrals of all the lamps in the array to a common neutral line and connecting the live terminals of the lamps in each row together to a live common conductor and connecting the ten live common conductors to the ten outputs, any one of the ten radial rows of lamps can be illuminated by causing the Triac (36) associated with that output to conduct. By switching from one Triac to the next so each of the radial rows can be illuminated in turn in a circular sweeping motion.

In order to limit the current requirement for the control system, it can be arranged that only ten or perhaps twenty of the lamps can be turned on at any instant. On the assumption that 100-watt lamps are used this will limit the power requirement to 1 -Kw or 2-Kws as the case may be and will allow a standard 13-amp plug and socket to be used for connection to the mains supply.

The control signals to be supplied to the Triac gate drive 34 must therefore comprise well defined rectangular pulses of appropriate duration to allow the gate drive circuits to trigger the Triacs at the beginning of each full cycle of alternating current during which the Triac concerned is to conduct. The remainder of the block circuit diagram is essentially concerned with the production of sequences of such pulses so as to produce in a circular array of lamps suc.h as has been described, a changing pattern of illuminated lamps. By arranging that any two Triacs can be operated simultaneously (but no more for current limitation purposes) two of the radial rows of lamps may be illuminated and by appropriate choice of Triacs, so the two rows may for example always be aligned through the centre of the array and appear as an illuminated diameter.

Alternatively by appropriate switching to adjoining rows can be illuminated and then extinguised as successive pairs of rows illuminate and extinguish moving circularly in opposite direction from the starting pair until the two rows diametrically opposed to the starting pair are illuminated. At this point the sequence can be continued or reversed (the visual effect will be virtually the same) so that the illuminated pairs of rows effectively bounce from this diametrically opposite position to the starting pair until the starting pair are once again illuminated. Continuation of the sequence of pulses will of course produce an apparent continual bouncing between the starting pair and the diametrically opposite pair.

By appropriate programming, the starting pair can be moved either at the end of each complete bounce or at the end of a whole number multiple of complete bounces so that the starting pair is moved successivley around the array.

Many other variations can be obtained as will hereinafter be described.

Since the switching of the Triacs can be expressed as a series of two-state signals or binary signals, the sequences of such two-state signals can be stored in a binary memory and the sequences recalled from the memory upon appropriate address. To this end the block circuit diagram includes a PROM memory 48 clock pulses for which are obtained from a counter 50.

The frequency of the clock pulses from the counter 50 and the-direction of counting (either up or down) determine the speed at which the different series of binary codes are delivered from the memory and the order in which they are read out.

This in turn will determine the speed at which the Triacs 36 are switched as well as the order in which the Triacs are switched.

The particular section of the memory which is to be addressed is selected by a switch 52 which via a diode matrix 54 determines one of a number of binary codes which can be applied to certain of the address inputs to the memory. Where one pattern is to follow another in a sequence an autopattern change counter 56 can be rendered functional so as to change the output of the diode matrix 54 in succession so as to supply different address information to the appropriate address inputs of the memory 48.

The readout from the memory is inhibited except at certain points in time related to the zero crossing points of the alternating current waveform of the supply 10 and to this end control signals are supplied to the memory 48 derived from the output of the squared-wave receiver 30 via an inverting circuit 58.

Where it is required that every alternate complete cycle of alternating current is to be eliminated in the outputs of the Trdiacs 36 an appropriate inhibiting signal is obtained via a NAND gate 60 which is supplied with timing pulses from a generator 62 driven by the same signals as are supplied to the memory 48 to cause the latter to readout and the NAND gate is also supplied with pulses from a divide-by-two circuit 64 which is rendered operational by operation of the full/dim switch 66.

When the divide-by-two circuit operates, the NAND gate produces appropriate inhibiting signals which prevent the memory 48 from being read during alternate full cycle periods of the alternating current supply 1 0.

The up/down counter 50 is controlled from a divide-by-64 network 68 which is driven from a pulse generator 70 the repetition frequency of which is controllable by an infinitely variable control 72 between a high speed and a low speed. In addition a range switch 74 is provided by which the pulse generator 70 can be made to operate withing a relatively high frequency range or a relatively low frequency range.

The actual repetition frequency of the pulse generator circuit 70 is voltage controlled and includes an input terminal to which a varying voltage level signal can be supplied from a detecting and automatic gain control circuit 76.

This latter is driven either by the output of a logarithmic amplifier 78 the input of which is a music signal derived for example from a record player or tape recorder via an input terminal 80 or the circuit 76 can be rendered unresponsive to the output of the amplifier 78 by means of a music/auto switch 82 which when in the auto position applies a fixed voltage on the input terminal to the pulse generator circuit 70 so as to cause the latter to maintain a fixed repetition frequency determined simply by the controls 72 and 74.

The direction in which the counter 50 is running is determined by an up/down signal which is derived from a selector switch 84. The switch has six positions. In a first position the input 86 of the counter 50 is left floating and the counter will automatically count in one direction. In a second position of the switch 84, input 86 is connected to the O-volts row and the counter reverses its direction of counting.

The other four outputs allow the input 86 to receive appropriate sequences of pulses which cause the counter to first count up and then down in succession either by so many steps first one way and then the other or by its total capacity and then in the reverse direction so as to produce a simple automatic reversing function.

Signals for the various reversing modes and auto-reversing modes are derived from either the counter 50 itself via an inverter 88 and a series of divide-by-two circuits 90, 92, 94 or from pulse generator 96 the repetition frequency of which is controllable by a control 98 and the ouput of which is supplied by a divide-by-two network to an appropriate input to the switch 84.

The device chosen for the memory 48 has open collector outputs and to this end pull-up resistors 102 and a source of current for the resistors 102 is provided by an inverting amplifier 104 which is driven from signals from the NAND gate 60 in synchronism with the signals supplied to the memory 48 from the NAND gate 60. The pull-up resistors 102 operate therefore in synchronism with the addressing of the memory 48.

The output from the memory 48 is temporarily latched by a latching circuit made up of two separate latches 106 and 108. The latches are supplied with 4-bit binary signals from the 4-bit binary output of the memory 48 and two decoding circuits 110 and 11 2 respectively receive the latched 4-bit binary signals from the latches 106 and 108 and decode the information into five separate output signals for controlling the ten drive circuits 46 previously referred to. In this way one or more of the opto-isolators 44 is caused to operate and transfer an appropriate signal to a Triac gate drive 34 so as to turn on one or more of the Triac 36 as previously described.

The memory output is effectively multiplexed by means of the latches 106 and 108 which are triggered and caused to latch by means of 7 used.

duration pulses derived from the output of the inverter 58 using a 7 used. delay 114 and a negative pulse shape circuit 11 6 and a positive pulse shape circuit 118.

The decoders 110 and 112 are themselves inhibited for a short interval of time immediately preceding each zero crossing of the alternating current supply 10 by means of an inhibit signal C derived from the output of the inverter 104 and applied along signal path 120 to the two decoders.

As an aid to indicating which of the ten radial lines of lamps in a circular display of the type previously described is illuminated at any instant, a ring of ten light emitting diodes 122 is provided on the front panel of the apparatus and signals from the opto-isolators 44 are supplied to cause the light emitting diodes to be illuminated, each of the light emitting diodes in the array 122 corresponding to one of the radial arms of the display of lights 42.

Where the non-operation of one of the light emitting diodes will interfere with the transfer of information from the opto-isolators 44 to the Triac gate drive circuit 34, a series of ten by-pass diodes 124 are provided so that in the event of one of the light emitting diodes 122 breaking down the bypass diode 1 24 will serve to maintain the circuit conditions and allow the opto-isoiators 44 to continue to drive the Triac gate drive circuit 34.

Description of individual circuits An 18-way terminal strip 10 provides input terminals for the live, earth and neutral of the mains supply. The live and neutral terminals supply the two transformers 1 6 and 1 8 which respectively provide reduced voltage alternating current for the live and earthy power supplies.

A full-wave rectifying circuit using diodes 1 A and smoothing capacitors C4A and C4B provides an unstabilised voltage of between 2 and 1 5 volts to a voltage regulator circuit type 78M05 the output of which is smoothed by R2 and C5. The positive output is connected via link 126 and bus bar 128 to terminal 130. The bus bar 128 is itself connected to the live side of the input supply via switch 14 and fuse 12.

The terminal 130 is connected to one side of each of ten Triacs one of which is shown at 36'.

The outputs of the Triacs are connected via fuses of which one is shown at 38' to each of ten outputs on the terminal strip 10, each of these outputs being numbered 1 to 10.

The drive for each of the Triacs is derived from a Triac gate drive circuit one of which is shown based on transistor NH1 and identified by reference numeral 34'. There are ten such transistors 34' and each is drived from an optoisolating circuit which incorporates a device having a light emitting diode 132 and a light sensitive transistor 134 optically connected therewith. Current through the light emitting diode section 1 32 causes the junction 1 34 to be illuminated and the junction current variation causes transisitor 34' to be switched.

A standby switch 32 serves to connect and disconnect the negative 5-volt rail of the floating power supply to the Triac drive circuit based on the transistors 34' etc.

A 245-volt voltage dependent resistor 136 is connected between the live bus bar 128 and the neutral bus bar 138. The characteristic of this resistor is to produce a virtual short circuit at voltages much in excess of 600 volts thereby eliminating voltage spikes greater than that voltage. Since the duration of such spikes is very small the amount of energy dissipated is relatively low and can be readily absorbed in such a resistor and in the event of an excessive spike the circuit would be protected by the fuse 12.

Capacitors C1, C2 and C3 serve to further remove high frequency interference from the mains supply in conjunction with resistor R1.

The suppressed power supply voltage appears across diode D1 and resistor and capacitor network R3, R4, R5, C6 and the junction between the diode and this network is connected via resistor R6 to the -5 volt rail 140. The junction provides the base current for a transistor P 1 the junction current of which controls the base current for a second transistor P2. This serves to drive the light emitting diode section 142 of the optoisolating device 28 the light sensitive junction 144 of which provides the drive for the square-wave receiver 30 already referred to with reference to Fig. 1.

The earthed power supply 24 referred to in Fig.

1 is shown in more detail in Fig. 3 of the drawings.

The secondary of the transformer 1 8 supplies the full-wave rectifying circuit made up of diodes 1 A and smoothing capacitor C28. A 5-volt regulator type 78M05 provides 5 volts regulated supply which appears across resistor R1 4 and further smoothing capacitor C8.

The-connections between this earthed power supply and the remainder of the circuit are shown in the remainder of Fig. 3 with reference to outline circuits which refer to the various figures remaining in the drawings.

Fig. 4 shows the circuit diagrams of an amplifier which produces an output voltage which will vary in relation to the amplitude of an incoming music signal or maintained at a fixed level depending on the position of an auto/music switch 146. The amplifier includes an input circuit generally designated 148 adapted to receive a stereo input signal and to produce therefrom a monoral signal which is developed across a pair of diodes D2 and D3 which limit the peak to peak audio voltage to 1.2 volts. The peak to peak input signal is applied to the two inputs of a matched pairs of transistors N1 and N2 via resistor R 1 5 and capacitor C12 on the one hand and resistor R22 capacitor C13 on the other hand.The output of the differential amplifier which appears across resistor R1 9 serves to control the base current of a further transistor P3 the output voltage of which is developed across resistor R24 wit a feedback resistor R23 between the output and the input of transistor N2. A resistor R1 6 of approximately 2.2 Kohms is inserted between the zero-volts end of the bias resistor R 18 and the earthed input of the input socket so as to prevent earth loop. The effect of the resistor Rl 6 is to limit any currents induced in an earth loop created by inappropriate connection of the equipment and reduces any such circulating currents to such a low level that hum to all intents is eliminated from the output of the amplifier.

The component values are selected so that a 4volt peak to peak output voltage appears across resistor R24 and this is. applied via a capacitor C15 and resistor R25 to a junction 1 50 from where the positive going excursions control the base current of transistor P4 the output of which in turn controls the base current of transistor N3 which controls the current flowing through two identical resistors R30 and R31.The centre tap 1 52 of these two series connected resistors constitutes the output terminal for the amplifier and an output voltage is developed between terminals 154 and 156. feedback network incorporating resistor R32, transistor N4 and diode D4 serves to maintain the voltage at junction 158 at 4.4 volts when switch 1 46 is closed and when a music signal is applied which will always have a peak to peak value of 1.2 volts the minimum voltage to which junction 1 58 can swing is + 1.4 volts. This means that the swing at junction 1 52 which will be at one-half the potential of junction 158 will be 0.7 to 2.2 volts when a music signal is being applied and the switch 146 is open. When switch 146 is closed the output terminal 1 54 will be maintained at 2.2 volts.

The signal from terminals 1 54 and 1 56 serves to control the base current and therefore the current flowing through the junction of transistor N5 in Fig. 5 Capacitors Cl8A and Cl8B determine the slope of the sawtooth waveform which will be generated at junction 1 60 as a result of the charging and discharging characteristic of the circuit made up of transistors N5, N6, P5 and P6 and D6. The time constant can be very substantially increased by connecting a further capacitor C19 in paraliel with capacitors Cl 8A and C18B by closing switch 1 62. When the capacitor C19 is connected in circuit, a time constant of some many seconds is produced.

The actual time constant is determined by the series resistance in the circuit of transistor N5 and this is controlled by the setting of the slider on a variable resistor R37 having its own switch 164.

The switch 1 64 is open, transistor N5 is cut off and no sawtooth waveform will be produced at junction 1 60. In consequence no pulse will be produced at an output junction 166.

With switch 1 64 closed, conduction through the transistor N5 governed by the setting of variable resistor R37 will cause the voltage across the capacitors to drop and the potential at junction 160 in turn to drop.

The current throught the transistor N5 will not only be determined by the value of resistor R37 but will also be determined by the potential on the base of the transistor which itself is determined by the output across R3 1. in Fig. 4. In the automatic mode, this voltage is set at 2.2 volts thus ensuring a relatively high current flow through N5. When the switch 146 is open, the voltage at junction 1 54 can drop to .7 volts and can assume any value in between depending on the instantaneous amplitude of the music signal so causing the transistor N5 to conduct in a variable manner.This affects the repetition rate of the sawtooth waveform which will result at junction 1 60 as a result of the recharging characteristic of the circuit made up of transistors N6, P5 and P6 and the charging diode D6.

The rapid recharge of the capacitors gives rise to a 5-volt peak to peak pulse at junction 166 which is supplied as a clock pulse signal to the clock input of a counter type 4024 which constitutes an divide-by-64 circuit 68. The divided ouput is applied along output line 1 68 to the clock input of a counter 4029/1 which counts up or down according to input condition and produces a BCD output on four terminals 01,02. 03 and 04.

A signal to produce automatic reversal of counting is obtained by taking an output TC via R44 to an inverting amplifier based on transistor N7 the output voltage of which is developed across R43 and appears at terminal 1 70. The signal at terminal 1 70 constitutes a signal TC and transistor N7 constitutes the inversion circuit 88 of Fig. 1. The up/down counter type 4029/1 consititutes the counter 50 of Fig. 1.

In order to achieve automatic reversal of the sequence movement a pulse generating circuit is provided as shown in Fig. 6 based on transistors N8, P7, P8 and diode D7 which controls the recharging of a capacitor C20. Discharging of the capacitor is governed by the setting of variable resistor R50 in series with R49 which are connected across the capacitor C20.

The control for the adjustable resistor R50 thus constitutes the automatic reverse speed control and a sawtooth waveform is obtained at junction 1 72. Pulses similar to those obtained from the circuit of N6, P5 and P6 in Fig. 5 are obtained across the resistor R52 and these serve as clock input pulses to a counter 1 74. The 02 output changes state in response to each input pulse and the frequency of the changing of state of this putput is thus determined by the setting of R50.

The 02 output is supplied via resistor R59 to a terminal 176 of a multiway switch generally desiganted 1 78. In this position an automatic reverse is obtained since the signal on output terminal 180 will change state alternately and it is this signal which in the circuit of Fig. 5 is applied to the junction of resistors R45 and R46 and determines the mode of counting of counter 50.

TC pulses in from junction 170 of Fig. 5 are supplied to the second clock input CL2 of a second counter 1 82 and the D2 output is connected to the first clock input CL1 of counter 182 and through resistor R58 to the third terminal on the multi-way switch 178 labelled B. The D1 output from counter 1 82 is conected through resistor R60 to the fourth terminal of multi-way switch 178 and because the D1 output constitutes a division-by-2 of the signal B, this switch position is labelled B 2 The D1 output is also connected via conductor 184 to the first clock input CL1 of counter 174 and the D1 output is connected to the 01 so that the 01 output of counter 174 constitutes a division-by-4 of the pulse frequency at terminal B of switch 1 78. This signal is applied via resistor R57 to the fifth terminal in the multi-way swtich 1 78 which is accordingly labelled B 4 The first two terminal positions in switch 1 78 constitute forward and reverse and are labelled as such. In the forward position the wiper 186 is left floating so that the terminal 180 is pulled up to +5v by R45.

In the reverse position, with the wiper 1 86 connected to second terminal in the switch 178, the O-volt potential rail is connected via wiper 186 to terminal 180 so as to automatically reverse the counter 50 in Fig. 5.

A B 2 square-wave pulse train is provided at terminal 1 88 for driving the automatic pattern change counter to be described in relation to Fig. 7.

Fig. 7 contains the circuit associated with the pattern select/automatic pattern change switch.

The switch control is mounted on the front panel of the apparatus (not shown) and the switch comprises a wiper 190 for selecting between nine terminals. Each of the terminals is connected via diodes to one, two or three of three bus bars 192, 194 and 196 and the wiper is connected to the 0volt rail so that when it is connected to any of the first four or last four of the terminals in the switch, the diode or diodes associated with those terminals are caused to conduct. The bus bars include protection resistors R62, R63 and R64 and depending on the position of the wiper 190 so the potentials on terminals A5, A6 and A7 are either high or low.The terminals A5 to A7 are connected to the address inputs of a memory (to be described) and depending on the binary code exhibited on terminals A5 to A7 so any one of a number of different patterns can be selected from the memory.

Terminal 5 of the switch allows the O-volt line to be connected via resistor R61 to the PL input of a counter 198 and the P1, P2 and P3 inputs are wired high so that outputs 01,02 and 03 are normally high. In the event that the PL input is brought to 0 with the wiper 190 on terminal 5, the counter is trigged and outputs 01, 02 and 03 are selectively brought to a low value typically 0 potential so as to produce different binary numbers on the three outputs which in turn appear on the A5 to A7 terminals. The numbers correspond to the diferent binary numbers obtained by selecting different ones of the other switch positions but instead of being a static binary number on the terminals A5 to A7 the number changes at a repetition rate determined by the counting of the counter 198.To this end the clock pulses supplied to the clock input CL of counter 198 are the B 2 square wave pulses from Fig. 6 from terminal 188.

Since the clock input is at B 2 and the counter delivers a binary type output, so the output is at B 4 R66, R67 and R68 are feed resistors in the auto pattern change mode which occurs when PL is low.

Fig. 8 of the drawings illustrate a number of ancillary circuits as follows: The output from light sensitive junction 144 on page 2 (duplicated in the top left-hand corner of Fig. 8) constitutes an input to a transistor P9 for controlling the base current thereof. After inverting the square wave output from P9 in inverting and buffer amplifier 200 the signal is supplied to terminal 202 for feeding to part of the circuit shown on Fig. 9 and also via resistor R76 to another inverting amplifier 204 the output of which is differentiated on the one hand by C26 and R77 and is applied via R78 to terminal 206 and in the other case by capacitor C27, resistor R80 and is transferred via R79 to terminal 208.

The terminals 206 and 208 supply 7 Msec negative and positive going pulses respectively to the circuit of Fig. 9 to latch the data corresponding to putputs 6 to 9 on the one hand and outputs 1 to 4 on the other hand from a memory to be described in greater detail in relation to Fig. 9.

The output from P9 is also supplied via capacitor C23 to control the base current of transistor N 10 and the output of inverting amplifier 200 via capacitor C22 to control the base current of transistor N9. The two capacitors C23 and C22 constitute differentiating capacitors in conjunction with resistors R7 1 and R72 and the output from R9 which is developed across R73 provides one input to a NAND gate 210. The other input is provided from the one 0 output of a counter 212 which is supplied with the signal from the output of P9 as its clock pulse input. The effect is to produce in the output of the NAND gate a series of 85,uses pulses. With switch 214 open, the one 0 input of the counter is always high since the reset input of the counter 212 is permanently low.This means that every pulse appearing at the first input to the NAND gate 210 from across resistor R73 will appear in the output.

With switch 214 close, the second input of the NAND gate 210 is alternately high and low at a frequency corresponding to one-half the frequency of the square-wave signal from P9 and the result is to eliminate every alternate pair of 85 sec pulses in the sequence A further inverting amplifier 21 6 serves to reinvert the pulses to provide the C output at junction 21 8 and the pre-inverted version of this signal is available at terminal 220 as the CS signal. The C signal is supplied to the decoders to be described with reference to Fig. 10 and to the memory pull-up resistors to be described with reference to Fig. 9. The CS signal which is known as the chip select signal is used to turn the memory on and is supplied to the circuit to be described with reference to Fig. 9.

Turning now to Fig. 9, a memory integrated circuit which constitutes the memory 48 of Fig. 1 is provided on its A5, A6 and A7 input with the three address bits from Fig. 7. Inputs Al, A2, A3 and A4 receive the signals constituting the binary coded decimal address from the circuit of Fig. 5 from the terminals labelled Al to A4 on that figure.

The chip select signal (CS) is supplied to the control terminals of the integrated circuit and when this signal is low the chip is allowed to operate.

Input AO receives the signal which appears at junction 202 in Fig. 8 and which constitutes the inverted version of the square-wave output of transistor P9.

The outputs of the memory are labelled 01/6 through to 04/9.

The control signal by which the memory can be read is control signal C from Fig. 8 and this is applied via pull-up resistors R81 through to R84 to the four output lines. Since the pull-up resistors R81 etc. are not permanently connected to the negative rail but are pulsed so the outputs only appear at controlled points in time and for controlled periods of time.

In order to utilise standard components and yet provide ten different outputs, the memory is multiplexed. This is achieved by supplying the square-wave from terminal 202 to the AO input of the memory 48. When the AO input is high the first half of the memory locations can be addressed and when the AO input is low the other half of the memory locations can be addressed.By using the first half of the memory locations to provide binary outputs on the four output lines from the memory 48 for controlling the first four Triacs in the Triac bank 36, and by storing binary information in the upper half of the storage locations which is accessed when AO input is low, which information corresponds to the binary signals to be applied to the output lines for controlling the sixth to ninth inclusive of the Triacs in the bank of Triacs 36, so the information from the memory can be multiplexed by latching the information from each of the two halves of the memory 48 and temporarily storing the binary signals in two latches 106 and 108 so the information can be made available simultaneously after both of the latches have been loaded and the timing of the latching pulses derived from the circuit of Fig. 8 is selected so that the latch 106 is operated after a first one of the 85 ysec pulses making up the C signal and the latch 108 is operated after the immediately following 85,usec pulse of the C signal from terminal 21 8 in Fig. 8.

The four output lines from memory 48 are supplied to the D1, D2, D3 and D4 inputs of latch 106 and to the D6, D7, D8 and D9 inputs of latch 108.

Part of the object of the latching circuits is to obtain control signals for ten devices using binary signals and to this end a total of twelve outputs are derived from the two latches corresponding to outputs 01, 01, 0, 03, and 4 in the case of latch 106 and 06, 06, 07, 08, O8 and 09 in the case of latch 1 08.

Fig.10 shows the ten different logic decoding circuits which are hard wired from the outputs of Fig. 9 to provide control signals for the opto +LED drive circuit 46 shown in Figs. 1 and 11.

Each of the circuits is based on a similar device type 4025 and each of these devices is made up of three, 3-input NAND gates. In most of the cases all three inputs are hard wired although it will be noted that in some cases only two inputs are actually needed and two of the inputs to the NAND gate are strapped together.

In the event that switch 214 in Fig. 8 is closed, the divide-by-2 counter 212 is rendered operational and the result is that the NAND gate 210 only releases every other pair of control signal pulses (C).

The logic gates used for decoding have the characteristic that the output of the gate is only "hi" and hence the light corresponding to the number allocated to the output terminal of the gate (1, 2, 3 etc.) is on if all the inputs to the gate are "lo".

The control signal C which appears at terminal 218 in Fig. 8 and which is graphically illustrated in Fig. 8, is made up of a series of 85 Msec pulses each occurring immediately prior to the zero crossing of the alternating current supply voltage and serving to inhibit the output of the gates of Fig.10 for the period. This allows the latches to operate and the information to be changed (if necessary) in the latches and for the new information to be established on the outputs of the latches before the gates making up Fig. 10 become operational.

When alternate pairs of the control signal C pulses are missing because of the closing of the dim switch, O's are fed into the latch and these inhibit the outputs from the gates making up Fig.

10 for the whole of the cycle of the mains supply during which the two C signal pulses are missing.

It will be seen that the signal C is supplied as one input to each of the NAND gates of Fig. 10.

As a result of the logic, the four bits of binary multiplex from the memory 48 appear as ten separate control signals each of which is an on/off signal at each of the ten numbered outputs 1 to 10 in Fig. 10 and the corresponding terminals are numbered appropriately in Fig. 11. The terminals 1 to 10 are connected through ten decoupling resistors R85, R86 etc. to the bases of ten transistors NH2 in Fig. 11 and the latter are connected through current limiting resistors R95, R96 etc. to the 0-volts rail and two light emitting diodes connected in series constitute the output load for each of the transistors NH2. The first of the light emitting diodes in each case is the light emitting diode section of an opto-isolator one of which is shown at 222. The ten opto-isolators correspond to the opto-isolators 44 of Fig.

As mentioned before, a second light emitting diode of which one is designated by reference numeral 224 is connected in series with each of the light emitting diode sections of the optoinsulators making up the isolator bank 44 and one such light emitting diode is identified by reference numeral 224. These second light emitting diodes correspond to the array of light emitting diodes 122 described with reference to Fig. 1 and typically mounted in a circular array on the front panel of the equipment.

When any one of the transistors NH2 is turned on, the two light emitting diodes associated therewith are caused to conduct and emit light. In the case of the isolator, a pulse is immediately generated in the light sensitive junction associated therewith as previously described. In the case of the upper light emitting diodes, such as diode 224, the conduction of current therethrough simply causes the light emitting diode to glow and indicate which of the radial arms of the array is currently being supplied with operating current.

One-amp by-pass diodes are connected in parallel with the light emitting diodes 122 and these correspond to the by-pass diodes 1 24 of Fig. 1. Each of the diodes is connected to a common bus bar 226 which is in turn connected via three series connected lamp diodes 228, 230 and 232 to the smoothed output of the earthed power supply 24 of Fig. 1 and the diodes are selected so that in the event that any of the light emitting diodes in the bank 122 becomes open circuit, appropriate load is provided for the continued operation of the circuit which would otherwise fail since the light emitting diodes in the bank 122 are connected in series with the light emitting diode sections of thQopto-isolators in the isolator bank 44.

Claims (21)

1. in a control system for controlling an array of lights arranged in an array of rows and columns or an array of concentric circles, and in which each of the lights has a live and neutral terminal which must be connected to live and neutral bus bars respectively for the light to be illuminated, solid state voltage or current controlled switches are provided in links connecting the live terminals of the lamps to the live bus bar and the neutral terminals of tie lamps to the neutral bus bar and control circuits are provided for selectively closing the solid state switches so as to produce any desired pattern of lights in the array.

2. A control system as claimed in claim 1 in which the number of lamps which can be so connected at any instant is limited to a given percentage of the total number of lamps in the array and the control circuit is programmed accordingly thereby limiting the current requirements.

3. A control system as claimed in claim 2 in which a visual impresesion that more of the lamps than the given percentage are illuminated at any instant is obtained by continuously switching different lamps into and out of circuit.

4. A control system as claimed in claims 1, 2 or 3 in which in the circuits controlling the operation of the solid state switches, circuit means is provided for generating a repetitive sequence of electrical signals, the repetition frequency of which is controllable, so that a given pattern of lights in the array can be moved either from one side to the other, or from top to bottom, or in a circular array, either from the centre outwards, or from the perimeter inwards, or in a radial manner around the circular array, the movement of the pattern being in a series of steps each step corresponding to a fixed pattern of lamps being illuminated in the array and each transition from one step to the next representing the change from one fixed pattern to the next fixed pattern.

5. A control system as claimed in claim 4 in which the said next fixed pattern is the same pattern but displaced in space within the array.

6. A control system as claimed in claim 4 or 5 in which further circuit means is provided, responsive to an electrical audio signal, for producing a control voltage in response to some parameter of the audio signal, the control voltage serving to control the frequency of the pulse generator producing the sequence of repetitive pulses so that the movement of the pattern of light around the array can be speeded up or slowed down depending on the particular chosen parameter of the audio signal.

7. A control system as claimed in claim 6 in which the audio signal is a music signal and the parameter is the amplitude of the signal or the amplitude of a part of the signal obtained by filtering.

8. A control system as claimed in claim 6 or 7 which includes means responsive to a ceasing of the audio signal to produce further control signals to cause the array of lights to change patterns slowly and continuously.

9. A control system as claimed in any of the preceeding claims 6 to 8 which include additional circuit means for generating a sequence of overriding control signals which change the programmed pattern in a cyclic manner so that the particular pattern of light which is moved in sympathy with the audio signal is itself changed periodically so that a sequence of different patterns appear each one moving in sympathy with the audio signal.

10. A control system as claimed in claim 9 in which the period of time between the changes of pattern is controllable so that short or longer periods of time between changes can be selected or the pattern changed to the next after a given number of sweeps.

11. A control system for controlling the operation of a plurality.of lamps which includes a corresponding plurality of solid state switches and individual control circuits for triggering the solid state switches between conductive and nonconductive states, circuit means for generating switching pulses for feeding to selected ones of the individual control circuits thereby to produce switching of selected ones of the said plurality of solid state switches and thereby cause illumination of selected ones of the plurality of lamps, and further circuit means for controlling the operation of the said first circuit means to modulate the operation of the latter in response to and electrical signal derived from a music signal, an alternating current power supply for the lamps, the said plurality of solid switches being connected so as to supply alternating current from the said alternating current supply to the lamps according to the control signals supplied thereto and further circuit means which synchronises the generation of the switching signals to ensure that a change in the switching signals occurs only at a zero crossing of the waveform of the alternating current source for the lamps and also only occurs at full cycle periods so that only full cycles of alternating current are supplied to the lamps.

12. A control system is claimed in claim 11 in which a dimming of the lamps is achieved by a further circuit means adapted to remove switching signals which would otherwise by supplied to the solid state switches thereby to remove from the switched outputs whole cycles of alternating current beginning and ending at zero crossings of the alternating current waveform so as to leave in full cycle sinewave waveforms of alternating current spaced by empty full-cycle periods.

13. A control system as claimed in claim 11 or 12 in which the signal derived from the music signal for modulating the generation of the switching signals is formed by amplifying the music signal by an amplifier having a logarithmic input/output function so that the output signal amplitude is a logarithmic function of the input signal amplitude and the amplitude changes in the output signal therefore correspond to percentage changes in volume.

14. A control system as claimed in claim 1s1 or 12 or 13 wherein power for the lamps is derived from an alternating current supply having a frequencyd of 50 or 60 herz and wherein alternate complete cycles of alternating current are removed by the control system from the alternating current supplied to the lamps to produce a flickering light.

1 5. A control system as claimed in any of claims 11 to 14 wherein timing circuit means is provided for producing a repetetive all change in the pattern of lamps illuminated simultaneously as a group and means is provided for adjusting the times at which the changes in the overall pattern occur.

16. A control system as claimed in any of claim 1 5 in which the timing circuit means also funcations so as to change not only the pattern or group of lamps which are to be simultaneously illuminated but also the sequence of the electrical signals supplied to the individual control circuits for the solid state switches so as to sequentially vary the sequence of control signals supplied to the individual control circuits so that with each change, the movement of the pattern of lights is changed for example from a mode in which a pattern is swept in one direction through an array of lamps to another mode in which the same pattern is swept in an opposite direction or in a different manner through the said array of lamps.

1 7. A control system as claimed in claim 1 6 in which the timing circuit is adjustable so as to permit the changes in mode of operation to occur either at relatively short or relatively longer intervals of time.

18. A control system as claimed in any of claims 11 to 1 7 which includes a plurality of solid state switches as claimed in claim 1 to allow more complex pattern changes in an array of lamps to be obtained by switching not only the connections between the live bus bar and the lamps but also the neutral bus bar and the lamps.

19. A control system claimed in any of the preceding claims in which the solid state switches are so called Triacs and electrical isolation between a separate power supply for triggering the Triacs and circuits producing the switching signals for the Triacs is achieved by using optoelectronic devices in which the transfer of ,information occurs via a modulation of the output of a light emitting diode which is received by a light sensitive semiconductor junction, the link being contained within a single component having input and output circuits for receiving signals for modulating the output of the light emitting diode and delivering electrically isolated signals corresponding to the input signals by appropriate amplification of the output from the light sensitive junction.

20. A control system as claimed in claim 19 in which voltage regulation of the power supply for the optroelectronic devices is achieved by connecting a voltage dependent resistor across the supply mains input to the system having an appropriate voltage/resistance characteristic for removing excessive voltage spikes.

21. Control systems for controlling lights constructed, arranged and adapted to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.