GB2054996A - D/A converter; MOST IC - Google Patents

Abstract

In order to avoid having to provide resistor ladder networks in an analogue to digital converter fabricated as an MOS integrated circuit, an array of MOS transistors (T1 to T6, T1D to T6D) are provided to form a weighted current source which draws current through a load (40) across which the analogue output voltage (VOUT) is developed. Each bit- stage of the DAC comprises an enhancement transistor (Tn) and a depletion transistor (TnD), whose source drain paths are connected in series between the load (40) and a supply rail (30), the W/L ratios of the transistors (Tn, TnD) of each stage being a factor of 2 greater or less than those of an adjacent stage. The enhancement transistor (Tn) of each stage is rendered conductive or non- conductive at will in response to an associated bit of the applied digital signal and thereby either connects or not connects the stage into the current path through the load (40). <IMAGE>

Description

SPECIFICATION Digital to analogue converter The present invention relates to a digital to analogue converter, particularly but not exclusively to a converter fabricated as an MOS integrated circuit.

An application of such a digital to analogue converter is in a remote control receiver in which the analogue output produced is used for driving the control circuits of a television receiver. In one known remote control receiver, the digital to analogue conversion is achieved by varying the mark-space ratio of a 8 KHz switched waveform. External filtering is used to convert the switched waveform to d.c.

analogue voltage. The need for external filters is undesirable because it is preferred to fabricate as much of the circuit as is possible in an integrated form.

A static digital-to-analogue converter can be made in bipolar integrated circuit technology using resistor ladder networks to generate binary weighted current sources. However resistor ladder networks are not easily achieved in MOS integrated circuit technology.

Accordingly it is an object of the invention to provide a digital-to-analogue converter which can be fabricated in MOS integrated circuit technology and does not require the provision of external filter circuits.

According to the present invention there is provided a digital to analogue converter comprising an input for receiving a digital signal, and an array of MOS transistors, forming a weighted current source coupled to the input, the array having an output on which an analogue output corresponding to a digital input is provided.

The digital to analogue converter in accordance with the present invention is able to provide a monotonic, that is linear, conversion of an input digital signal and provide a static output.

In an embodiment of the analogue to digital converter in accordance with the present invention, the weighted current source comprises a number of stages, each stage being associated with a respective digit of an input signal, all said stages being connectable at will to a bias voltage source in response to an applied digital signal and being connected to a common load from which the analogue output is derived.

Each of the stages may comprise an enhancement MOS transistor and a depletion MOS transistor of the same conductivity type having their source-drain paths connected in series between the common load and a supply raid, the gate of the enhancement transistor being connectable at will to the bias voltage source, the width to length ratios of the depletion and enhancement transistors of each stage being a factor of 2 greater or less than those of an adjacent stage.

Conveniently at least the enhancement transistors of at least all but the least significant bit stage, each comprise a multiple transistor formed by two or more transistors having a common gate and substantially the same width to length ratios.

The bias voltage source may comprise a comparator for comparing a reference voltage with another voltage, the bias voltage appearing on the output of the comparator. A reference voltage source may comprise an enhancement MOS transistor and a depletion MOS transistor having their sourcedrain paths connected in series, the width to length ratio of the enhancement transistor being substantially equal to the total width to length ratios of the enhancement transistors of all the stages and the width to length ratio of the depletion transistor being substantially equal to the total width to length ratios of the depletion transistors of all the stages. The enhancement transistor of the reference voltage source comprises a multiple transistor.

If necessary a plurality of weighted current sources are coupled to a common bias voltage source.

The MOS transistors of the bias voltage source and those of the or each weighted current source are fabriated as an integrated circuit and a load of the bias voltage source and the common load of the or each weighted current source each comprise an externally connected resistor. The advantages of external resistors over internal resistors are that the resistors can be accurately matched and have a low temperature coefficient and the values of the resistors can be varied within defined current limits, to suit the application.

The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a simplified schematic circuit diagram of a digital to analogue converter in accordance with the present invention, Figure 2 is a diagrammatic view of a multiple enhancement transistor for use in the reference network of the bias voltage source, Figure 3 is a diagrammatic view of a number of multiple enhancement transistors for use in respective stages of the weight current source of the digital to analogue converter shown in Figure 2, and Figure 4 is a detailed current diagram of a 6 bit digital to analogue converter in accordance with the present invention.

Figure 1 may be considered conveniently as comprising two parts 20 and 22. The part 20 comprises means for producing a bias voltage VBlAS on a line 24 which supplies this bias voltage to the other part 22 which constitutes a weighted current source which is responsive to a digital signal and produces an analogue output voltage VOUT on a line 26. Both parts of the illustrated circuit comprises MOS transistors of the same conductivity type, conveniently n-channel. The circuit includes a Vnn rail 28 at 12 volts, a Vss rail at zero volts or circuit ground and a further rail 32 at-V2 volts, in this embodiment V2 = 17 volts.

The means for producing the bias voltage comprises a voltage comparator 34 which prodices the bias voltage VBIAS by comparing a reference voltage VREF applied to the non-inverting input of the comparator 34 with a voltage V1 applied to the inverting input of the comparator 34. The voltage V1 determines the desired output voltage. The reference voltage VREF is derived from the bias voltage on the line 24 by a reference network including an enhancement MOS transistor TR whose drain-source path is connected in series with the drain-source path of a depletion MOS transistor TRD and a load resistor 36, connected between the rails 30, 32. The gate of the transistor TR is connected to the line 24 and its source together with the gate of the transistor TRD are connected to the rail 30.The reference voltage VREF is taken from a junction 38 of the drain of the transistor TRD and the resistor 36.

A capacitor C is connected between the output of the comparator 34 and the rail 30 to avoid oscillation.

In it operation, the voltage VREF and the voltage V1 are compared in the comparator 34 and the bias voltage Veis is applied to the gate of the transistor TR. With this closed loop arrangement the bias voltage Vales is adjusted automatically until the reference voltage VREF equals V1. The current through the transistor TR equals (V2-V1)/R, where R is the value of the resistor 36.

Turning now to the other part 22 of the illustrated circuit, the weighted current source comprises a plurality of stages equal in number to the number of the bits, e.g. 6 bits, in the digital signal. Apart from the matter of the width to length ratios of the transistors used, which matter will be discussed later, each of the stages is similar to the other and accordingly only one will be described in detail.

Each stage comprises an enhancement MOS transistor T1 to T6 whose source-drain path is connected in series with the source-drain path of a depletion MOS transistor T1 D to T6D. The gate of the enhancement transistor T1 to T6 connected to the movable contact of a change-over switch S1 to S6. In the switch position shown the gate of the transistor T1 to T6 is connected to the bias voltage line 24 and in the other position, not shown, the gate is connected to the rail 30. The drain of the transistor T1 to T6 and the gate of the transistor T1 D to T6D are also connected to the rail 30. The drains of the transistors Ti D to T6D are all connected to one end of a load resistor 40 having the same value as the resistor 36, namely R, the other end of the resistor 40 is connected to the rail 32.The output analogue voltage on the line 26 is derived from the one end of the resistor 40.

The cascode connection of these transistors T1 + T1 D to T6 + T6D ensures that these current sources will have a high output resistance provided that the drain of the depletion transistor is at least 4 volts above Vss. Calculations indicate a current source resistance of about 400 KQ at 1 mA and 200 KQ at 2 mA, which resistance is high compared with the load resistance, R say 5.6 KQ, which relationship is necessary to give a good linearity of the output.

As mentioned eariler each stage of the part 22 is associated with a respective bit of the digital signal which is applied to the switches Si to S6. In order to provide the necessary binary weighting to each stage, each transistor T1 to T6 and T1 D to T6D is binary weighted multiple of a unit size of width to length ratio, in the case of the enhancement transistors T1 to T6 the unit size is 6 H/68 and of the depletion transistor T1 D to T6D, the unit size is 20 /7,u. Each stage after is a factor of 2 greater than the preceding stage so that:: T1 = 32x6/6,u T1D = 32x20"7,u T2= 16x6/6 T2D = 16x20/7 T3= 8x6/6 T3D= 8x20/7 T4= 4x6/6 T4D= 4x20/7 T5= 2x6/6 T5D= 2x20/7 T6 = 6/6 T6D = 20/7 As the current source, transistor TR, of the reference network is made equal to the combined total of the transistors T1 to T6, its width to length ratio will be 63 (that is 32 + 1 6 + 8 + 4 + 2 + 1) x 6/68.

By similar reasoning the width to length ratio of the transistor TRD is 63 x 20/7JU.

Thus, in Figure 1, if the gates of the transistors T1 to T6 are all connected to VelAs by the switches S1 to S6, that is all the bits of the digital signal are "0", the combined current through these transistors is equal to the current through the transistor TR and hence VOUT = VREF = V1. Alternatively if the gates of the transistors T1 to T6 are all connected to Vss, that is all the bits of the digital signal are "1", then no current flows and VOUT = V2. By operating the switches S1 to S6 in a desired sequence it is possible to obtain 63 steps or 64 (26) states of analogue output between V1 and V2. For example, with a VBIAS of 2.25 volts, V2 of 17 volts and a value of R = 5.6 K for the resistors 36 and 40 to provide an output voltage of about 5.0 volts when all the switches S1 to S6 are connected to the rail 24 and an overall swing of 12 volts, it has been calculated that an average step height of 1 90.5 mV is obtained over the whole range.This may be illustrated in the following tabular summary of three changes in binary input:

Binary input VoUT(voltS) Step AV(mV) 000000 4.993 188 000001 5.181 011111 10.865 191 100000 11.056 111110 16.807 193 At 000000 IOUT = 2.15 mA In operation, the small increase in AV at higher output voltages is explained by the channel length shortening of the depletion transistor(s) T1 D to T6D increasing its (or their) gain. This in turn increases the drain voltage of the associated enhancement transistor(s) and so increases the size of the output voltage step AV as is shown in the above tabular summary.

In a practical circuit the accuracy of the voltage steps depends on the degree of matching of the transistors used in forming the weighted current source. The transistors must be designed so as to cancel out the effects of overall process variations. However point defects of variations in transistors cannot be eliminated by design and if such transistors are present then malfunctioning of the digital-toanalogue converter would occur.

One practical way of overcoming the effects of process variations is to fabricate the current source transistors as arrays of unit size transistors, which arrays will be referred to a multiple transistors.

Figure 2 illustrates schematically a multiple transistor 42 for use as the enhancement transistorTR in Figure 1. It will be recalled that the width to length ratio of this transistor is 63 x 6/6. In the illustrated multiple transistor 42, the source of electrodes 44 and the drain electrodes 46 are interconnected by a multiple path channel 48 in the form of a 2-dimensional lattice. A meanderline or sepentine shaped gate 50 is disposed on the lattice to provide 63 channels, each having a width to length ratio of 6 d6 6,u/6,u. The overall size of the multiple transistor 42 is 1 62,u x 126 y.

A similar type of fabrication can be used to provide the enhancement transistors T1 to T6 (Figure 1). Such a construction is shown schematically in Figure 3. For convenience of identification, each of the multiple transistors is separated from its adjacent one by a broken line and the transistor is identified by the samefeference as in Figure 1. Further the drain and gate contact of each transistor are identified by Dn and Gn, respectively, where n is the number of digital bits and in the illustrated embodiment n = 6.

The transistors T1 to T3 comprise 32, 16 and 8 x 6 u/6 u channels and can conveniently be formed in an 8 x 7 lattice, the transistor T1 having two drain electrodes D1 and a meanderline gate G 1, the transistor T2 having single drain D2 and.a gate G2 with two parallel legs and the transistor T3 having a single drain D3 and gate G3. As the sources S of these electrodes are all connected to Vss, there is no need to distinguish one source from another. As is evident the transistors T4 to T6 are configured to provide 4, 2 and 1 > c 6 6 y/6,u channels. The total area occupied by these multiple transistors is 210 x 126,u.

Although not shown, the depletion transistors TRD and T1 D to T6D which have a unit size of 20 ,u/7 y can be fabricated in a similar way.

In order to reduce the effects of voltage drop along the different conductors it may be necessary to metallise the source and drain fingers.

Figure 4 shows a practical digital to analogue converter constructed in n-channels MOS technology. Where appropriate, the same reference numerals have been used as in Figure 1 to indicate those parts which correspond in Figure 4.

The part 20 of the circuit includes a comparator 34 based on a long tail pair amplifier comprising enhancement MOS transistor 52, 54, the current through which transistors is determined by another enhancement MOS transistor 56 whose gate is connected to a current mirror circuit 58. The voltage V, and the reference voltage VREF are applied to the gates of the transistors 52, 54, respectively. The outputs 60, 62 of the long tail pair amplifier are derived from its loads comprising cascode connected depletion transistors. These outputs 60, 62 are connected to another current mirror circuit 64 whose output is connected to a buffer amplifier including an enhancement MOS transistor 66 and a depletion MOS transistor 68.The bias voltage VBIAs is derived from the drain of the transistor 66, which drain is also connected to an internal capacitor C for preventing oscillation and to the gate of the transistor TR.

As in the case of Figure 1 , the purpose of the transistors TR and TRD and the resistor 36 is to enable a VREF which is substantially equal to V to be derived from the junction 38. The use of the long tailed pair amplifier arrangement transistors 52, 54 and 56, enables VREF to be maintained within + 10 mV of Vi, this tolerance figure being well below the size of a step AV in the output voltage.

Turning now to the other part 22 of the circuit, there are six current weighted stages comprising the transistors Ti to T6 and T1 D to T6D, as in Figure 1. However the switches S1 to S6 comprise pairs of enhancement MOS transistors 70, 72 having their source-drain paths connected in series between the VelAs line 24 and the rail 30. The gate of the transistor T1 is connected to a junction 74 of the source of the transistor 70 and the drain of the transistor 72. The gates of each pair of the transistors 70, 72 are connected, respectively, to the 0,, Qn outputs, where n is the number of stages, of associated flipflops (not shown). Thus only one transistor of each pair of transistors 70, 72 can be conductive at any one time.For example if the binary input to the most significant stage is "0" then Q, is "0" and Q, is "1", the transistor T1 is conductive and the current through the resistor 40 produces a voltage change thereacross. Alternatively if the binary input is 1 , then Q1 is "1 " and Q1 is "0", the transistor T1 in nonconductive and hence the stage effectively presents an open circuit.

In order to facilitate the fabrication of the enhancement transistors 70, 72, their width to length ratios are the same and are equal to the unit size, namely 6 y/6 u, of the enhancement transistors TR and T1 to T6. The resistors 36 and 40 are external of the integrated circuit chip and have the following advantages over internal resistors, namely (a) the resistors 36, 40 can be matched accurately and have a low temperature coefficient and (b) the values of R can be varied, within defined current limits, to suit the application. With the mentioned dimensions of the depletion and enhancement MOS transistors, load currents of up to 3 mA are possible. When fabricated the circuit illustrated in Figure 4 does not require any extra pins compared with a circuit constructed with internal resistors because in order to permit the votlage V2 to be independent of the long tailed pair amplifier voltage VDD, rail 28, a V2 pin would have to be connected to the internal resistors. With external resistors, a pin is available providing a VREF output. If desired a capacitor 76 shows in broken lines may be connected between VREF and ground, the rail 30, to prevent pulses from being fed into the comparator.

If desired one bias voltage generator, the part 20 in Figures 1 and 4 can be used for several digital to analogue converters on the same chip.

Claims (7)

1. A digital to analogue converter comprising an input for receiving a digital signal, and an array of MOS transistors forming a weighted current source coupled to the input, the array having an output on which an analogue output corresponding to a digital input is provided.

2. A converter as claimed in Claim 1, wherein the weighted current source comprises a number of stages, each stage being associated with a respective digit of an input signal, all said stages being connectable at will to a bias voltage source in response to an applied digital signal and being connected to a common load from which the analogue output is derived.

3. A converter as claimed in Claim 2, wherein each of the stages comprises an enhancement MOS transistor and a depletion MOS transistor of the same conductivity type having their source-drain paths connected in series between the common load and a supply rail, the gate of the enhancement transistor being connectable at will to the bias voltage source, the width to length ratios of the depletion and enhancement transistors of each stage being a factor of 2 greater or less than those of an adjacent stage.

4. A converter as claimed in Claim 3, wherein at least the enhancement transistors of at least all but the least significant bit stage, each comprises a multiple transistor formed by two or more transistors having a common gate an substantially the same width to length ratios.

5. A converter as claimed in Claim 3 or 4, wherein the bias voltage source comprises a comparator for comparing a reference voltage with another voltage, the bias voltage appearing on the output of the comparator and a reference voltage source comprising an enhancement MOS transistor and a depletion MOS transistor having their source-drain paths connected in series, the gate of the enhancement transistor being coupled to the output of the comparator, the width to length ratio of the enhancement transistor being substantially equal to the total width to length ratios of the enhancement transistors of all the stages and the width to length ratio of the depletion transistor being substantially equal to the total width to length ratios of the depletion transistors of all the stages.

6. A converter as claimed in Claim 5 wherein the enhancement transistor of the reference voltage source comprises a multiple transistor.

7. A digital to analogue converter constructed and arranged to operate substantially as hereinbefore described with reference to, or as shown in, the accompanying drawings.

7. A converter as claimed in any one of Claims 2 to 6, wherein a plurality of weighted current sources are coupled to a common bias voltage source.

8. A converter as claimed in any one of Claims 2 to 7, wherein MOS transistors of the bias voltage source and those of the or each weighted current source are fabricated as an integrated circuit and a load of the bias voltage source and the common load of the or each weighted current source each comprise an externally connected resistor.

9. A digital to analogue converter constructed and arranged to operate substantially as hereinbefore described with reference to, or as shown in, the accompanying drawings.

New claims or amendments to claims filed on 22/9/80 Superseded claims 1-9 New or amended claims:

1. A digital to analogue converter comprising an input for receiving a digital signal, a weighted current source comprising a plurality of parallel arranged stages, each stage being associated with a respective digit position of an input signal, all said stages being connectable at will to a bias voltage source in response to an applied digital signal and being connected to a common load from which an analogue output corresponding to a digital signal can be derived, wherein each of the stages comprises an enhancement MOS transistor and a depletion MOS transistor of the same conductivity type having their source-drain paths connected in series between the common load and a supply rail, the gate of the enhancement transistor being connectable at will to the bias voltage source, the width to length ratios of the depletion and enhancement transistors of each stage being a factor of 2 greater or less than those of an adjacent stage.

2. A converter as claimed in Claim 1, wherein at least the enhancement transistors of at least all but the least significant bit stage, each comprise a multiple transistor formed by two or more transistors having a common gate and substantially the same width to length ratios.

3. A converter as claimed in Claim 1 or 2, wherein the bias voltage source comprises a comparator for comparing a reference voltage with another voltage, the bias voltage appearing on the output of the comparator and a reference voltage source comprising an enhancement MOS transistor and a depletion MOS transistor having their source-drain paths connected in series, the gate of the enhancement transistor being coupled to the output of the comparator, the width to length ratio of the enhancement transistor being substantially equal to the total width to length ratios of the enhancement transistors of all the stages and the width to length ratio of the depletion transistor being substantially equal to the total width to length ratios of the depletion transistors of all the stages.

4. A converter as claimed in Claim 3, wherein the enhancement transistor of the reference voltage source comprises a multiple transistor.

5. A converter as claimed in any one of Claims 1 to 4, wherein a plurality of weighted current sources are coupled to a common bias voltage source.

6. A converter as claimed in any one of Claims 1 to 5, wherein MOS transistors of the bias voltage source and those of the or each weighted current source are fabricated as an integrated circuit and a load of the bias voltage source and the common load of the or each weighted current source each comprise an externally connected resistor.