GB2054923A - Self-testing alarm systems - Google Patents

Abstract

A self-testing alarm system comprising means for inhibiting outputs of the system and testing means for simulating alarm conditions and monitoring the response of the system to the simulated alarm conditions. The system further comprises means for detecting inhibition of the system outputs, means for providing a system test output in response to detection of inhibition of the system outputs, means for enabling the testing means in response to the system test output, means for maintaining said inhibition whenever the system test output is provided, and means for annunciating failure to remove said inhibition after testing of the system.

Description

SPECIFICATION Self-testing alarm systems.

The present invention relates to self-testing alarm systems.

The testing of alarm systems has always posed problems as a full scope test must result in the activation of system outputs such as the sounding of alarm bells. Repeated automatic full scope tests of extensive systems cannot be contemplated as personnel intended to respond to the alarms cannot distinguish between real and test alarm signals. In the case of fire protection alarm systems where the system responds to alarms by for example automatically releasing extinguishant, full scope tests obviously cannot be contemplated.

In view of the problems it is known to provide means for inhibiting the outputs of alarm systems to enable testing of all system components except for output devices such as alarm sounders or extinguishant release solenoids. Known inhibiting circuits are generally manually operated and enable the manual initiation of simulated alarm conditions and monitoring of the system response.

As the complexity and the demanded reliability of alarm systems has increased, the manual testing of each of a series of system subcomponents has become less acceptable, primarily because manual testing can only be as reliable as the personnei operatlng the system. It should be noted that frequent automatic testing reveals faults early and this contributes to system availability. This is not possible with manual testing because time-consuming manual tests inevitably decrease system availability. Hence automatic testing gives access to high system availability which was previously unachievable.

Testing of a full system can theoretically be effected simply by implementing a series of the known manual testing procedures automatically.

In fact however to include automatic test equipment of the complexity of manual test equipment would be expensive and would not present data in a sufficiently concentrated form to be useful. Automatic full-system testing also carries with it inherent problems. For example if the system outputs are inhibited during test implementation and no faults are detected, the inhibit must be removed after the completion of testing or the system will be incapable of responding to real alarm conditions with potentially catastrophic results. As a further example, the system must be inhibited before testing and the inhibit must not be removed until all simulated alarm conditions have been cleared, otherwise the system would respond to simulated alarms by for example releasing extinguishant, again with potentially catastrophic results.For the above reasons there has been some reluctance to implement fully automatic systems.

It is an object of the invention to provide a selftesting alarm system which is provided with means to prevent the above problems arising.

According to the present invention there is provided a self-testing alarm system comprising means for inhibiting output of the system, and testing means for simulating alarm conditions and monitoring the response of the system to the simulated alarm conditions, characterised in that the system comprises means for detecting inhibition of the system outputs of the inhibiting means, means for providing a system test output in response to detection of inhibition of the system outputs, means for enabling the testing means in response to the system test output, means for maintaining said inhibition whenever the system test output is provided, and means for annunciating failure to remove said inhibition after testing of the system.

Preferably means are provided for ensuring that spurious test outputs which themselves result from faults also inhibit the system outputs.

Preferably means are provided to prevent the system assuming a test condition in the event of any alarms in the system being activated.

Preferably the inhibiting means is operative to open contacts in series with the coils of system output relays in order to prevent system outputs during testing. The potential generated across the open contacts can serve as a 'clear to test' signal enabling generation of the system test output. The testing enabling means may comprise a transistor driven by the system test output. Preferably a gate is provided which prevents the transistor from responding to the system test output in the absence of system inhibition.

The means for maintaining the inhibition of the system whenever the system test output is provided may be a feedback loop returning the system test output as a substitute system inhibition signal. For example, the output of the transistor driven by the system test output may be returned to the inhibition means.

The means for annunciating failure to remove system inhibition may comprise a device for detecting when the system has been inhibited for a predetermined period and for annunciating system failure thereafter. Thus if the system inhibit is maintained too long, for example as a result of a fault in the inhibiting means, or a fault in the system test output means, the fault is annunciated.

It will be appreciated from the above that the inhibition detecting means prevents the system assuming its test condition until inhibition of the system has been positively identified, that the inhibition maintaining means prevents the system outputs from being enabled during a test even if the inhibition means proper fails, and that the failure annunciating means warns that the system has been rendered inoperative in permanent test mode.

To enable the system to meet a wide variety of operating conditions, such as the number and distribution of smoke or flame detectors for example, and the number and type of output devices, the system component inputs and outputs are preferably programmable so that unused inputs and outputs can respsond positively to testing. This may be achieved by providing manual switches which can be operated to provide inputs programmed to indicate that signals are or are not expected to be received during a self-test sequence. If these expectations are not met, a fault signal is generated. This greatly improves system flexibility.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 shows an input voting circuit; Fig. 2 shows an output relay circuit; Fig. 3 shows a common facilities circuit; Fig. 4 shows a self-test control circuit; Fig. 5 shows an auxiliary facilities circuit; and Fig. 6 shows a response testing circuit.

Referring to the drawings, the illustrated embodiment of the invention comprises a voting circuit (Fig. 1 ) which receives the outputs of for example a series of smoke detectors and initiates system responses such as extinguishant release in the event of two or more detectors being activated, a relay circuit (Fig. 2) which receives the output of the voting circuit and controls system response accordingly, and a facilities card (Fig. 3) which provides common facilities required for effective operation of the system. The relay circuit (Fig. 2) also incorporates relay condition annunciating and testing circuits.

In addition the described embodiment comprises a self-test control circuit (Fig. 4) which generates signals necessary to perform a testing sequence, an auxiliary facilities card (Fig. 5), and a simulated alarm response testing circuit (Fig. 6).

The auxiliary facilities card (Fig. 5) provides an interface between the control circuit of Fig. 4 and testing circuits in the system.

Referring now to Fig. 1 in particular, assuming for the sake of simplicity that the system is intended to detect smoke in a single area only and to release extinguishant in response to smoke being detected by five smoke detectors distributed in that area, the five detectors are connected via interface circuits (not shown) to respective ones of inputs 1 to 5. Further input terminals 6, 7 and 8 are provided but are unused.

The inputs 1 to 8 are connected by inverters 9 to terminals 10 to 1 7. Whenever a detector provides a 'smoke detected' output to an interface circuit (not shown) the voltage at the respective one of terminals 10 to 1 7 goes low. The signals at terminals 10 to 1 7 are applied via resistors 18 to the negative inputs of trip amplifier 19 and 20.

The trip threshold of amplifier 20 is such that it is triggered if one or more of the signals appearing at terminals 10 to 1 7 goes low, thereby providing at its output a "1 up" signal indicative of one detector having been actuated. The threshold of amplifier 19 is such that it is triggered if two or more of the signals appearing at terminals 10 to 1 7 goes low, thereby providing at its output a "V1" signal indicative of at least two detectors having been actuated. The "V1" signal thus constitutes a reliable 'voted' output which cannot be the result of a simple fault in one detector. If it were desired to derive a signal indicative of at least three detectors having been actuated rather than at least two, a link can be connected between terminals 21 and 22 to shift the threshold of amplifier 1 9.

The V1 signal is passed via gate 23 and a high impedance open collector driver to a transistor 24 which energises a common alarm terminal 25 linked to the facilities circuit (Fig. 3) and a voted executive output terminal 26 linked to the relay circuit (Fig. 2). The signal at terminal 25 of Fig. 3 turns on transistor 27, thereby energising coil 28 and closing contacts 29 to energise a common alarm (not shown). The signal at terminal 26 of Fig. 2 energises coil 30 thereby closing contacts 31 to energise an extinguishant release solenoid (not shown). Thus the system has responded in a conventional way to the actuation of its detectors.

The relay circuit comprises four further relay contact and coil sets 32,33; 34,35; 36,37; and 38, 39. In the simple exemplary systein, none of these relays are used.

When one or more of the detectors indicates an alarm, it is necessary to annunciate this fact. For this purpose the V1 and 1 up signals are applied to respective gate circuit 40, 41 which are operative to provide an output to turn on a transistor 42.

This transistor delivers current via terminal 43 to turn on transistor 44 (Fig. 3). This energises relay coil 45, thereby closing contacts 46 and energising an alarm sounder (not shown).

When an alarm has been annunciated, it can be "accepted" i.e. the system controller can indicate that the alarm condition has been noted, by depression of button 47 (Fig. 3) which applies a positive potential to terminal 48 which is linked to the voting circuit (Fig. 1). This signal is inverted to form the signal ACPT which is applied to gate 40 to cause transistor 42 to turn off and silence the alarm sounder. The common alarm is not cancelled (see terminal 26, Fig. 1).

If it is desired to inhibit the output of the voting circuit, for example to allow manual testing of the circuit, a button 49 may be depressed. This applies an inhibit signal NHB to to gate 23, blocking the V1 output and thereby preventing a voted executive output appearing at terminal 26. The lNHB signal is also used to turn on transistor 51 and to energise 'inhibited' LED 52. Transistor 51 delivers current via terminal 53 which is linked to the facilities circuit (Fig. 3). This current causes the energisation of relay coil 54 and contacts 55 close accordingly. These contacts are used to drive a "part of system inhibited" lamp (not shown).

In the present case, no executive outputs are required in response to the appearance of the '1 up' signal. To accommodate situations where such an output would be useful, the '1 up' signal is applied to a gate 55 (Fig. 1) which is exactly equivalent to the gate 23 to which the V1 signal is applied. The gate responds to the '1 up' signal in the absence of the inhibit signal to turn on transistor 56 and provide a 1 up executive output at terminal 57.

Referring now to Fig. 4, features of the self-test system will be described. A prerequisite of a safe self-test sequence is inhibition of the output functions of the system. Accordingly a self inhibit signal SI is provided at the output 58 of a latch 59. The latch 59 is controlled by a two input gate 60 which receives an ALARM signal on input 61 and the output of a further gate 62. The ALARM signal indicates whether or not the system is already in an 'alarm actuated' state and is derived from an ALARM signal appearing at input 63 via a 500 mS delay circuit formed by capacitor 64 and resistor 65. If an alarm condition is indicated at input 61 , the gate 60 cannot set the latch and therefore a self-test sequence cannot commence. Accordingly, the self-test functions in no way interfere with the normal alarm processing of the system.

Assuming no alarm conditions, an automatic self-test can be initiated periodically by setting switch 66 as shown and selecting the period of LF oscillator pair 67, 68 using DIL switches 69. The output frequency of oscillator 68, which is locked to the frequency of oscillator 67, is passed by a gate 70 enabled by switch 66 to the gate 62 and thence to gate 60 which sets the latch 59. Again assuming no-alarm conditions, a selftest sequence can be initiated by operating switch 66 to block the output of oscillator 68 and depressing manual test button 71. This sets a 100 mS pulse generator 72 to apply a pulse to gate 62 to enable gate 60 to set latch 59. In either manual or automatic operation, the first result of the initiation of a self-test sequence is the appearance of the SI inhibit signal (terminal 86).

If automatic self-test is selected and the oscillator fails, with the result that the SI signal cannot be automatically generated, it is necessary for the system operator to be aware that the system is not being tested. Accordingly the output of oscillator 67 is applied to a 'missing pulse detector' formed by timer 73, which signals oscillator failure by causing a transistor 74 to deliver current via terminal 75 which is connected to the facilities circuit (Fig. 3). Thus current turns on transistor 76, thereby turning off transistor 77 and de-energising coil 78 and opening contacts 79.

This illuminates a fault lamp (not shown). In addition the missing pulse detector 73 sets a latch formed by gates 80, 81 and 82 which turns on transistor 83. This delivers current via fault sounder terminal 84 which is connected to the facilities circuit (Fig. 3). The fault sounder can be silenced without extinguishing the fault lamp, by pressing the accept button which applies the ACPT signal to terminal 85 (Fig. 4). This is inverted and applied to gate 82, resetting the latch of which that gate forms a part and turning off transistor 83.

Assuming that the inhibit signal SI has appeared at the output 58 of latch 59, this signal is inverted and thus the SI signal appears at terminal 86. Looking at the left hand bottom corner of Fig. 4, the gT signal is then applied to a ten second timer 87. The S7 signal should normally be present for about four seconds. If however the Si signal is maintained, this means that the entire system is inhibited and therefore out of action. This condition must be detected, and accordingly if the Si signal is maintained for ten seconds the timer 87 applies a 'catastrophy' output to transistor 88 which energises appropriate warning devices connect to terminal 89.

The SI signal from latch 59 is also applied to a timer 90 via a gate 91 and a 10 mS delay circuit formed by capacitor 92 and resistor 93. A clear to test signal CTT is applied to terminal 94 from the relay circuit (Fig. 2) and the gate 91 prevents the SI signal reaching timer 90 unless the OTT signal is present to indicate that the response outputs of the system have been inhibited. As described below, this ensures that the relays cannot respond to a self-test by for example releasing extinguishant as a result of a prior failure to inhibit.

If the CU signal is present the timer 90 is set and as a result a self-test signal ST appears at terminal 95, the signal ST appearing at terminal 96. The Signal is also applied to a latch 97 which receives the ALARM signal from terminal 63. The output of the latch 97 is a reset signal SR which is not used in the presently described system but is made available as in some systems it is useful. Furthermore, the ST signal sets a latch 98 which can only be reset if every part of the system passes the test sequence, these circumstances resulting in the signal STF being applied to terminal 99. The output of the latch 98 is passed by a gate 100 if and only if the system inhibit signal Si is absent, and thereby avoiding annunciation until the end of a self-test sequence.

If at the end of a sequence the latch 98 has not been reset, Si disappears and transistors 101 and 102 are turned on to illuminate a self-test failed lamp (not shown) connected to terminal 103 and to energise a self-test failed sounder (not shown) connected to terminal 1 04. The sounder can be silenced by pressing the accept button to reset a latch formed by gates 105, 106. Thus the system is fail-safe as the latch 98 causes a fault annunciation unless there is a positive indication that all the test sequence has been carried out successfully.

Referring now to Fig. 5, the auxiliary facilities circuit will be described. The =, ST, and ST signals are received on inputs 86, 95 and 96 respectively from the self-test control circuit (Fig. 4).

'Thewsignal is applied to an open collector driver 107 which provides an U1 signal to terminal 108 which is connected to the alarm response testing circuit (Fig. 6) The output of driver 107 is also applied to the base of a transistor 109 which is turned off during self inhibit.

Transistor 109 is connected via terminal 110 to the facilities circuit (Fig. 3) and when turned off de-energises relay coils 28 and 45. The common alarm and alarm sounder outputs provided by contacts 29 and 46 are thus inhibited.The output of driver 107 is also applied to transistor 111 which also goes off during self inhibit. The transistor 111 is connected between terminals 112 and 11 3 which are connected to the facilities circuit (Fig. 3). When transistor 111 is off, the output of transistor 114 driven by a clock oscillator 11 5 is inhibited, preventing signals at terminal 11 6 from turning on and off the various LED devices in the system during self-test. The purpose of the signal at terminal 11 6 will be described hereafter.

The SI signal is also applied to a gate 117 which receives the output of a timer circuit 118.

The timer 118 receives the output of a gate 11 9 which is connected to the ST input terminal 95 via gate 120 and to the ST input 96 via gate 121 and inverter buffer 122. The duration of the SI signal should be greater than that of the ST signal. If this were not so, it could happen that a test sequence was still in progress after the disappearance of the inhibit signal SI and that the test sequence itself would initiate system response. To prevent this happening, the timer circuit 118 sets an upper limit of three seconds on the duration of the ST signal which should have a duration of only two seconds. The timer is reset by the disappearance of the ST signal which normally occurs within its three second limit.If however the ST signal is maintained for three seconds, the timer output prevents the gate 11 7 from turning on transistor 123. The gate 11 7 also prevents the turning on of transistor 123 in the absence of the self inhibit signal SI. Thus the circuit checks that the SI signal is present, checks that the ST signal is not maintained too long, and only then turns on transistor 123.

The transistor 123 provides the FST signal via terminal 124 to the alarm response testing circuit (Fig. 6). If transistor 123 was to short circuit, thus simulating a permanent system test condition, the inhibit signal SI would disappear and the system would respond to the simulated alarms with potentially catastrophic results. To prevent this happening, if transistor 123 goes short circuit, inhibition is maintained by feeding the FST signal back to terminal 86 via terminals 125, 126. The connection between terminals 125, 126 is omitted to avoid complicating the drawings.

The FST signal at the output of gate 11 7 is also applied to a 0.5 second timer 127. When the FST signal disappears a half second accept and reset pulse is applied by open collector driver circuit 128 to transistor 129. Transistor 129 applies an accept signal to terminal 130 and a reset signal to terminal 1 31. Terminal 1 30 is connected to accept terminal 48 (Figs. 1 and 3). Terminal 131 is connected to a reset terminal of an interface circuit (not shown). This interface circuit monitors field transducers for fault and alarm conditions.

Registering alarm, it latches in the signal until such time as the alarm is removed and the circuit reset. The interface circuit indicates faults by detecting an open circuit line to the transducers.

Thus, when the FST signal disappears, all the self-test induced alarm conditions are reset so that when the SI signal disappears the system is in its normal condition. During a test, the FST signal is applied via resistor 132 to LED 133 which accordingly annunciates 'test in progress'.

The FST signal is also applied to flip-flop 134 and causes a 'test failed' signal STF to be applied to gate 135. The gate 135 receives the Si signal and provides an STF output only when the SI signal is absent. At the end of a test, the SFT signal is therefore applied to an LED 1 36 to annunciate 'test failed' unless before the SI signal disappears the flip-flop 134 is reset by the appearance of a 'test passed' signal STP at terminal 137. The terminal is connected to the relay circuit as described below. Assuming that the STP signal does appear, it is applied to open collector driver 1 38 which applies the signal STP to terminal 99. Terminal 99 is connected to the seif-test control circuit (Fig. 4) and the STP signal is effective to reset latch 98 as described above.

The ALARM signal appearing at terminal 63 (Fig. 4) is routed via the auxiliary facilities circuit (Fig. 5) to which terminal 63 is connected. The ALARM signal is derived from another open collector driver 1 39 controlled from common alarm and common fault lamp terminals 25 and 75 connected to the facilities circuit of Fig. 3.

Terminals 25 and 75 carry signals identifying any fault other than those which can only be detected by the self-test system.

Referring now to Fig. 6, inputs 10 to 17 are connected to the like-numbered terminals of Fig. 1 and thus receive signals indicative of the state of the detectors connected to the system. As only five detectors are provided, inputs 1 5, 1 6 and 1 7 are not used. To allow for this incomplete usage, exclusive-OR gates such as gate 139 are used in conjunction with DIL switches such as 140. The output of gate 139 is produced only if input 10 is high and switch 140 closed, or input 10 is not produced and switch 140 open. Thus an output is produced by gate 39 only if input 10 is in the state anticipated by the setting of switch 140.The output of gate 1 39 is passed with others to NAND gate 143 which produces an output STP during self-test via an inverter only if all inputs 10 to 17 are in the state anticipated by the programming of the DIL switches. The output of gate 143 is passed to AND gate 144. The gate also receives the '1 up' signal via terminal 145 from the voting circuit (Fig. 1), the 'V1' signal via terminal 146 from the voting circuit (Fig. 1), and the self-est signal ST via terminal 124 from the auxiliary facilities circuit (Fig. 5). Assuming all these four signals are all present, the gate 144 applies a self-test passed signal STP to normally high impedance open collector driver 147 which applies the STP signal via terminal 137 to the auxiliary facilities circuit (Fig. 5).

The self-test signal ST is used to set a flip-flop 1 48 to provide an output which if gated to open collector driver 1 50 causes a signal to be applied via terminal 151 to illuminate fault LED 152 (Fig.

1). The gate 1 49 is prevented from enabling illumination of the LED 1 52 during a self-test sequence by the Si signal which it receives via terminal 108 from the auxiliary facilities card (Fig.

5).

When the V1 signal appears at terminal 146 (Fig. 6), gate 153, if it is not inhibited by the Sl signal it receives via terminal 108, supplies a VIX output to gate 1 54, and the reset terminal of flipflop 1 55, and gate 1 56. The gate 154 sets flip fiop 1 55 which causes the clock signal derived via terminal 116 from the facilities card (Fig. 3) to be gated to transistor 157, causing a "mimic voted" lamp (not shown) to flash on and off.If the 'accept button' 47 (Fig. 3) is pressed, the ACPT signal is applied via terminal 1 58 from terminal 48 (Fig. 5) to gate 1 54. This resets flip-flop 1 55 which stops the clock signal. The transistor 1 57 is then held on continuously. If the V1 signal disappears, transistor 1 57 turns off. An LED 1 59 (Fig. 1) connected to terminal 1 60 annunciates the condition of transistor 1 57.

It is important to note that the So signal prevents the LEDs flashing during self-test.

The gating circuit indicated generally by numeral 161 operates in an analgous manner to circuits 153, 154, 155 and 156 to turn on transistor 1 62 and thereby energise a lamp in response to receipt of the '1 up' signal at terminal 145. An LED 1 63 (Fig. 1) connected to terminal 1 64 annunciates the condition of transistor 1 62.

Referring again to Fig. 2, self-testing of the relay circuit will be described. The self inhibit signal SI is applied to terminal 86 from the control circuit (Fig. 4) and energises relay 165, opening contacts 1 66. This makes it impossible for any of the relays 30, 32, 34, 36 and 38 to be energised and therefore inhibits all system responses taken via contacts 31,33, 35, 37 and 39, such as extinguishant release, to genuine or simulated alarms. The upper terminal of relay 166 is the source of the 'clear to test' signal CU which is applied via terminal 94 to the control circuit (Fig.

4). Thus, until contacts 1 66 open, the CU signal is not available and the self-test cannot proceed as the ST signal is inhibited as previously described.

It will be recalled that in the present example only relay 30 can be energised, the other relays 32, 34, 36 and 38 not being used. Therefore, during self-test only input 26 carries a voted executive output signal. As contacts 166 are open, the current through the relay 30 is not sufficient to switch contacts 31 but is sufficient to set data at the D input to flip-flop 167. The =;signal received via terminal 124 from the auxiliary facilities circuit (Fig. 5) is applied via a delay circuit 168 to the clock input of the flip-flop 1 67. If a simulated alarm condition is indicated by current through relay coil 30, the output of flip-flop 167 holds LED 1 69 off. If however there is no current through the relay coil 30, LED 169 comes on to annunciate a fault.

Relays 32, 34, 36 and 38 are associated with respective flip-flop and LED annunciation circuits entirely analogous to circuits 1 67 and LED 1 69.

As their inputs are not in use however, they cannot provide simulated alarm signals. To enable the full system to be tested despite this fact, programming switches 1 70 to 1 74 are provided which operate exactly as the eight DIL switches such as switch 1 40 in Fig. 6 as previously described.

The outputs of gates 1 75 to 179 are taken to a NAND gate 1 80 which also receives the St signal.

If and only if each gate 175 to 179 indicates inputs to relays 30, 32, 34, 36 and 38 as anticipated by the programming of DIL switches 1 70 to 174, and the ST signal is present, the gate 180 causes the 'self-test passed' signal STP to appear at terminal 137 which is connected to the auxiliary facilities circuit (Fig. 5).

Referring again to Fig. 3, failure of the oscillator 11 5 is detected by a missing pulse detector 181 which is effective to turn on transistor 182 and thereby illuminate LED 183. The anode of an SCR 1 84 then goes high and a fault output signal appears at terminal 84 (Figs. 3 and 4). When the accept button 47 is pressed, the SCR 1 83 turns on and the potential at the terminal 84 drops. This 'accepts' an alarm and turns off the alarm sounders.

An extensive system will of course take longer to test than a small system, and it is important that the self-testing circuitry should take account of this. In the described embodiment this is done by concluding a test only after the ALARM signal has returned to its normal state following the resetting of the input interface circuits (not shown).

As briefly described above, the input interface circuits continuously monitor the state of field transducers for alarm and fault conditions. The alarm condition is monitored by the module which latches into alarm mode and unlatches only after the alarm signal has been removed and accept and reset signals have been applied to the input module.

It will be appreciated that subsidiary testing circuits may be added to the described system. The system might also be expanded to include more than the above signal processing circuits all or some of which may be tested by the above described techniques. For example, an LED test button and associated circuitry could be provided in a conventional manner.

The described circuit provided numerous highly advantageous features. In particular, faults are annunciated during self-test if self inhibit signal SI is maintained for too long, if the self-test condition ST is maintained for too long, if the self-test condition is implemented in the absence of the SI signal, and also the self-test condition is never implemented without a positive indication that the system output controls have been disabled. In addition, the system can be programmed to accomodate a variety of detectors and output relay configurations simply by manipulation of built in switches. Thus a wide range of system requirements can be met and an installed system can easily be modified or expanded at will without disruption of the self-test sequence.

Claims (14)

1. A self-testing alarm system comprising means for inhibiting outputs of the system and testing means for simulating alarm conditions and monitoring the response of the system to the simulated alarm conditions, characterised in that the system comprises means for detecting inhibition of the system outputs of the inhibiting means, means for providing a system test output in response to detection of inhibition of the system outputs, means for enabling the testing means in response to the system test output, means for maintaining said inhibition whenever the system test output is provided, and means for annunciating failure to remove said inhibition after testing of the system.

2. A self-testing alarm system according to claim 1, characterised in that means are provided for ensuring that spurious test outputs which themselves result from faults also inhibit the systems output.

3. A self-testing alarm system according to claim 1 or 2, characterised in that means are provided to prevent the system assuming a test condition in the event of any alarms in the system being activated.

4. A self-testing alarm system according to any preceding claim, characterised in that the inhibiting means is operative to open contacts in series with the coils of system output relays in order to prevent system outputs during testing.

5. A self-testing system according to claim 4, characterised in that the potential generated across the open contacts serves as a 'clear to test' signal enabling generation of the system test output.

6. A self-testing alarm system according to any preceding claim, characterised in that the testing enabling means comprises a transistor driven by the system test output.

7. A self-testing alarm system according to claim 6 characterised in that a gate is provided which prevents the transistor from responding to the system test output in the absence of system inhibition.

8. A self-testing alarm system according to any preceding claim, characterised in that the means for maintaining the inhibition of the system whenever the system test output is provided is a feedback loop returning the system test output as a substitute system inhibition signal.

9. A self-testing alarm system according to claim 8, when dependent upon claim 6, characterised in that the feedback loop is provided by returning the output of the transistor driven by the system test output to the inhibition means.

10. A self-testing alarm system according to any preceding claim, characterised in that the means for annunciating failure to remove system inhibition comprises a device for detecting when the system has been inhibited for a predetermined period and for annunciating system failure thereafter.

11. A self-testing alarm system according to any preceding claim, characterised in that the inhibition detecting means prevents the system assuming its test condition until inhibition of the system has been positively identified, that the inhibition maintaining means prevents the system outputs from being enabled during a test even if the inhibition means proper fails, and that the failure annunciating means warns that the system has been rendered inoperative in permanent test mode.

12. A self-testing alarm system according to any preceding claim, characterised in that input and output components of the system are programmable so that unused inputs and outputs can respond positively to testing.

13. A self-testing alarm system according to claim 12, characterised in that the systrem component inputs are provided by manual switches which can be operated to provide inputs programmed to indicate that signals are or are not expected to be received during a self-test sequence.

14. A self-testing alarm system substantially as hereinbefore described with reference to the accompanying drawings.