GB2054198A - Optical scanner - Google Patents

Abstract

An optical scanning head produces a sine wave. The impulse created by the head crossing a pattern is used to sample the sine wave to produce one of the coordinate functions and, rather than producing a similar cosine wave, an impulse delayed 90 DEG is used to sample the sine wave to produce the desired remaining coordinate signal. These two signals are then used to control the X and y coordinate drive motors of the system, eg an cocyger cutting torch. The sine wave is also utilized to produce signals which permit manual positioning of the apparatus. The sine wave signal is used to produce sampling pulses at the time of occurrence of the peak and zero values of the sine wave which are used to sample the sine wave and produce manual steering signals dependent on the maximum amplitude of the sine wave from the speed control. <IMAGE>

Description

SPECIFICATION Optical pattern tracer This invention relates to optical pattern tracers and in particular optical pattern tracers utilizing a circular scanning mode and coordinate drive mechanisms.

In the past, optical pattern tracers have been evolved which utilize a mechanical means of producing a circular scan for viewing the pattern by means of a photocell. A typical example of such a prior device is Canadian Patent 917,773 issued December 26, 1972 and assigned to the assignee of the present application. As described in that patent, the scanning system includes a motor which rotates a mirror causing the photocell to view a spot which rotates over the pattern. At the same time, the motor rotates a generator which produces sine and cosine functions. By relating the information derived from the photocell and the sine and cosine functions generated by the scanner signals can be produced which represent the relative velocity in coordinate directions which will be required to cause the pattern tracer to follow the pattern.These signals have been utilized to drive coordinate drive motors moving the pattern tracer and associated tool in accordance with the pattern.

It will be noted in the previous system, both sine and cosine functions were required.

It is an object of this invention to simplify the design of such a tracing system and in particular to eliminate one of the function generators and at the same time produce a system based largely on standard integrated circuit components, thus simplifying the construction and economizing the design.

In accordance with the invention, the optical scanning head produces a single function which will be referred to as a sine wave. A speed control selects from a potentiometer a certain percentage of this sine wave. The impulse created by the scanning device is used to sample the sine wave to produce one of the coordinate functions and rather than producing a similar cosine wave, a delayed impulse, effectively delayed 90 , is used to sample the sine wave to produce the desired remaining co-ordinate signal. These two signals are then used to control the X and Y coordinate drive motors of the system. This arrangement is satisfactory for a single direction of tracing, either clockwise or counterclockwise around the pattern depending upon which coordinate signal is generated from the delayed pulse.

At the same time, the sine wave function is also utilized to produce signals which permit manual positioning of the apparatus. The sine wave signal is used to produce sampling pulses at the time of occurrence of the peak and zero values of the sine wave which are used to sample the sine wave and produce manual steering signals dependent on the maximum amplitude of the sine wave from the speed control.

A clearer understanding of our invention may be had from a consideration of the following description and drawing of a specific embodiment in which: Figure 1 is a block diagram of the system; Figures 2A and 2B together provide a more detailed circuit diagram; and Figure 3, on the same sheet as Fig. 1, is a series of waveforms useful in explaining the operation of the circuit.

Considering first Fig. 1, there is shown a circular scanning optical scanner 6 which views a pattern 7 by causing a photoelectric device to observe the reflective quality of the pattern in a circular manner as designated at 8. The method of producing the optical scan may be any suitable scanner such as that disclosed in the foregoing Canadian Patent.

The photoelectric scanner thereby produces a pulse on terminal 9 each time the photooptical device detects the pattern. At the same time, the scanner produces a sinusoidal output applied to speed control 10. From the pulses at terminal 9 is selected only those which represent the crossing of the pattern in the direction in which the tracer is traveling by means of selector circuit 11. The selected pulses are also shaped in the same circuit.

The output from the selector shaper 11 is applied to delay circuit 12 and to the sample and hold circuit 13. The output from the delay circuit 12 is applied to sample and hold circuit 14. The output from speed control 10 being a sinusoid of amplitude determined by the speed setting is applied to both sample and hold circuits 13 and 14 and also to signal processor 15. The output from the sample and hold circuits 13 and 14 are applied to the X and Y amplifiers 16 and 17 respectively.

The output from these amplifiers is used to control the X and Y velocity of the tracer 6 and also the tool which may be directly connected or connected through corresponding motor drives to cause the tool to perform the same convolutions as the tracer in a well known manner.

The circuit thus far is a block diagram of the pattern tracing portion. However, in operation it is necessary to move the tracer over the surface to pick up the pattern or to make straight cuts. In order to do this, the operator must have overriding control. This is provided by switch 18 which is a four position switch permitting the operator to drive the system in the X or - X direction in the Y or - Y direction selectively. The outputs from this switch 18 are applied to the X and Y generators 19 and 20 respectively and the outputs from the X and Y generators, which are only operative when the switch 21 is actuated, are applied to sample and hold circuits 13 and 14.When the scanner is producing an output at terminal 9 and the apparatus is energized for tracing, the sample and hold circuits sample the sinusoid from speed control 10 in accordance with the pulse provided by the selectors, shaper 11 in sample and hold circuit 13 and in accordance with the delayed pulse from delay circuit 12 in sample and hold circuit 14. The delay provided by delay 12 is equal to a 90 rotation of the scanning apparatus. Therefore the information derived from the sample and hold circuit 14 represents a 90 delay from the information derived in sample and hold circuit 13.Therefore, the outputs from sample and hold circuits 13 and 14 respectively are the two coordinate pieces of information, for example, the value of a sinusoid at the time of the interception of the pattern and the value of an equivalent cosine signal. These therefore provide the necessary X and Y coordinate information to move the tracing apparatus.

To permit operator control, the sine wave applied to processor 15 and to X and Y generators 19 and 20 produces impulses at the zero and maximum negative and positive value of the sine wave. Depending on the position of switch 18, a pulse will be derived from the X generator or the Y generator and occurring at positive or negative or zero value of the sine wave which when applied to sample and hold circuit 13 or the sample and hold circuit 14 causes the apparatus to move in either a positive or negative direction, in either the X or Y coordinate direction with a velocity determined by the speed control setting. When the pulses derived from both the Y generator and the X generator occur at the zero value of the sine wave the machine stops.

Considering now Figs. 2A and 2B, there is shown a detailed circuit of the various components more generally described in Fig. 1. In particular, it will be seen that the scanner is now represented as a photocell 30 and a sine wave generator 31. The shape and value of the pulse from the photocell is adjusted by the amplifiers 32 and 34, so that when the edge of pattern is encountered the output of amplifier 34 goes from logic zero to logic 1. This pulse is applied to NAND gate 35 whose output is applied in turn to monostable 37.

OR gate 36 and monostable 37 are so arranged that when a pulse is received on NAND gate 35 the monostable 37 disables the NAND gate inhibits any further pulse being passed through for a period of time only slightly less than a complete scanning period. This circuit ensures that, having once established the direction of travel of the machine, only pulses in the same direction will be detected and the reverse pulse will be disregarded. Pulses from monostable 37 are then applied to three circuits, the first, the onpattern generator consisting of monostable 39, which has a pulse duration slightly longer than a single scan period and thus produces a logic 1 signal on terminal 40 as long as the pattern is being detected. This signal in turn energizes 41 the on-pattern indicator LED.

The second circuit to which the output from monostable 37 is applied is shaper monostable 47. The pulse from monostable 37 is also applied to monostable 43 which produces a pulse at its output a time after being pulsed equal to 90 of scan rotation which will be about 8.3 milliseconds at 1800 RPM. The output from this monostable is applied to a shaper which consists of monostable 45 which correspond to monostable 47 in the other channel, the output from both monostables being applied to the AND gates 48 and 49 respectively. The outputs from the AND gates 48 and 49 are applied to NOR gates 86 and 87 and thence through NAND gates 50 and 51 and inverter amplifiers 52, 53 and 54, 55 to the sample and hold circuits 56 and 57 respectively.

The output from the sine wave generator 31 is inverted and stabilized by amplifier 58 so that it has constant amplitude. A certain portion of this sine wave is selectively derived by speed control potentiometer 59 and applied to sample and hold circuits 56 and 57.

These circuits produce a signal proportional to the value of the sinusoid at the instant it is sampled by the sampling pulse applied to sample and hold circuits. This signal is then applied to the X and Y amplifiers 16 and 17 and thence to the X and Y coordinate drive motors 60 and 61.

On the left hand side of the drawing will be seen switches S1 and S2. In the foregoing description, it has been assumed that S2 is in the position shown. If on the other hand, it is desired to operate the tracer in a manual mode, S2 is moved to strip and the manual switch S1 is moved to the desired X, - X, Y or - Y position.

A sine wave from amplifier 58 is also applied to both inverter amplifier 62 and comparator 63. The output from amplifier 62 is applied to phase shifter 64 and the output from phase shifter 64 applied to comparator 65, the output from comparator 65 is applied to inverter 66.

Waveforms at various points in the circuit are as shown in Fig. 3. With S1 in the + X position, the + X terminal of the switch is at zero volts, the remaining terminals are at + 12 volts. The terminals + X and - X of S1 are connected to NOR circuit 67. Terminals + Y and - Y of S1 are connected to NOR circuit 68. The terminals are also connected through inverters 69, 70, 71 and 72 respectively to NAND circuits 73, 74, 76 and 77. The square wave output from inverter 66 is applied to NAND gates 73 and 76. The square wave output from shaper 65 is applied to NAND gates 74 and 77. The square wave output from comparator 63 is applied to NAND gates 75 and 78 and also to NAND gate 79. The output from NAND gates 73, 74, 75 and 79 is applied to NOR gate 80.

The output from NAND gates 76, 77, 78 and 79 is applied to NOR gate 81. The outputs from NOR gates 80 and 81 are applied to shaper monostables designated 82 and 83 respectively. The outputs from these monostables are applied to AND gates 84 and 85 which correspond to AND gates 48 and 49 in the trace circuit, all of which are applied to NOR gates 86 and 87. From here on the circuit corresponds to that described in respect to the tracing operation and the X and Y coordinate signals are determined by the position of the manual switch which in turn determines the time of sampling of the sine wave provided from the speed control at the sample and hold circuits and whether the signal is in the X or Y channel. In addition, the control of the X and Y drive logic is provided to ensure the exclusive control of the system by the operator or by the pattern.

For example, with S2 in the START or STRIP position, one input to NAND 93 is a zero causing a logic 1 output which is inverted to a zero by inverter 94. This logic zero applied to NAND 79 disables the other input to NAND 79 which therefore may be disregarded. At the same time, with S2 in the STRIP position, one input to NOR 96 is a zero causing a 1 output regardless of its other input. This logic 1 applied to NAND gates 73 to 78 enables these gates permitting the manual position switch S1 to control the production of the desired sample pulse.

If on the other hand, S2 is in the START position, the zero from S2 is inverted by inverter 90 and applied to NAND 95 as a logic 1. The output from the STRIP terminal of S2 is also a logic 1 applied to NAND 95.

The Q output from monostable 39 is a logic 1 in the absence of detected pattern. With all inputs logic 1 to NAND 95 the output is a logic zero to NOR 96. Even though the other input to NOR 96 from S2 is a logic 1, the output from NOR 96 is a logic 1 enabling NAND's 73-78. Also, with S2 in the START position the input to NAND 88 and NOR 89 from the STRIP contact of S2 is logic 1. The logic zero on the START contact is inverted by inverter 90 and appears as a logic 1 at the input to NAND 88. Until the pattern is acquired, Q at terminal 40 is a logic zero which is applied to NAND's 88 and 89. The outputs of NAND 88 and NOR 89 are therefore both logic 1 which when applied to NOR 91 cause a logic zero output.This logic zero inverted by inverter 92 to logic 1 when applied to AND gates 84 and 85 enables these gates and permits pulses from monostables 82 and 83 to be applied to NOR gates 86 and 87 and thence to the sample and hold circuits and the motor control as previously explained.

The logic zero from NOR 91 is also applied to AND gates 48 and 49 disabling these gates and preventing pulses appearing at their other terminals from being transmitted to the sample and hold circuit.

Thus, with S2 in the START position to acquire a pattern the tracer moves in a direction determined by the position of switch S1 at a velocity determined by the amplitude of the sine wave derived from the speed potentiometer 59 until a pattern is detected.

As soon as a pattern is detected, Q becomes a logic zero, both inputs to NOR 96 are logic 1. Its output becomes a logic zero and NAND gates 73 to 78 are disabled preventing continued manual control once a pattern has been acquired.

Q at terminal 40 becomes a logic 1. With all inputs to NAND 88 logic 1 its output becomes logic zero. This logic zero applied to NOR 91 causes its output to become logic 1.

This output is tied back to the input of NOR 89 causing its output to become logic zero so that when S2 is moved from START to TRACE the output from NOR 89 remains a logic zero and the output from NOR 91 remains logic 1 even though the output from NAND 88 becomes logic 1.

This logic 1 from NOR 91 enables AND gates 48 and 49 permitting pulses from monostables 45 and 47 to be applied to NOR gates 86 and 87 and thus to the sample and hold circuit. At the same time the logic 1 from NOR 91 is inverted by inverter 92 and applied to AND gates 84 and 85 disabling them and preventing signals from the manual positioning circuit from entering the sample and hold circuit.

With S2 in the TRACE position the STRIP and START terminals both apply logic 1 signals to NAND 93. If the tracer is tracing a pattern the 0 output of monostable 39 is a logic zero, thus maintaining the output of NAND 93 logic 1 which when inverted by inverter 94 provides a logic zero to NAND 79.

Should the pattern be lost or S2 be turned to TRACE when the pattern has not been acquired, the 0 output of monostable 39 becomes logic 1. This together with the other logic 1 inputs to NAND 93 causes the output to become logic zero which inverted by inverter 94 applies a logic 1 to NAND 79, ena bling this gate and permitting the signal on its input to be applied through OR gates 80, 81 to monostables 82, 83. This input to NAND 79 is the waveform shown at G in Fig. 3.

At the same time the inputs to NAND 95 from the STRIP terminal of S2 and Q from monostable 39 are both logic 1. The input to NAND 95 from the START terminal of S2 through inverter 90 is logic zero. The output of NAND 95 is therefore logic 1. The other input to NOR 96 is logic 1 from the STRIP terminal of S2. With both inputs logic 1 the output of NOR 96 is logic zero. This logic zero disables NANDs 73 to 78 and prevents sig nals from S1 from controlling the tracer.

Considering now Fig. 3, we may now describe the operation of the system. The waveform shown at A in Fig. 3 occurs at point (E) on Fig. 2. Its inverted stabilized form as shown at B in Fig. 3 appears at point in Fig.

2. The inverted form of a form B shown at C in Fig. 3 appears at Gcin Fig. 2. The phase shifted form of the sine wave now a cosine wave as shown at D in Fig. 3 appears at point Qin Fig. 2. This waveform clipped by comparator 65 produces the square wave shown at E in Fig. 3 with the wave fronts occurring at the transition points of sine wave D in Fig. 3 and occurs at ;tin Fig. 2. The inverted form of this waveform appears at '3in Fig. 2 as shown at F in Fig. 3. A similar waveform 90 displaced is produced in a comparator 63 as shown at G in Fig. 3 and appears at 0Gin Fig. 2.

With S2 in the STRIP position, NAND gates 73 to 78 are enabled as described previously, NAND gate 79 is disabled as are AND gates 48 and 49. The only signal applicable therefore is that from S1. Let us assume that S1 is in the + X position which applies a logic zero to inverter 69 which appears as a logic 1 at NAND gate 73. The remaining gates 74 and 77 are disabled because their inputs from S1 through the inverters are all logic zero. The other signal applied to NAND gate 73 is waveform F. It will be seen that this provides a zero to one transition at the maximum of sine wave B. This 1 transmitted through NOR 80 to monostable 82 produces a sampling pulse which is applied to AND 84 which it will be noted is enabled, because the output from NOR 91 is zero which inverted by inverter 92 enables AND gate 84.This pulse through NOR gate 86 and AND gate 50 is applied to the sample and hold circuit 56 and causes the sine wave B to be sampled at its maximum amplitude point. In fact, the sampling circuit of course only samples that portion of sine wave B which is derived from the speed control and therefore the signal provided by the sample and hold circuit to the motor 60 is determined by the setting of the speed control.

The zero input to NOR 67 from the + X terminal on S1 causes the output of this NOR to be a logic 1 which is applied to NAND gate 78. The other signal applied to NAND gate 78 is waveform G which it will be noted provides a logic zero to logic one transition at the zero crossover point of waveform B. This zero to 1 transition from NAND gate 78 when applied through NOR gate 81 to monostable 83 produces a sample pulse which is applied through AND gate 85 at OR gate 87 and AND gate 51 to the Y channel sample and hold circuit 57 which samples the sine wave B of an amplitude determined by the speed control. Since the sample is at the zero transition point, the output from the sameple and hold is zero volts to the Y amplifier 17 causing zero speed from motor 61.The total result therefore of the selection of STRIP on S2 and the positioning of S1 in the + X position is a movement of motor 60 only with a speed determined by the speed control and thus a movement in the X direction only.

In a similar manner, positioning of S1 in the - X, + Y or - Y positions causes samples of sine wave B at its maximum or zero crossover value to be selected by the sample and hold circuits and applied to the output amplifiers.

If, on the other hand, because of the logic previously described, a logic zero appears at Go in Fig. 2 this disables NAND gates 73 to 78.

If at the same time, a logic 1 appears at N in Fig. 2, NAND gate 79 is enabled. The other input to NAND gate 79 is waveform G and as previously indicated, transition of waveform G from zero to 1 occurs at the zero voltage crossover of waveform B. This transition from zero to 1 of waveform G causes both monostables 82 and 83 to generate sampling pulses which are applied through AND circuits 84 and 85, NOR circuits 86 and 87, NAND circuits 50 and 51 to the sample and hold circuits 56 57. Since both these samples occurs at the zero crossover point, zero voltage is applied to the motor control circuits 16 and 17 and motor 60 and 61 go to zero speed.

Switch S3 is used to control the operation of the oxygen solenoid when the tracing apparatus is associated with an oxygen cutting torch. The solenoid, not shown, is connected to the terminals of optical coupler 99 which in turn is controlled by FET 98 so that when a positive potential is applied to the gate of the FET 98 the oxygen is turned on.

It will be seen that with S3 in the OFF position, no potential is applied from the switch to the FET 98 and the oxygen will not be switched on. With S3 in the manual position 12V will be applied through the MAN terminal of S3 to the diode 100 and to the gate of FET 98 causing the oxygen to be switched on.

With S3 in the automatic position and S2 in the START position the zero volts from the START terminal of S2 is applied to the input of inverter 90 and appears as + 12 volts at its output which is applied through the diode 101 to the gate of FET 98 causing the oxygen to be switched on. If the pattern is acquired and S2 turned to TRACE, point at NOR 91 has become a 1 and applies 12 volts to the AUTO terminal of S3 which is applied through the diode 100 to the gate of FET 98.

With S2 in the TRACE position, the input to inverter 90 is + 12V which cause a zero output. This zero however is blocked by the diode 101 and does not appear at the gate of FET 98 which continues to hold the oxygen on. If, however, the pattern is lost, the output at becomes a zero. With only zero volts applied to the gate of FET 98 the oxygen is cut off.

It will therefore be evident from the foregoing that a logic system has been provided which ensures that the system may operate in the STRIP, TRACE or START mode and will automatically stop and cut off oxygen if the pattern is lost or not properly acquired.

While the system has been described with particular logic modules, it will be understood that the components can be replaced by equivalent circuitry of any desired form which performs a similar logic and utilizes the signals in a similar manner.

Claims (7)

1. An optical pattern tracer including a photoelectric pattern detector, scanning means to cause said detector to scan the pattern around a circular path centered on the steering axis of said tracer, means to produce from said pattern detector a first pulse indicative of the intersection of the scan and the pattern means synchronized with said scanning means to produce a sinusoidal voltage representative of the rotational position of said detector as it scans around said circular path, means to produce a second pulse time delayed after said first pulse an amount equal to the time required for said detector to proceed ninety degrees around said circular path, means to utilize said first and second pulses to sample said sinusoid and thereby produce voltages representative of the coordinate voltages required to move said tracer around said pattern.

2. An optical pattern tracer wherein the tangential velocity of said axis of said tracer with reference to said pattern is determined by controlling the amplitude of said sinusoid.

3. An optical pattern tracer as claimed in claim 1 wherein said sinusoid is used additionally to produce first control pulses coincident in time with the zero crossing of said' sinusoid and second control pulses coincident with the positive and negative maximum excursion of said sinusoid.

4. An optical pattern tracer as claimed in claim 3 wherein said first pulse is replaced by one of said first or second control pulses and said second pulse is replaced one of the other of said control pulses.

5. An optical pattern tracer as claimed in claim 4 including mutually exclusive switching means to ensure substitution of control pulses for said first and second pulses and prevent simultaneous utilization of first and second pulses with said control pulses.

6. An optical pattern tracer as claimed in claim 1 including logic means to stop the tracer in the absence of a detected pattern.

7. An optical pattern tracer as claimed in claim 1 or 6 including logic means to disable a cutting means when said tracer is stopped.