GB2053536A - Computer Terminal - Google Patents

Abstract

A low-cost computer terminal comprises a microprocessor 14 which monitors a modem 10 and a parallel port 11 for communicating with other data processing means, and a data entry and control keyboard 12. The microprocessor program is stored in EROM 18, and incoming data for display is stored in RAM 25. Display is by a standard T.V. set. Horizontal scan counter 22 and vertical scan counter 26 control the scan, suitable count ranges being decoded to give horizontal and vertical sync signals and left and right margins. The counters 22 and 26 also read out the characters from RAM 25 for display; the output characters are converted into visual form by ROM 33 (for alphanumeric characters) and PROM 34 (for graphics option). Each character is displayed as a 9 x 16 dot matrix; the matrix is divided into 2 x 3 areas for the graphics option. <IMAGE>

Description

SPECIFICATION Computer Terminal The invention relates generally to the field of digital computer peripherals and more particularly to the field of programmable computer terminals. Prior art terminals utilized expensive cathode ray tubes and special interface chips such as USARTS to accomplish the task of communicating with and displaying information from the main computer. The cheapest terminals available in 1979 were around 500 Dollars and not powerful or flexible as the disclosed terminal.

The hardware disclosed herein is capable of reading and writing on a serial communication line at adjustable speeds up to 600 baud utilizing a modem. It can read a keyboard and read and write from a parallel port. All entering data from any input may be displayed on a black and white television set and all data being displayed may simultaneously be transmitted out the serial or parallel ports. Upper and lower case and page and scroll mode are available and any combination of inputs and outputs can be set from the keyboard.

Field reversal is also available. Carriage return, line feed, clear screen, home up and cursor positioning are also available. Finally, a limited graphics capability exists by virtue of a PROM that may be programmed with any graphics patterns desired by an individual user.

The numerous functions and flexibility provided in the disclosed apparatus is due to use of a programmed microprocessor. The low cost is attributed primarily to use of a standard home television set in conjunction with a microprocessor programmed to perform many of the functions formerly performed by separate chips.

The prior art is crowded with computer terminal apparatus. However, the least expensive computer terminal available at the time of filing sold for more than twice as much as the disclosed computer terminal could be built for in kit form.

Further, no terminal in the prior art had as many options and capabilities and yet had as low a cost as the disclosed terminal.

Accordingly, the present invention provides a computer terminal comprising: a keyboard which allows the entry of data and control by an operator; interface means which interface with another data processing device so that data may be sent to and received from that other device; a memory for storing data; display means; and control means which monitors the keyboard and the interface means, and in response to control signals, sends data from the memory via the interface means, stores data in the memory from the interface means, and displays data stored in the memory on the display means.

A system embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of the system; Figure 2 is a diagram of the video generator and associated circuitry; Figure 3 is a diagram of the microprocessor and modem; and Figure 4 is a diagram of the parallel port.

Turning now to Figure 1, data to be displayed enters the terminal either through modem 10, parallel port 11 or keyboard 12. Data from keyboard 12 or parallel port 11 goes to microprocessor 14 over data bus 13. Modem 10 handles serial input and output for microprocessor 14 by linking it to another device through the telephone lines or some other communications network. Erasable Read Only Memory (EROM) 18 holds the series of preprogrammed instructions that microprocessor 14 executes in controlling the functions of the terminal. The program can be changed to suit individual user needs. The particular algorithm preferred consists of a main program loop that is interrupt driven by a vertical address counter 26 via flip-flop 1 69. The main loop controls the vertical sync and blanking by counting interrupts.

The interrupt function also provides the timer base for scanning of the keyboard, parallel port flags and modem. At different intervals, the main loop will branch to other sub-routines which handle the serial input function, the serial output function, the keyboard scan, and the parallel port input flag scan. As each character is received, the program must determine what is to be done.

Regular characters for display will be stored in the RAM while control characters each cause a separate function such as the graphics option, field reversal, and peripheral attachment of modem, screen and parallel port.

All timing for generation of the video display is developed from a clock 19. The oscillator output SC is sent to character shift register 21 and graphics shift register 21 a where it is used to shift the character or graphics information dot line byte to video generator 23 one bit at a time. 64 characters are displayed on each horizontal scan line, each character comprising a dot matrix 9 dots wide and 16 lines of dots tall. There is room for 89 characters per line but the excess over 64 is used for margins on the left and right. Character shift register 21 or graphics shift register 21 a shift out horizontal row of the dot matrix for every character display time. The character display time is the time it takes to shift out 9 dots at a rate of one dot for every period of crystal oscillator 19. A dot time is the inverse of the clock frequency or 80 ns.

The character times are marked for microprocessor 14 and horizontal address counter 22 by divide by nine counter 20. This is done by generating the ADVH signal every ninth period of the clock. By counting the ADVH signals, microprocessor 14 knows when the end of each horizontal line is reached. By keeping track of the signal from flip-flop 169, the microprocessor knows when to turn on the vertical blanking signal via the Video Status Register 30 and the vertical sync signal via data bus 1 3.

Horizontal address counter 22 counts out 89 character spaces per line and serves to supply the horizontal address of the character to be accessed from RAM memory 25. It also serves to generate a horizontal sync signal marking the end of each horizontal line and a line active signal for horizontal blanking to create the left and right margins.

A vertical address counter 26 serves to keep track of which line is being displayed and, more specifically, which line of the 16 line tall dot matrix for each character is being traced. Each horizontal sync pulse advances vertical address counter 26 one count, indicating the trace has moved down one line. Flip-flop 169 is set and reset by the first bit of vertical address counter 26.

The T.V. picture uses interlaced scan such that 8 horizontal lines are traced out for each line of characters displayed in a first half frame and another 8 during the next half frame. The second half frame is traced in the interstices of the first half frame.

Microprocessor 14 can load the vertical address counter 26 with an initial vertical address count via data bus 13. In this manner, the microprocessor controls the display as page mode or scroll mode by designating the vertical address of the first line to be displayed in each frame. The microprocessor also develops a blank signal and a vertical sync signal by setting these bits in video status register 30 via data bus 13. The vertical address counter 26 could of course be used to generate the vertical sync and blanking information.

The vertical character address count from vertical address counter 26 is coupled to a portion of the horizontal and vertical address input of a 2 to 1 multiplexer 27. Horizontal address counter 22 also sends its count, the horizontal character address, to the remaining portion of the horizontal and vertical address input of multiplexer 27.

Multiplexer 27 serves to supply an address to RAM 25 from either the address bus 1 5 or the horizontal and vertical character addresses from counters 22 and 26. One of these two inputs is switched to the multiplexer output feeding the address input of the RAM. Switching is controlled by an lSW signal under the control of the address bus 1 5 of microprocessor 14.

Microprocessor 14 serves to fill the RAM with the characters to be displayed one line at a time via the data bus 13. It does this by writing the ASCII character data from data bus 13 to the memory locations specified to RAM by address bus 1 5. Address bus 1 5 is switched through multiplexer 27 to the address input of the RAM.

An SMEM signal controlled by microprocessor 14 controls whether ram 25 functions in the read or write mode. Microprocessor 14 simultaneously controls the address switching by multiplexer 27 via the ISW signal. Signals ISW and SMEM are formed by decoding the address appearing on address bus 1 5 and combining the decoded signals with control signals from the microprocessor 14. When microprocessor 14 is not loading RAM 25, ISW causes the address outputs from the horizontal and-vertical address counters to be switched through the multiplexer 27 to form an address to access the character data stored in RAM 25. This data is used for display and/or transmission out from the parallel port and/or modem, depending upon the wishes of the operator as indicated by the control characters entered from the keyboard.For applications where the data need not change, such as in educational applications, preprogrammed binary data may be placed in a ROM and substituted for RAM 25. This would eliminate the need for the keyboard, ports, multiplexer and microprocessor (if the counters were modified to supply vertical sync and blanking signals).

The character data output from the RAM is fed to both the character generator ROM 33 and the limited graphics PROM 34. These read only memories are programmed with groups of bytes representing the specific dot patterns of light and dark dots recognizable by a user as the ASCII set of alphanumeric characters or any of the 64 special graphics patterns capable of being displayed by the terminal. Graphics PROM 34 uses the low order 6 bits of the data from the RAM to display a 2x3 pattern in place of the ASCII character. This graphics capability can be visualized by dividing the 9 x 16 character dot matrix into 6 rectangular regions in 2 x3 matrix arrangement. One of the 6 low order bits used for graphics is assigned to each rectangle.If a particular bit is on, then its corresponding rectangle will be lit on the screen pattern by a dot pattem output from graphics shift register 22a which corresponds to lighting all the dots in the 9x 16 dot matrix within the particular rectangle to bit lit.

Both the character generator ROM 33 and the limited graphics PROM 34 output a dot line byte in parallel format in response to the character data presented at their respective inputs. The first 3 bits of the vertical address counter are used by these memories to determine which line of dots in the vertical dimension of the matrix to retrieve and present at the dot line output. This dot line byte is sent to the character shift register and graphics shift register in parallel format and is shifted out therefrom serially at the rate of one dot for every period of the clock.

By activating buffer 35 (by a control signal obtained by combining control signals from the microprocessor 14 with a decoded address on buffer 15), the output character data from the RAM can be directed out of parallel port 11 and to microprocessor 14 via data bus 13 for transmission by modem 10.

Video generator 23 combines the video information received from character generator ROM 33 or limited graphics PROM 34 with the horizontal and vertical sync signals and blanking signals to form the composite video output signal to the T.V. set. The output signal is approximately 2V for white information and 0.75V for black information, with sync information dipping to the OV level if negative going sync is used. (If positive sync is used, the order is reversed i.e. sync is +5V and white is about +0.75V.) The output from the video generator is fed into the video amplifier of the T.V. set used for display.

Figure 2 details the operation of the logic of video generator 23 and character generator ROM 33. To better understand it, a more detailed explanation of the T.V. picture is necessary. The raster of any T.V. picture is comprised of many parallel horizontal lines traced across the screen by an electron beam. The intensity of this beam is varied to cause small phosphor dots on to the screen to emit light of an intensity proportional to the intensity of the electron beam. As the beam sweeps across the screen a line of glowing dots of varying shades of black and white will be formed.

In a computer terminal application we are interested in displaying a few lines of characters on the screen. To do this each character must be broken down into a matrix of light and dark dots in a pattern recognizable by the user as the desired character. In the present system, the dot matrix is 9 dots wide and 1 6 lines of dots tall. 64 of these dots matrices or characters will be displayed on each line of characters put on the screen. A line of characters will require 1 6 horizontal lines, one for each line of dots in each character dot matrix.

The clock frequency is 12.6 MHz and has a period of one dot time or 80 ns giving a total character display time of 720 ns. The period of one line therefor is 64 Ms, comprised of 57 zbS for the sweep to go from left to right 7 us to return to the left side of the screen. The dot must be turned off for the retrace and to create blank left and right margins on either side of the displayed text.

This is the purpose of the line-active flip-flop 1 38.

In order to ensure that there is an adequate border at the left and right of the display, only 48 ,us of the 57,us sweep time is actually used for display of characters. Flip-flop 138 is controlled by decoder 1 39a fed from horizontal address counter 22, which is advanced once for every character display time by the ADVH signal. When a count of 64 is reached, flip-flop 138 is reset, thereby sending VOUT low and darkening the screen. When a count of 72 is reached, decoder 1 39a clears a sync flip-flop 140. The resulting low output signal grounds VOUT. Flip-flop 140 is set at the the count of 72. At the same count, Horizontal Address Counter 22 is preset to a -17 count by a feed-back line.Flip-flop 140 remains cleared, thereby blanking the scan. The horizontal address counter 22 then begins counting forward to 0. At a count of -11 flip-flop 14Q is set thereby ending the sync blank of the scan. When the count reaches 0, flip-flop 1 30 is set thereby enabling the display.

The T.V. picture is comprised of 262- parallel, horizontal lines traced at a rate of 30 frames per second. Interlaced scan is used. Thus a 30 frames per second tracing rate as used here means 60 half frames are traced every second with each half frame comprised of 262 2 lines. The next half frame 2626 lines are interlaced between the lines of the previous half frame. At 525 lines per frame and 30 full frames per second, the T.V. horizontal sweep frequency is 15,750 lines per second. The vertical sweep frequency is therefore 60 half frames per second.

The T.V.'s horizontal and vertical sweep oscillators must both be locked in sync with the character data to be displayed from the RAM to make an intelligible picture. To accomplish this synchronization and to establish blank margins at the top and bottom and left and right of the twenty-four lines of displayed text, four signals must be developed. Sychronization of the horizontal sweep oscillator is accomplished by a sync flip-flop 140 and synchronization of the vertical sweep oscillator is accomplished by a Vert. Sync signal. Blanking of the video information from the right of the last character in a line of text through retrace and up to the first character in the next line is accomplished by a flip-flop 138.A blank signal BLNK causes blanking from the right of the last character of the last line of the twenty-four lines of next through tracing of the lower blank margin, vertical retrace and through tracing of the top margin to the first character of the first line of text in the next frame.

Horizontal address counter 22, vertical address counter 26 and microprocessor 14 generate these four synchronization and blanking signals.

The horizontal address counter counts out the 89 character display periods in each line and causes flip-flop 1 38 to blank out the video signal to the left and right of the 64 characters displayed in each line of text. The horizontal address counter also causes the horizontal sync signal to be generated by flip-flop 140 at the end of each line.

The sync flip-flop drives the vertical address counter 26. This counter provides the vertical address data of the line being traced. This vertical address is used by RAM 25 in accessing the character to be displayed. The first bit of the vertical address is used to set the interrupt flipflop 169 to 1.

This flip-flop sends a signal to the microprocessor 14 for every positive pulse from counter 26. Since the first bit of counter 26 changes at every signal from flip-flop 140, microprocessor 14 is interrupted every second line in each half frame.

The Vert. SYNC and Blank signals are controlled by microprocessor 14 by setting or resetting of a VSYNC and BLNK flip-flop of video status register 30. The microprocessor decides when to turn the VSYNC and BLNK flip-flops on and off by counting interrupts. Four subroutines each starting at a different interrupt count are used to do this. One routine turns on the screen to start the display. The first thing it does is load the vertical address counter with the address of the first line to be displayed. By controlling this address, either the scroll mode or page mode of display can be used. The routine then loads an internal register in microprocessor 14 used to keep track of the interrupt count with the count at which the next subroutine is to be entered.This internal register is decremented at each interrupt until the count reaches zero at which time the next subroutine is entered. Finally, the routine starts the display by turning the BLNK signal off. This enables gate 50a, thereby enabling video information to be developed on the VOUT line. The twenty-four lines of text are then displayed with each interrupt decrementing the internal interrupt count register.

The BLNK signal must be turned back on at the end of the last line of text. A second subroutine, which is entered when the interrupt count register reaches 0, performs this task. It also resets the interrupt count register to another count such that at third subroutine will be entered after the last line of the half frame has been traced. Finally it checks to see if the half frame being traced is even or odd scan and sets the VSR-EVEN bit of video status register 30. (This bit can in a sense be regarded as the highest bit of vertical count).

The third subroutine functions to turn on the VSYNC bit ("on" EQUALS "low") to cause vertical flyback of the electron beam from the bottom to the top of the screen. The VSYNC signal is gated through gate 88 to ground the VOUT signal. The microprocessor keeps the VSYNC bit on for 3 interrupts by setting the internal interrupt count register to 3. Thus, the fourth subroutine will be entered three interrupts later to turn the VSYNC bit off. Because interlaced scan is used, the VSYNC signal must be triggered in the middle of the last line in every other half frame. The third subroutine functions to provide for this delay depending upon whether the scan is even or odd as determined by the second subroutine.

The fourth subroutine serves to turn the VSYNC bit off at the top of the new half frame. It also sets the interrupt count register to the count necessary to branch to the first subroutine to turn off the Blank signal at the beginning of the first line of text so as to provide a top margin of blank lines. The subroutine also toggles an internal scan bit changing the type of scan from even to odd to even. These four subroutines are each executed once for each half frame. Other programs may be used or the microprocessor may be eliminated altogether in some alternative arrangements.

As described earlier, each of the 24 text lines of characters displayed per frame consist of 16 horizontal lines of dots. 4 of these 1 6 lines, 2 at the top and 2 at the bottom, are left blank in the preprogrammed matrices stored in the character generator ROM 33. These 4 blank lines of dots act as spacers between the lines of text. In all 384 lines of the frame are used for the 24 text lines, the remaining available lines being used as top and bottom margins.

The output signals SC of clock 1 9 is fed to character shift register 21 and graphics shift register 21 a. Character generator 33 loads character shift register 21 in parallel format with 7 bits representing one horizontal line of dot matrix of the character to be displayed. 2 dots of the 9, one on the left and one of the right, are left blank for spacing purposes. These bits are shifted out one per clock cycle. A similar situation occurs with graphics shift register 21 a and graphics PROM 34.

The video information from shift register 21 and 21 a enters gate array 38. Only one gate of this array is used at any one time to gate dot pattern video information through to the T.V. set.

The reason four gates are needed for the video gating function performed by gate array 38 is to accommodate the terminal field reversal and graphics option capability. Each character can be displayed as either white on a black field or black on a white field. The eight bit of memory storage for each character is used to determine the field setup. This bit, MD7, will cause a black on white display when it is off and the graphics option (controlled from the keyboard) is off. The graphic option status is set by the microprocessor in response to a control character from the keyboard. The microprocessor sets the option bit of video status register 30 via data bus 13.

As seen from Figure 2, when the graphics option is off gates 45 and 46 have opposite signals at their inputs such that graphic signals from 21 a is barred and the signal from 21 is allowed through to the T.V. set. Field format is reversed with the signals to gates 45 and 45a.

The signal from flip-flop 49 controls whether the display is black on white field or white on black field. The state of this flip-flop is controlled by the state of the MD7 signal (the seventh bit of the character word stored in memory). A control 0 is entered from the keyboard to reverse the field format. A control N is entered from the keyboard to enable the graphics option.

It is seen from the above that, depending upon the state of the fielde reversal flip-flop 49 and the graphic option signal, several different display possibilities are presented. Summarizing these possibilities: Graphics MD7 Option Display Type Off Off Black on White On Off Black on White Off Qn Black on White On On Graphics Option On Off White on Black The output of gate array 38 will be high if the screen is to be white and will go low for black for negative sync.

Character generator 33 needs a character data input for providing the address from which to retrieve the dot line byte comprising one of line dots in the character dot matrix. The 7 bits of the ASCII code for the character to be displayed are presented to character generator from the RAM 25. 4 other signals representing 4 bits (including VSR-EVEN) of the vertical address form the address where a dot line byte from the dot matrix comprising the character to be displayed may be found. These bits tell character generator 33 which horizontal line of dots to display of the sixteen lines of dots in the vertical dimension of the dot matrix.

Character shift register 21 receives the parallel format dot line byte from character generator 33.

The shift register shifts the dot line byte out serially at the rate of one dot for every cycle of the SC signal. These data bits propagate through gate array 38.

The video data portion V OUT will reach its most positive point with all the input gates array 38 disabled. If any of the gates of array 38 or the Line-Active gate 63 or the Blank gate 77 is enabled, the VOUT signal is then dropped to a lower voltage. With either the VSYNC signal or the HSYNC signal enabled (low), the output of gate 88 grounds VOUT.

The clock and timing circuitry 19, 20 is, as noted above, a 12.5 MHz clock 19 and a divideby-9 counter 20. The counter 20 has two outputs-the ADVH signal already mentioned, and an end-of-cycle signal which appears alternately with ADVH.

Figure 3 is a block diagram of the circuitry for generating a variety of control signals required throughout the system. The microprocessor 14 produces certain output control signals. These are fed to a gating network 1 57a, of AND and OR gates. In order to obtain a greater number of separate control signals than is available from the microprocessor 14 directly, 3 bits from the address bus 1 5 are fed to a decoder 151 which also feeds the network 157a, so that the signals from the microprocessor 14 can be combined with the decoded address bits to yield further control signals. The microprocessor can thus control such functions as reading or writing in the RAM 25, monitoring the keyboard 12 reading its program from the EROM 18, setting the video status register 30, controlling the modem 10 and the parallel port 11, etc.

It takes a few hundred ns to access the character data from RAM 25 and to access the dot pattern from character generator 33 or graphics PROM 34. Therefore, the parallel load command to character shift register 21 and graphics shift register 21 a should be delayed slightly from the time the address of the character to be displayed is presented to the RAM. To create this delay, the Shift-Load signal to the shift registers 21 and 21 a is derived from the end-ofcycle signal from counter 20.

Microprocessor 14, shown in more detail in Figure 3, is initialized at powerup by an initialize circuit (not shown). Serial input from the modem is handled by microprocessor 14 via the Rx signal.

When no character is being received, the Rx signal is high. The program continually interrogates this input to determine when a character is being received, with the beginning of a character indicated by a high to low transition.

The signal Rx is latched into flip-flop 30a (which is in fact part of video status register 30). This changes the hardware generated interrupt vector on the next interrupt by changing the information on data bus 1 3. When microprocessor 14 receives an interrupt request, it drives the INTACK signal low, which enables gate 106a. The lowering of INTACK indicates that microprocessor 14 is ready to receive the interrupt vector from the data bus. The interrupting device is responsible for supplying this interrupt vector to the data bus. This occurs with the transmission of signal Rx to bit D3 of data bus 13. The subroutine entered via this interrupt vector sets flip-flop 30b of the video status register 30 to keep the interrupt vector pointed to the new routine. The Rx bit is then periodically tested so that the incoming character may be assembled.

The microprocessor 14 also scans the keyboard 12 by addressing it via the address bus 15 and the decoder 1 6 and by enabling the buffers coupling its output to the data bus 1 3. The keyboard 1 6 consists basically of a rectangular array of switches. A set of vertical lines are fed from the decoder 16, and each switch can be depressed to connect a vertical line to one of the set of horizontal lines, which are coupled through buffers to the data bus 1 3.

A keyboard scan is performed once for each half frame. During scanning of the Scan lines by microprocessor 14, the data from the Sense lines is read and loaded into an internal register of the microprocessor. There the data is tested after each scan for non-zero to indicate a switch closure, making it possible to check for depression of two keys simultaneously. When a character is sensed, the scanning is continued.

Only when the same character has been sense several times in succession, does microprocessor 14 assume it is a valid character. This procedure eliminates switch bounce.

A parallel port can be included in the system such that data may be received in parallel format from another data processing device and displayed on the screen. Also, data received from the modem or keyboard may be sent out from the parallel port to the other data processing device at the option of the operator by depressing certain control characters on the keyboard.

The terminal may be thought of as having three input peripherals (keyboard, modem, parallel port) and three output peripherals (screen, modem, and parallel port). The software is written such that, by use of control characters from the keyboard, specific input peripherals may be assigned to one or more output peripherals. A three byte table is used to record the desired attachments. The first byte represents the input parallel port, the second byte is the input line from the modem, and the third byte is the keyboard. If bit seven is on in any of these bytes, then the screen is attached to the input peripherals represented by the bytes with bit seven on. If bit six is on, then the output line to the modem is connected to that particular input peripheral. Likewise, bit five represents the output parallel port.

Figure 4 shows the logic arrangement of the external parallel port 11. It consists of two eight bit tri-state registers, input register 11 a for receiving and output register 36 for transinitting.

When a character is transmitted, output register 36 is loaded and the Portoutbusy flip-flop 11 6a is set.

The device receiving the character must sense the Portoutbusy flip-flop to determine when the character for transmission has been loaded from data bus 13.

When output register 36 has been read, the Portoutbusy flip-flop will be reset to allow the terminal to load another character.

A similar situation exists for the input register 11 a. When a character is transmitted to the terminal, the Portinbusy flip-flop 11 8a will be set when a character is loaded into the register. The software scans Portinbusy flip-flop and, when set, will read the contents of input register 11 a resetting the Portinbusy flip-flop. The external device must sense the status of the Portinbusy flip-flop before attempting to reload the input register.

The modem 10 shown in Figure 3 utilizes frequency shift keying modulation. Two frequencies are used to represent a logical zero (space) and a logical one (mark), the two frequencies being 200 Hz apart. Two pairs of frequencies are used for two way communications making the system of the full duplex variety. The lower pair of frequencies is used for translation by the terminal while the higher pair is used for receiving in the originate mode. The modem may also be switched to the answer mode where the situation is reversed, During full duplex operation, both devices are transmitting at the same time.

When no data is being transmitted, modem 10 sends a continuous mark frequency or logical one.

Character transmission commences with a start bit which is the first change from a high level to a low level. The marks and spaces making up the character to be transmitted follow this start bit.

The character can, if desired, be followed by a parity bit and will be completed by transmission of a stop bit returning the communications line to the continuous mark state. This mark state will continue until the next character is sent.

Modem 10 is capable of speeds up to 600 baud, and contains the complete frequency shift keying modulator and demodulator circuitry necessary for FSK modulation. A 1 MHz crystal provides a stable frequency reference. The oscillator output is divided down internally and passed through an internal seven stage frequency counter. The data to be transmitted enters modem 10 on the digital format Tx signal line from microprocessor 14 where it enters an internal modulator frequency decoder. It is modulated there using FSK techniques. The modulator frequency decoder is linked to a seven stage frequency counter and combines with said frequency counter and an internal digitial sine wave generator to provide an FSK modulated digitally synthesized sine wave output. In the originate mode, this sine wave is 1270 Hz for a mark and 1070 Hz for a space in U.S.Standard format while in the answer mode, a mark is 2225 Hz and a space is 2025 Hz. This output signal is amplified in transmitter op amp 121 and fed to a speaker 1 32 for a telephone handset mouthpiece.

A switch 124 which enables the output signal to amplifier 121 is operated by the position of the telephone handset in the cradle.

An originate/answer switch 128 selects the pair of transmitting and receiving frequencies used during modulation and demodulation. A test switch 1 27 will cause the self test mode to be entered where the demodulator is switched over to demodulating the transmitted signal from the modem itself.

The received signal from the telephone handset is picked up by inductive pickup 127 and amplified by receiver op amp 128. the output is passed through either the three stage originate mode or answer mode filter pair 138-9.

Selection of the filter is made by switching. Each filter is comprised of three op amps tuned to form a very sharply defined bandpass filter which will amplify the received frequency pair and reject all other frequencies.

The output from these filters is squared up and limited by a signal limiter op amp 133 and amplified to the demodulator of modem 10.

Modem 10 passes the received signal through an internal level change detector and demodulator counter linked to the internal 1 MHz oscillator. The signal is then passed through an internal demodulator decoder for conversion to a digital signal for output as the Rx signal to microprocessor 14.

Claims (9)

Claims

1. A computer terminal comprising: a keyboard which allows the entry of data and control by an operator; interface means which interface with another data processing device so that data may be sent to and received from that other device; a memory for storing data; display means; and control means which monitors the keyboard and the interface means, and in response to control signals, sends data from the memory via the interface means, stores data in the memory from the interface means, and displays data stored in the memory on the display means.

2. A terminal according to Claim 1, wherein the interface means comprise a modem, for interfacing with a communications network, which converts data serially between binary and FSK forms.

3. A terminal according to either previous claim, wherein the interface means comprise a parallel port which transmits and receives data in binary parallel form.

4. A terminal according to any previous claim, wherein the control means comprise a microprocessor and a read-only memory storing its program.

5. A terminal according to any previous claim, wherein the display means is a commercial T.V.

set.

6. A terminal according to Claim 5, including a video signal generating circuit fed by a horizontal sync flip-flop which controls the horizontal sync portions of the waveform to the T.V. set, and a vertical sync flip-flop which controls the vertical sync portions of the waveform to the T.V. set.

7. A terminal according to Claim 6, including a line active flip-flop which controls the left and right margins of the display on the T.V. set.

8. A terminal according to either of Claims 6 and 7, including a vertical scan counter which counts the line scans, and a read only memory addressed by a combination of the character to be displayed, obtained from the memory, and the low order bits of the vertical scan counter, to generate the signals which cause a visual representation of the character to be displayed.

9. A computer terminal substantially as herein described.