GB2052812A - Computer response time monitor - Google Patents

Abstract

Time required for completion of a computer operation or time between such operations is measured at a computer terminal by means of counter accumulating clock pulses. The resulting data is encoded in the format used for entering keyboard data into the terminal and transmitted to the computer. A keyboard lock or enter data signal generated at the terminal controls the timing. Other measurement functions may be performed. The measurement data may be displayed on a CRT at the terminal.

Description

SPECIFICATION Response time monitor This invention relates to electronic data processing apparatus. More specifically, it relates to means responsive to signals being transmitted between a computer and a display unit having a keyboard for measuring the response time of the computer, that is, the time required for completion of a computer activity. t Many forms of data processing systems are known in the art which include data input equipment, a central processor, a memory and output devices, such as printers, punches, memories, and the like. In these systems, data which is either stored in the system or entered into the system by an operator, for example by a keyboard, is manipulated in accordance with predetermined programs, and then the completed work is displayed visually or in a printout or otherwise recorded for later use.In large scale systems of this general type, use is frequently made of terminals, placed in different locations for the convenience of the user, by means of which many different users can have access to the computer for the performance of the variety of data processing operations which may be programmed into the computer. Because of the high cost of acquiring and operating computer equipment, it is desirable for the organization using the computer to have accurate cost information regarding the time that it takes the computer to perform each operation for each different user in order to enable the organization to allocate and control the cost of using the equipment most effectively.

For this purpose, it is desirable to know the actual operating or response time the computer takes to complete a particular transaction or process. This information should be made available at the computer terminal, as part of the information displayed, or it can be made available as a printout, or collected in the computer itself.

The need for computer process time measurement capabilities of the type just described has been recognized in the computer industry and arrangements in which operation of timing circuitry in the computer is controlled by programmed instructions are known.

There is a need, however, for a simple inexpensive auxiliary equipment which can be added to existing systems for performing this function.

One auxiliary system is known, which may be attached to a computer and which depends for its operation on the "system available" status symbol which is flashed on the viewing screen of the terminal when a particular operation is completed. The "system available" or "system inhibit" signals used in a display terminal are usually in the nature of a spot and may, for example, be made up of several horizonal lines of the video raster having a length equal to the width of an alphabet character and appearing at a location on the right hand side of the screen.

In this prior art auxiliary system, a photoelectric cell is applied to the face of the cathode ray tube to detect the light from the status symbol. When the symbol is detected, a microprocessor, separate from the computer being measured, processes the signal from the photocell. For such processing it may be necessary to compensate for variations in the signal strength resulting from the software used, for scan characteristics, for changeable refresh rates, for spot brightness and duration, and for other system characteristics which influence the brightness of the spot. This system is complex and its performance is easily affected by failure to compensate precisely for the system variables just mentioned.

It is an object of the present invention to use one or more signals generated by a computer for measuring the time it takes the computer to complete a particular operation.

A further object of the invention is to provide a relible and convenient system of measurement for use at a computer terminal which is also capable of supplying the information generated to the central processor.

Another object of the invention is to provide a reliable and convenient system for measurement of the number of key strokes required to complete a particular transaction.

Still another object of the invention is to provide a reliable and convenient system for use at a computer terminal which is capable of reading the dead time between transactions at the terminal.

The present invention uses a signal generated at the terminal keyboard when the "Enter" key is depressed to initiate counting of internally generated clock pulses in a main counter. The process related signal used for this purpose is a "keyboard lock signal," directed to the keyboard from the terminal visual display unit to prevent operation of the keyboard from affecting the computer during completion of the work in process. Once begun, counting of the clock pulses continues as long as the "keyboard lock signal" remains in effect.The measurement process ends when the keyboard is released at the end of the process and signals generated in response to elapsed time information stored in the main counter are coded and supplied to the display in the same form as from the keyboard so that the response time information appears in normal decimal sequence on the face of the cathode ray tube at the end of the measurement cycle. Readout to the display unit begins when the timing measurement ends. A second counter generates binary signals which control the operation of electronic switches connected in the circuits between the keyboard and the display by which signals, coded in the proper form, are supplied to the display input wiring for translation by the display into visual timing data.An auxiliary output is provided for operating a separate printer and provision is made for selection of keyboard lock signal or like information from a source other than a terminal to which the timing equipment is connected.

In the preferred embodiment described above, the timer circuit of the invention is illustrated in connection with a computer. According to another feature of the invention, transfer of a response time measurement can be initiated in response to a keyboard code signal, such as "ENTER", instead of an unlock signal. Then, instead of entering response time data in the first three character positions of the display unit buffer, by delaying the strobe associated with the ENTER key the data is placed in the last three character positions of the screen buffer, following data keyed in by the operator.

Data other than response time measurements may be transferred into a computer data stream by insertion through the apparatus disclosed. For example, the number of key strokes per transaction may be monitored by means of a counter unit which responds and counts the strobe pulses generated by each key stroke, thus providing a measure of the "traffic", or operator activity. By means of additional electronic switches, the tally in the keystroke counter is read out of the response time monitor, in sequence, after the response time measurement. Then the keystroke data is stored, in sequence, in the display unit in the same way as the response time data.

The information transmitted to the host computer need not be limited to transaction measurements; other data may be translated or coded into the proper form for insertion into the data stream and supplied to still more inputs of an expanded, multiple-position electronic switch.

For terminals using handshake signals between the display and the keyboard for controlling transmission of data from the keyboard to the display, another embodiment of the invention provides for switching of additional input data, coded in the proper form, through the monitor switches and into the display upon receipt of a data acknowledge signal from the display.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an illustrative embodiment of the invention; Figure 2 is a schematic diagram illustrating the logic activating the main counter and electronic switch of the response time monitor of Fig. 1; Figure 3 is a schematic diagram of the main counter and the electronic switch of Fig. 2; Figure 4 is a block diagram of a digit scan counter useful in the circuit of Fig. 1; Figure 5 is a schematic diagram of the counter and electronic switch of Fig. 2 modified to respond to an ENTER code; Figure 6 is a schematic diagram of a circuit for sensing the presence of an ENTER code; Figure 7 is a schematic diagram similar to that of Fig. 2, but modified to include a keystroke counter; and Figure 8 is a block diagram of a circuit for implementing the keystroke counter function shown in Fig. 7.

Figure 9 is like the circuit of Fig. 3, but in addition provides for transfer of additional input data in response to a data acknowledge signal from the display.

Reference is made to Fig. 1 in which a keyboard 2, connected through response time monitor 4, supplies control signals to the visual display unit 6. For the sake of illustration, the teachings of the present invention are illustrated herein in connection with a response time monitor realized in connection with a type 3277 Interactive Terminal which is produced by the International Business Machines Corporation and which is connected, via a type 3271 Controller connected to line 7, to a central computer. The response time monitor is connected between the keyboard and display units of the Interactive Terminal by opening the connector in the cable which joins them and by inserting appropriate female and male connectors, connected to the monitor, as will be understood by those skilled in the art.In Fig. 1 this has been done and, with response time monitor 4 in the circuit, signals between keyboard 2 and the display 6 are transmitted through the monitor unit by means of the illustrated connections. In operation, "system available" and "system inhibited" signals are transmitted to and made visible on the screen of display 6 indicating whether the keyboard may be used or is disabled.

Whether or not the keyboard is disabled depends upon a keyboard lock signal which is generated in the computer system. When a keyboard lock signal is transmitted from display unit 6 6 to keyboard 2, monitor 4 is activated and, when the computer process has been completed, the time measurement which was thus initiated is stopped. The monitor then transmits the amount of time so measured to display 6 in the same format as signals from the keyboard where it may be retained in storage until polled by the computer. Thus, the response time information becomes a part of the normal data flow between keyboard and main computer, and each transaction entered by the operator will have the response time information for the prior transaction appended to it.The information thereby automatically becomes available to the main computer where it may be stored and or processed as part of the normal data processing trail.

This obviates any requirement for manual intervention or ancillary means of data collection. This information is available to the central computer system via the link from the Interactive Terminal and needs only to be called for by the computer.

The structure of response time monitor 4 is shown in more detail in the block diagram of Fig.

2. There, it can be seen that the main interconnection between keyboard 2 and display unit 6 is provided by an electronic switch 8. There is also provided an auxiliary output 9 for connecting signals to a printer, for example, to make permanent local record of the data. The operation of electric switch 8 is controlled by signals S, and S2, transmitted on lines 16 and 18, respectively, to choose signals from keyboard 2 or, when a time measurement has been completed, from main counter 10. Parity circuits 14 are also fed by counter 10 for generation of parity signals which are transmitted to display 6 to provide appropriate parity information related to the activity of counter 10, as will be understood by those skilled in the art.

Control of the counting and signal generation circuitry is initiated by means of a keyboard lock signal transmitted on line 20 from keyboard 2 to the logic circuitry shown at the left of Fig. 2.

The measurement system employs a master clock 22 which is a free-running multi-vibrator operation at 1OHz. The square wave output of clock 22 is supplied by line 24 to one input each of AND gates 26 and 28. The other input of AND gate 26 is supplied, via inverting driver 30, with signals which are the inverted from of keyboard lock signals KL supplied by line 20. Line 32 from AND gate 26 is connected to main counter 10; provision is thus made for control of the supply of clock pulses to main counter 10 by the keyboard lock signal.

The 1 OHz clock signal fed to AND gate 28 is also gated into digit scan counter 12 via connecting line 35. It thus serves as the base for generation of switch control signals S1 and S2. Clock pulses are also fed from the output of gate 28, via NAND gate 34, inverting amplifier 36, and flip-flop 38, to provide strobe pulses for transmission on line 40 to electronic switch 8.

The strobe pulse activates display unit 6 after selection of each digit of the timing measurement to be displayed. Just prior to generation of the strobe pulse, digit scan counter 12 generates a "master reset" pulse which resets digit scan counter 12, and, via connecting line 42, main counter 10, and data entry cycle flip-flop 44.

Provision is made for selection of keyboard lock signal or like information from a source other than the terminal to which the timing equipment is connected. Control of the counting and signal generation circuitry by means of a keyboard lock signal transmitted on line 20 from keyboard 2 to a logic circuitry shown at the left of Fig. 2. Keyboard lock signal KL is supplied, via inverting driver 30, to "counter run gate 26, from the pin of single-pole, double-throw, "inhibit select" switch 46. This switch may be operated to choose between keyboard lock signal KL or an inhibit signal supplied from an external source, connected to the other terminal of the switch. Whichever signal is chosen, (in Fig. 2, the KL signal), is fed from switch 46 to manualautomatic switch 48.By operation of switch 48 choice may made of whether push button 50 or keyboard lock signals KL will cause the transfer of the timing information of the display. As shown, switch 48 is in the internal cycle scan operate position, and the keyboard lock signals KL are fed, via digit scan gate 52, to data entry cycle flip-flop 44.

At the end of the response time interval, keylock signal KL goes high, clock pulses are no longer transmitted by AND gate 26 to main counter 10, and the data entry cycle is begun.

During the data entry cycle the measured response time stored in main counter 10 is scanned out into display unit 6 and appears to the display unit to be normal keyboard signals. "D" type flip-flop 44, which controls the data entry operation is set; once "set", it cannot be reset until a reset signal is received on line 42. Activation of flip-flop 44 by keyboard lock signal KL results in application of a signal from the Q output of the flip-flop to one input of gate 28, via line 54, as well as to an input of digit scan 52, via inverter 53. As a result, clock pulses from clock 22 are transmitted to digit scan counter 12, and a holding signal is applied to gate 52 to inhibit further input transitions of data entry cycle flip-flop 44 until the end of the scan cycle.

Reference is now made to Fig. 3 which shows detail of a circuit for transmitting the count stored in main counter 10 either through electronic switch 8 to display unit 6 or, separately, to auxiliary output 9 for use by an external printer or the like.

Shown in Fig. 3 are electronic switch 8, which contains five Dual input Multiplexers 60, 62, 64, 66, and 68, constituting the individual switches. Also shown are decade counters 70, 72 and 74, which comprise the main counter 10. Decade counters 70, 72 and 74 may be of the Divide-By-2 and By-5 type. In addition, there are parity generators 76, 78 and 80. These may be 9-Bit Odd/Even Parity Checker/Generators. Counters 70, 72 and 74 are connected in cascade, and clock pulses from AND gate 26 are applied to the input of first counter stage 70 via line 32. The outputs of the counters are in binary-coded decimal form, so that, when first counter 70, the tenths counter, changes from a count of 9 to 0, a signal is conveyed from the OD output of counter 70 to the input of counter 72, causing it to advance one count.Similarly, the QD output signal from second counter stage 72 drives third counter stage 74. Since the clock rate is ten pulses per second, the first stage of counter 10 advances the second counter stage once per second, and the second stage advances the third stage once every ten seconds.

A timer having a maximum count of 99.9 seconds is thus provided. It will be understood by those skilled in the art that the maximum time to be measured will determine the counting capacity, and that longer times merely requires the addition of another counter stage for each decade to be counted.

Fig. 3 also shows that all four outputs QA, QB, QC, QD, of each counter 70, 72 and 74 are connected to multiplexers 64, 66, and 68 and to parity checker/generators 76, 78, and 80, as well as to auxiliary output 9. In particular, it will be noted that the QD outputs of counter units 74, 72, and 70, are connected by connecting lines 83, 85, and 87 to input terminals 1 Cl, 1 C2 and 1 C3 of third multiplexer 64, respectively.Similarly, the QC outputs of each counter unit are connected to the 2C1, 2C2 and 2C3 inputs of multiplexer 64, and the QB and QA outputs of main counter units 70, 72, and 74 are respectively connected to the 1C1, 1C2, and 1 C3 and 2C1, 2C2, and 2C3 inputs of multiplexer 66. Provision is thus made for selection of individual output signals from counter units 70, 72, and 74 by the switch unit.

Before describing the remainder of the circuit of Fig. 3, reference is made to Fig. 4 which shows detail of digit scan counter 12. Counter 12 controls the indexing of multiplexers 60 through 68 by means of control signals S1 and S2 transmitted on connecting lines 16 and 18, respectively. As shown Fig. 4, these signals are generated at the Q outputs of flip-flops 82 and 84 which form the first two stages of a three stage counter circuit. The three flip-flop stages, 82, 84 and 86 of digit scan counter 12 may be Dual J-K Master-Slave flip-flops with Preset and Clear. The input to first digital scan flip-flop 82 is provided on line 35 from AND gate 28, as was discussed previously, and is controlled by data entry cycle flip-flop 44. Clearing of the three counters, 82, 84, and 86 is accomplished by connection to line 54.The output of flip-flop 82, taken from the Q terminal, is supplied as switch control signal S1 to connecting line 16. The inverse of this output, Q, is connected to the clock input of second flip flop 84. The Output of of flip-flop 84, connected to line 18, supplies switch control signal S2. Output signal 0 of flipflop 84 is connected to the clock input of flip-flop 86, whose 0 output terminal supplies the reset signal transmitted by connecting line 42 to decade counters 70, 72, and 74 of main counter 10 and to one input of AND gate 27, for control of the transmission of clock pulses from clock 22 to the reset terminal of data entry flip flop 44. The Q output of flip flop 86 is connected to AND gate 34 for generation of the strobe pulse.

Referring back to Fig. 3, it will be seen that the input terminals 1 Cl, 1 C2, and 1 C3 of multiplexers 60 and 62 are all connected to a fixed supply voltage through a dropping resistor.

A A positive signal is thus transferred to multiplexer output terminals 120, 122, 124 and 126 when the internal switching logic of the associated multiplexer connects any of the input terminals to its output terminal 1Y or 2Y.

The fifth multiplexer 68 in electronic switch 8 chooses the parity and strobe signal outputs to be fed to display 6. Thus, parity signals, generated in parity checker/generators 76, 78, and 80, are transmitted on lines 90, 92, and 94 and to terminals 1C1, 1C2, and 1C3, respectively, of multiplexer 68. Similarly, strobe pulses generated on line 40 of monitor 4 are connected to terminals 2C1, 2C2, and 2C3 of multiplexer 68.

Connections from keyboard 2 are made by means of connecting lines 100 through 118, all of which are supplied via dropping resistors from the 5-volt system supply and are connected to the multiplexers as follows. Keyboard lines 100 and 102 are connected to input terminals 1 CO and 2CO of multiplexer 60. Keyboard lines 104 and 106 are connected to input terminals 1 CO and 2CO on multiplexer 62. Keyboard lines 108 and 110 are connected to input terminals 1 CO and 2CO on multiplexer 64. Keyboard lines 112 and 114 are connected to input terminals 1 CO and 2CO on multiplexer 66, and keyboard lines 116 and 118 are connected to input lines 1 CO and 2CO on multiplexer 68.

The purpose of the assembly of five multiplexer switches in electronic switch 8 is to determine whether 8-bit character coded signals from keyboard 2 or from counter 10 will be transmitted to display 6. In normal operation, signals flow directly through the switches between keyboard 2 and display unit 6. When a time measurement cycle provided for by the monitoring arrangement of the invention is completed, these same switches serve to transmit simulated keyboard signals constituting the measurement data in 8 bit character coded signals from the response time monitor circuitry to display 6 for automatic display. At the same time, parity and strobe signals originating in the response time monitor are substituted for those normally transmitted from keyboard 2 on keyboard lines 116 and 118. The IBM equipment on which the response time monitor was fitted utilized EBCDIC (Extended Binary-Coded Decimal Interchange Code) character coded signals. In this code, only the last four digits are required for transmitting the numeric information from the response time monitor. Therefore, provision is made by means of three of the inputs to multiplexer 60 and 62 to substitute positive voltage signals for the Bit 0, Bit 1, Bit 2, and Bit 3 signals of the first four digits being fed in on keyboard lines 100, 102, 104 and 106, respectively. As was seen above, the Bit 4, Bit 5 and Bit 6, and Bit 7 inputs to multiplexers 64, 66, and 68 are supplied by the main counter unit.

Switch unit 8 provides the electronic equivalent of ten 2-pole, 4-position switches, all of which are simultaneously switched by switch signals S1 and S2 connected to the SA and SB terminals, respectively, of each multiplexer. Therefore, the input from keyboard 2, suppled via keyboard leads 100, 102; 104, 106; 108, 110; 112, 114; and 116, 118, to the 1C0 and 2CO input terminals of the associated multiplexers, will be connected to display output lines 120, 122; 124, 126; 128, 130; 132, 134; and 136, 138, respectively, when no signals S1 or S2 are transmitted to the multiplexers on control lines 16 and 18. When activated by signals S1 and S2, the multiplexer switches transmit the simulated keyboard signals to the display unit.

Table 1, below, illustrates the correspondence between the logical state of control signals S1 and S2 and the choice of input signal switched to the output Y1 and Y2 of the electric switches.

When both control signals S1 and S2 are at logical 0, the signals from the keyboard are fed directly to display unit.

TABLE I SWITCHING OBTAINED WITH DIFFERENT CONTROL SIGNAL COM BINATIONS Logical State of Control Signal Input Signal Switched to Ouput Output Output S1 S1 1Y 2Y O 0 1 C0 1C0 2CO 0 1 1C1 2C1 1 0 1C2 2C2 1 1 1C3 2C3 The relation between the states of the scan cycle counter flip-flops and the connections established in the multiplexers for sequential supply of time measurement related signals from the main counter to the display for production of decimal digits in the usual significance is shown in Table 2, below.

TABLE 2 SCAN CYCLE SEQUENCE I States of Cycle Switch Description Scan Flip-Flops Control Signals Count 82 84 86 S2 S1 O Before Reset Reset Reset O O Keyboard Connected to Cycle Display 1 Reset Reset Set 0 1 Tens Digit Fed to Display 2 2 Reset Set Reset 1 0 Units Digit Fed to Display 3 Reset Set Set 1 1 Tenths Digit Fed to Display 4 4 Set Reset Reset O O Keyboard Connected to Display Cycle Terminated, Reset Reset Reset O 0 Counting Stopped The switching circuit provided by multiplexer 68 supplies the parity bit (even parity), and strobe signals required to complete the transfer of EBCDIC, character coded data to the display unit.

The keyboard signals, such as keyboard lock, shift control, and alarm signals, are routed to the display unit, along with power supply and ground circuit connections, via wiring in the interconnecting cables (not shown), as will be understood by those skilled in the art.

Operation of the circuit described above is as follows. Clock pulses from AND gate 26 are fed to first counter stage 70 in main counter 10. When tenths counter 70 changes from a count of 9 to 0, the transition of the high order bit signal, QD, is coupled to the input of counter stage 72, causing it to advance one count. Similarly, the QD signal from second stage 72 drives third counter stage 74. The outputs of these counters are fed to the input terminals of multiplexers 64 and 66 for selection to form the lower order bits of the 8-bit EBCDIC code. As was discussed above, the high order bits of the EBCDIC code are supplied by multiplexers 60 and 62.

When a count has been completed, the four lower bits of accumulated value in three stage main counter 10 are sequentially switched, as shown in Table 2, under control of sequential signals S1 and S2 from digit scan counter 12. Their outputs are switched to the C1, C2, and C3 multiplexer input connections.

Parity scanner/generators 76, 78 and 80 generate required parity bits for the BCD outputs of main counter stages 70, 72 and 74 respectively. These are fed to the 1C inputs of electronic multiplexer switch 68, which provides sequential selection of the parity signal associated with each digit selected during the data entry cycle.

At the end of the response time interval, the keyboard lock signal returns to high level. This causes AND gate 26 to inhibit the clock pulses which were driving main counter 10, and marks the beginning of the data entry cycle. During the data entry cycle, the response time measurement stored in main counter 10 is scanned into display 6 instead of the normal keyboard signal. To this end data entry cycle flip-flop 44 is set by the positive level transition at its clock input. Flip-flop 44, once set, cannot be reset until a low level signal is applied at its reset input. Flip-flop 44 is normally in the reset state, with its Q output at low level and its Q output at high level. The feedback signal from the 0 output is inverted by inverting amplifier 53 and fed to one input of AND gate 52.The other input of AND gate 52 is fed the keyboard lock signal via non-inverting driver 49. When both inputs to AND gate 52 are high, the high output produced is fed to the clock input of data entry cycle flip-flop 44, switching it to the set condition and causing its Q output to go high. The inverted feedback signal from the Q output then inhibits further input transitions, keeping flip-flop 44 in this condition until it is reset at the end of the scan cycle.

Sequential scanning of the three response time digits is controlled by digit scan counter 12.

Initially, the Q output of scan flip-flops 82, 84 and 86 are at a logic 0 or low voltage level.

When data entry cycle flip-flop 44 is in the set position, AND gate 28 is enabled and passes counting pulses to the input of the first counter, flip-flop 82. The counting pulses appear during positive going cycles of clock 22 when a true condition occurs at the input of AND gate 28. The first three counts advance the first two stages of the counter and produce switching control signals S1 and S2 which are transferred by lines 16 and 18, respectively, and control the operation of multiplexer switches 60, 62, 64, 66 and 68. This results in sequential selection of the BCD signal outputs in main counter 10 for transmission to the display.

When the keyboard is in operation, the strobe pulse from the keyboard gates the keyboard data signals into the display immediately after each new character code is produced by depressing a key. In order to prevent premature data entry by the operator after occurrence of the "systems ready" signal on the display, generation of the strobe signal is delayed by one-half clock cycle. This is accomplished as follows. The positive pulses from AND gate 28 occur during the positive half of the clock cycle. The signal fed to strobe generator 38 is inverted by inverter 39 and so provides positive-going pulses during the second half of the clock cycle which are coupled through NAND gate 34. With both its inputs high, NAND gate 34 has a low output.

The Q signal from third stage flip-flop 86 of digit scan counter 12, which is fed to the other input of NAND gate 34, is normally high during the first three cycles of scan counter 12. Thus, one input of NAND gate 34 is enabled. Due to the inversion of pulses supplied from inverter 39, the output of NAND gate 34 goes low during the second half of the clock cycle and remains so until the Q output of third stage flip-flop 86 changes to low.

The net result of the gating circuitry just described is to provide a pulse which occurs in the second half of clock cycles occurring during the first three counts of digit scan counter 12. This interval is called the strobe interval. The logic level of the strobe interval pulse is inverted by inverter 36 and supplied to one-shot multivibrator 38, which is designed to produce a negativegoing pulse of 5 milliseconds duration at the leading edge of the strobe interval. This strobe pulse is fed to the 2C inputs of electronic multiplexer 68 to provide the required strobe pulse for display 6, after selection of each digit. Immediately after the fourth pulse fed to the digit scan counter 12, the positive transition of output Q of third counter 86 causes the master reset to occur before the strobe pulse. This master reset pulse is supplied by line 42 to all main counter and digit scan counter stages as well as to data entry cycle flip-flop 4, resetting them. The path of the reset signal through AND gate 27 and inverter stage 29 provides noise immunity and level inversion for signals to be supplied to the "clear" input of data entry cycle flip-flop 44.

It will be noted, in addition to connections to the BCD outputs of main counter stages 70, 72, and 74, the auxiliary output is also provided with a strobe pulse connection to facilitate operation of an attached printer, for example.

In an alternative embodiment of the invention, a single parity generator is connected across the output signals from electronic switches 60, 62, 64, 66, and 68. In this way a keyboard fail indicator can be added as a parity generator, which will also generate a parity bit for signals fed to the display unit from the keyboard. The parity bit generated in this way is compared with the parity signal from the keyboard to check the integrity of data flowing through the monitor from the keyboard to the display.

The process described above can be used with equal facility to measure the interval between operations and to provide a direct measurement, for example, of time chargeable to overhead.

Inversion of the keyboard supplied to switch 46 will result in initiation of a timing measurement by the restoration of keyboard control to the operator. Thus when the keyboard signal from keyboard 2 goes low, releasing the keyboard to the operator, inverter 120 supplies a positive keylock signal, permitting clock pulses to flow from clock 22 to counter 10. Similarly, when the keyboard signal goes high at the time the "Enter" command is given at keyboard 2, the counting operation is stopped and the data entry cycle begun. The necessary change in circuitry to produce this result is shown in Fig. 2 by the dashed lines.

It will be apparent to those skilled in the art that the principles of the invention, as illustrated in the present embodiment in connection with a particular Interactive Terminal in a computer, can be utilized with a variety of input and output units, either with the computer described above or with other computers by utilizing process related control signals passing between the computer and the terminal to activate the timer and to generate time measurement reporting signals which are compatible with those already in use for communicating between the terminal keyboard or other input and the display.

When the system is measuring response times related to operation of the local keyboard, as described above, readout occurs when the digit scan counter is triggered by transition of the keyboard lock signal going from locked (low) to unlocked (high). When this occurs, the three digit response time value is stored in the buffer of the display unit in the first three digit positions. Data entered via the keyboard subsequently is placed in the buffer after the first three digit positions. When the operator presses the ENTER key, causing generation of an ENTER code at the completion of data entry, the data, including the response time information, is locked into the display.Then the keyboard lock signal operates to lock the keyboard, initiating another response time measurement operation, while the computer is acquiring the data, including previous response time measurement data, during a computer polling or read cycle.

Response time data thus read into the computer can be subsequently stripped out of the data stream as part of the transaction or process performed by the computer.

It is sometimes desirable to delay reading out of the response time data from the monitor until data entry has been completed by the operator and the ENTER key is depressed. The function for doing this is controlled by setting manual-automatic switch 47 (Fig. 7) to the position marked "From Fig. 6" (line 144). Switch 47 corresponds to manual-automatic switch 48 of Fig.

2. The circuitry of Figs. 5 and 6 provides means for doing this. Fig. 5 is essentially the same circuit as was shown and described in connection with Fig. 3, but differs in that passage of the strobe signal from the keyboard directly to the 2CO terminal of parity and strobe signal multiplexer 68, as shown in Fig. 3, is interrupted, with the connecting wiring being brought out, at the bottom of Fig. 5, as strobe lines 118 and 140. It will also be seen, at the top of Fig.

5, that connections to keyboard input lines 100 to 114, the respective transmission paths for bits numbered 0 to 7, are also brought out and directed to Fig.6.

As was pointed out in the description of Fig. 3, the strobe signal transmitted on line 118 from the keyboard is part of the ten-signal data set required for entry of characters from the keyboard into the display unit. When data from the response time monitor is being fed into the display unit, the response time monitor generates a strobe signal of its own which is connected to the display unit by multiplexing switch 68, at the same time that the switch connects the monitor unit to the display unit for transmitting response time data.In the IBM equipment, with which the response time monitor circuit illustrated here is adapted for use, the strobe pulse generated by the keyboard is a negative going pulse and the digit codes and parity signal which are generated when a key is depressed on the keyboard are stored there until the next key strobe occurs, at which time transfer to the display unit occurs.

The circuit of Fig. 6 provides the necessary means for delaying transmission of the strobe pulse for each key stroke until the key code can be examined. If, when examined by this circuit, the code is found not to be an ENTER code, the strobe pulse is immediately propagated to the display unit, allowing normal data entry to occur. However, when an ENTER code is detected by the circuit of Fig. 6, the digit scan cycle is initiated and the response time monitor generates a strobe pulse which is transmitted to the display unit when the electronic switches restore the keyboard signal path. Since the ENTER code was stored in the keyboard, it is then transferred to the display unit, following data entered by the operator.

This process is brought about in the circuit of Fig. 6 by reading the information on input lines 100 to 114 in NAND gate 142. Input lines 100, 102, and 114 contain inverting amplifiers so that the presence of the IBM ENTER code, 0111101, will produce a response in NAND gate 142. When NAND gate 142 is activated by the presence of an ENTER code, NAND gate 142 goes negative and transmits, due to inversion in amplifier 143, a high signal on line 144 to selector switch 47 in Fig. 7. This signal activates readout by the digit scan counter. Generation of the keyboard strobe for the display unit, the original keyboard strobe being delayed, is initiated in the circuit of Fig. 6 by the ENTER code detected signal tramsmitted on line 144 which is also transmitted to terminal A of one-shot multivibrator 146.The B input to one-shot multivibrator 146 is supplied from one-shot multivibrator 148, which, in turn, is triggered by the keyboard stobe signal supplied by line 11 8 to input terminal A. Thus, when multivibrator 146 is enabled by the presence of an ENTER code, an input signal from multivibrator 148 will cause a negative going pulse to be generated and returned on keyboard strobe line 140 to display unit 6.

While the above circuit has been illustrated in conjunction with an IBM enter code, it will be understood by those skilled in the art that other computer systems may use other codes in keeping with the protocol in use, and that, whatever the code, the NAND gate used for detection and its inputs, can readily be adapted to respond. Thus, a TAB code used to move a cursor to another field, or a PF or other special function code incorporated for initiating storage could be used.

Reference is now made to Fig. 7 which shows a diagram of an alternative embodiment of the invention in partial schematic and partial block form. By means of this circuit, which is a modification of the circuit of Fig. 2, a response time monitor, in addition to performing the described measurements of the time for completion of a transaction at the keyboard of a terminal of the time between transactions, may be equipped to generate data which is a function of terminal traffic as measured by the number of key strokes employed in each transaction. By means of this circuit, information as to the number of key strokes is coded and made available in the display unit, along with response time data, for reading into the data stream of the computer.In addition to the change to the manual-automatic switch described above, Fig. 7 differs from Fig. 2 in that it shows a key stroke counter 150, which receives key strobe pulses on line 118 from keyboard 2. As was explained earlier, such a strobe pulse is generated each time that a key is pressed at the terminal. Key stroke counter 150 is set to zero by a reset pulse from digit scan counter 112 received from line 42, as were the other counters described above.

Key stroke totals are supplied from key stroke counter 150 to parity circuits 14 for generation of parity signals, and to electronic switch 8 which determines when they will be transmitted to display unit 6. As will be seen below, additional switch signals, generated by digit scan counter 12, are transmitted, on lines 154 and 156, to electronic switch 8 and control the added switching function necessary for sequencing the extra digits generated in key stroke counter 150 into the display unit.

Fig. 8 is the circuit of Fig. 4, modified to include the key stroke counting and switch function.

For the sake of simplicity, detail of the wiring which interconnects counters 70, 72, 74 and parity generators 76, 78 and 80 with duplexers 60, 62, 64, 66 and 68, all of which has been described in connection with Fig. 4, has been omitted from the drawings. Instead, the necessary connections from individual response time counters 70, 72, and 74 to the response time parity generators and to multiplexing switches 64 and 66 are indicated by a single connecting line 158. Similarly, a single line 160 interconnects response time parity generator and multiplexing switch 68. As described above in connection with Fig. 3, multiplexing switches 60-68 are controlled by signals S1 and S2 transmitted from JK flip-flops 82 and 84 of scan counter 12 (Fig. 4) on lines 16 and 18. In Fig. 8, this connection is shown as line 162.Monitor strobe line 40, which supplies the pulses needed to cause registration of data read out from the monitor in the storage buffer of display unit 6, is extended from it input connection to multiplexer 68 to provide a similar input to multiplexer 172.

Key stroke counter 150 of Fig. 8 is of the same construction as the response time counter shown in and described in connection with Fig. 3. However, instead of counting timing pulses generated by the clock generator of Fig. 2, counter 150 counts the keyboard strobe pulses originating in keyboard 2 and received on line 118. There individual counter stages, connected in cascade, provide a maximum count of 999. This counter capacity is sufficient for many applications. As will be apparent to those skilled in the art, additional counter stages may be added for each additional decade required, should the need arise. The QA, OB, QC, and QD outputs of each counter stage are all connected, in the same way as provided for the response time counter, to the 1C1, 1C2, 1C3 and 2C1, 2C2, and 2C3 inputs of additional switching multiplexers 168 and 170. This interconnection is indicated by means of connecting line 190.

Keystroke counter parity signals are generated in parity signal generator 161 by means of individual generators which are connected to individual key strokes in the same way as were the individual parity counters of the response time counter in Fig. 3. The outputs of the keystroke parity generators are connected via connecting lines, generally shown as 192, to appropriate 1 Cl, I C2 and 1 C3 inputs of additional switching multi-plexer 1 72.

Other connections to the added multiplexers of electronic switch 8 are as follows: Monitor strobe pulses arriving on strobe line 40, in addition to being connected to inputs 2C1, 2C2 and 2C3 on multiplexer 68, are connected to inputs 2C1, 2C2 and 2C3 on multiplexer 172, The other inputs to multiplexers 60, 62, 64, 66, and 68, are as they were shown in Fig. 3, and serve the same purpose.

Additional connections made to added switching multiplexers 1 64, 1 66, 1 68, 1 70 and 172 include connections from the 1Y outputs of each of the multiplexers 60 to 68 to the 1CO inputs of each of the multiplexers 164 to 172. Similarly, the 2Y outputs of multiplexers 60 to 68 are connected to the 2C0 inputs of multiplexers 164 to 172.

Switching instructions for multiplexers 164 to 172 are generated by JK flip-flops 194 and 196, which have been added to scan counter 12. Switching signals S3 and S4 are transmitted on lines 154 and 156 to the SA and SB input terminals of switching multiplexers 164 to 172.

Last JK flip-flop 198 in scan counter 12 now generates the reset signal for line 42, in the same way as was described above, except that now key stroke counter 150 is also provided with a reset signal.

Operation of the response time monitor with read-out of the added key stroke counting circuit is similar to that described above in connection with the reading out of signals from main counter 10. Response time counter 10 functions in the same way that it did previously, responding to count pulses transmitted to it, for example, when the keyboard lock signal goes negative. Similarly, counting in counter 10 stops when the keyboard lock signal returns to a high condition. When the keyboard lock signal goes high, scan counter 1 2 is activated as before, provided that switches 46 and 48 are in the position shown.

Meanwhile, keyboard strobe pulses supplied to key stroke counter 150 on connecting line 11 8 from keyboard 2 are accumulating in the counters of that unit. Since every action taken by the operator requires a key stroke, everything that the operator does generates a stroke signal for counting in key stroke counter 150. When the keyboard is locked, operation of the keys is prevented; no more signals can be generated by the operator and the previously generated count of the stroke signals remains stored in the keyboard stroke counter until the keyboard lock signal goes high. Scan counter 12 then causes the switching duplexers to read out the accumulated signals in succession from response time counter 10 and key stroke counter 150.

Under command of the S1 and S2 signals first generated by the flip-flops of scan counter 12, the data in response time counter 10 is first scanned out and transferred to the output terminals of multiplexers 64 and 66. As before, duplexers 60 and 62 transmit fixed voltages to complete the EBCDIC numerical code of the IBM system used here to illustrate the invention.

Similarly, but under control of switching signals S3 and S4, the contents of key stroke counter 150 are sequentially read out by multiplexers 168 and 170, immediately following the numbers from response time counter 10. When multiplexers 164 to 172 are not activated, the data transmitted to the 1 CO and 2C0 inputs from 1Y and 2Y outputs of duplexers 60 to 68 is transmitted through to the associated transmission line leading to display unit 6. As is the case with switching multiplexers 60 and 62, switching multiplexers 164 and 166 also transmit fixed voltage signals completing the makeup of the high order components of the IBM EBCDIC signal.

Parity and stroke signals are transmitted in a similar manner: key stroke count parity signals are supplied on line 192 to one portion of multiplexer 172 and stroke signals, generated by the monitor, are transmitted from line 40 to like sections of both multiplexers 68 and 172. As before, keyboard parity signals arriving on line 11 6 and keyboard strobe signals arriving on line 118 are fed to the 1 CO and 2C0 inputs of multiplexer 68, being passed straight through to multiplexer 172 when the multiplexer 68 is not activated.

The principles of the method and/or apparatus taught by the invention have obvious utility beyond the gathering of "time and motion" data to which they have been applied in this specification. Thus data other than response time or key stroke counts can be inserted, by connection to an encoder which translates it into numerical form and makes it available for connection into the buffer by a switch at an appropriate time. Also, the number of inputs coded need not be limited to the two shown in Fig. 8, but can be expanded to a much larger number.

Still further flexibility in system operation can be realized by utilizing the principles of the invention set forth above. For example, in some circumstances, generation of monitoring data in excess of the capacity of the display buffer might cause "wrap-around" whereby return of the buffer pointer to the beginning of the screen buffer can result in an attempt to enter data in a restricted field, causing the screen to lock, or in overlay and destruction of previously entered data. By means of a gate circuit like that connected to the keystroke counter of Fig. 6, a predetermined threshold count in the keystroke counter can effect delay of generation of the keyboard strobe signal and prevent entry of data until the next cycle.

In the preceding description the invention was described as it can be applied to a type 3277 Interactive Terminal, manufactured by the International Business Machines Corporation. In that terminal, information is encoded by the keyboard into a EBCDIC code for transmission to the display. In the system employed in that terminal, the electric signals representing the coded data are present at the output from the keyboard until another key is depressed. When such a system is used, transfer of coded data into the display is initiated by a strobe pulse generated simultaneously with the coded data by each keystroke; this is the process described in connection with Figs. 1-8 above.

With other systems, such as may be used in terminals where the display polls the keyboard or where a microprocessor using an interrupt structure is employed, a "handshake" procedure is used to bring about the data transfer. In such cases the strobe signal generated by the keyboard does not directly bring about the transfer of data. Instead, it either arms a circuit in the display which responds to a polling operation or it generates an interrupt within the display circuitry.

The strobe generated by the keyboard signal is sometimes known as a "data ready flag", an ''interrupt request", or a "data available signal". In the following, the term "data available strobe" will be used. After receipt, then of a data available strobe in the display, actual transfer of data to the display takes place when the display sends a handshake signal, hereinafter called a "data acknowledge" strobe, to the keyboard which requests transfer of the data.

In the embodiment of Fig. 9, the circuit of Fig. 3 is modified for use in a terminal which utilizes a data acknowledge strobe between the display and keyboard to initiate the data transfer. The strobe signal, generated when a key in keyboard 2 is depressed, is forwarded from the keyboard on via line 118 and switch 68, as before, but it is sent to the key-board as a data available strobe. In Fig. 9, provision is made for strobing the data from previously described electronic switches 60 to 68 of the monitor unit into the display when a data acknowledge strobe is received from the display; i.e., the reading out of the signals from the switches is enabled by the data acknowledge signal.

The "data acknowledge" signal, the "handshake" from the display is returned to the monitor unit in Fig. 9 by means of connecting line 152 to which switch control terminals S1 and S2 of all switches 60, 62, 64, 66 and 68 are connected in parallel. (These terminals were grounded in the circuit of Fig. 3 and, therefore, did not control switch action). Now when line 152 goes high, switches 60, 62, 64, 66, and 68 are inhibited and data from counters 70, 62, and 74 will not be read out to the display.When the data acknowledge signal causes line 152 to go low, however, the S1 and S2 terminals are, in effect, grounded, and readout of data from counters 70, 72, and 74 under control of the switch control signals applied to terminals SA and 5B of the switches is enabled and occurs in the same way as discussed in the description of Fig.

3 above.

There has been illustrated in the foregoing a system which is widely adaptable to a variety of computers and which, because it is intimately associated in its concept and function with the operating mode of a computer terminal, is well insulated from revisions of computer protocol such as frequently occur in large systems. Since anything that is done by way of changing operating mode and protocol of a computer must take into account the characteristics of the terminal, revisions in the computer operating system, which with other types of monitoring systems would necessitate revision of the mode of operation of the monitor, do not affect the present invention.

It will be apparent to those skilled in the art that the measurement of computer operation, process or transaction time, as described above, includes any time delays introduced by the central processing unit, any associated teleprocessing controller attached to the computer, moderns or other signal conditioning devices in the communication link, the communications link itself, and any circuitry, device, controller, or distributed processor in line with the communications path to and from the terminal.

It will also be apparent that the principles of the invention, as illustrated in the present embodiment in connection with a particular Interactive Terminal in a computer, can be utilized with a variety of input and output units, either with the computer described above or with other computers, by utilizing process related, or other signals passing between the computer and terminal to activate the circuitry and to translate measurement or other signals into coded data in a format which is compatible with that already in use for communicating between an existing terminal keyboard or other input and display. Therefore, the below appended claims should be construed in keeping with the spirit of the invention, rather than limited to the illustrative embodiment described above.

Claims (44)

1. A system for measuring and for indicating, independently of the programming of a computer, at least one of the time required for the computer to carry out an operation and the time between sequential operations thereof, the system comprising: (a) means for furnishing clock pulses; (b) means for sensing the initiation of computer operation; (c) means for sensing completion of the computer operation;; (d) means for accumulating at least one of (i) the clock pulses between the initiation and completion of the computer operation to determine the time required for the operation, and (ii) the clock pulses between the completion of the computer operation as determined by the completion sensing means and the initiation of the next succeeding computer operation as determined by the initiation sensing means to determine the time between sequential operations of the computer and (e) means for indicating the accumulation of clock pulses as a measurement of at least one of the time of an operation of the computer and the time between sequential operations of the computer.

2. A system in accordance with claim 1 in which the means for sensing the initiation of a computer operation comprises means for sensing the introduction of an input signal into the computer from an input device.

3. A system in accordance with claim 2 in which the input device comprises a keyboard.

4. A system in accordance with claim 1 in which the means for sensing completion of a computer operation comprises means for sensing the output of a signal from the computer which follows the completion of any operation therein.

5. A system in accordance with claim 1 in which the means for indicating the accumulation of pulses is a counter.

6. A system in accordance with claim 1 in which the computer has a readout device and means for storing data to be read out, the system further comprising means for directing the accumulation of pulses from the accumulating means to the storing means of the computer for presentation thereof in response to a subsequent input to the computer from an input device.

7. A system in accordance with Claim 2 in which the means for sensing introduction of an input signal into the computer comprises a keyboard lock signal.

8. A system in accordance with Claim 2 in which the means for sensing introduction of an input signal into the computer comprises an identification signal.

9. A system for measuring the time required for computer operation, independent of the programming of the computer, and for reporting the required time, including: a clock pulse generator; a counter coupled to the generator for accumulating and storing clock pulses; means responsive to a control signal related to the computer processing for starting and stopping accumulation of pulses in the counter; and means for translating the count stored in the counter into time measurement signals to read out.

10. A system according to claim 9 in which the means for starting and stopping accumulation of pulses is responsive to a signal from a keyboard for starting and to a signal from the computer following processing of keyboard signals for stopping.

11. A system according to claim 9 in which the time measurement signals are translated into a visual display.

12. A system according to claim 9 in which the process control related signal is a keyboard lock signal.

13. A system according to claim 9 in which the means for starting and stopping accumulation includes gating means for starting and gating means for stopping the accumulation of pulses in the counter.

14. A system according to claim 9 in which the means for translating the stored count includes a multiple position switch for selecting an output from the keyboard or an output from the counter.

15. A system according to claim 14 in which the multiple position switch includes a multiplexer.

16. A system according to claim 14 and including means for sequencing the multiple position switch to transfer the time measurement related signals in decimal sequence.

17. A system in accordance with claim 16 in which the means for sequencing includes a counter for generating binary control signals for the multiplexer.

18. A method for measuring and for indicating, independently of the programming of a computer, at least one of the time required for the computer to carry out an operation and the time between sequential operations thereof, the method comprising the steps of: (a) furnishing clock pulses; (b) sensing the initiation of a computer operation; (c) sensing completion of the computer operation; (d) accumulating at least one of (i) the clock pulses between the initiation and completion of the computer operation to determine the time required for the operation, and (ii) the clock pulses between the completion of the computer operation and the initiation of the computer operation thereafter to determine the time between sequential operations of the computer; and (e) indicating the accumulation of pulses as a measurement of the time of an operation of the computer of the time between sequential operations of the computer.

19. A method in accordance with claim 18 in which the step of sensing the initiation of a computer operation comprises sensing the introduction of an input signal into the computer from an input device.

20. A method in accordance with claim 18 in which the step of sensing completion of a computer operation comprises sensing the output of a signal from the computer which follows the completion of any operation therein.

21. A method in accordance with claim 18 in which the computer has a readout device and means for storing data to be read out, the method further comprising the step of directing the accumulation of pulses to the storing means of the computer for presentation thereof in response to a subsequent input to the computer from an input device.

22. A system in accordance with claim 9 further including: means for reading the translated count from the counter into a computer terminal in response to a signal from the computer.

23. The system of claim 22 in which the signal is a keyboard lock signal.

24. The system of claim 22 in which the signal is an enter code.

25. The system of claim 22 in which the signal is a code generated at a computer input.

26. The system of claim 22 in which the means for reading the translated count from the counter into the computer terminal in response to a signal from the computer includes means for delaying transmission of a strobe signal to the computer.

27. Apparatus for coupling data from a number of signal inputs into a computer terminal which is connected to a computer system and which has an input arrangement adapted for receiving coded data from a data generator, as well as means for storing the coded data, comprising: one or more signal inputs, other than the data generator, from which data is to be supplied to the terminal; means coupled to at least one signal input for encoding data received thereon; and means for transferring encoded data from the encoding means into the storage means of the terminal in sequence with data from another input, in response to a control signal.

28. The apparatus of claim 27 in which the means for encoding comprises a counter.

29. The apparatus of claim 28 in which the input signal to the counter comprises pulses generated by activating one or more keys at the keyboard.

30. The apparatus of claim 28 further comprising: a pulse generator coupled to the counter via a control which is responsive to the duration of an input signal for supplying a train of pulses having a length proportional to the duration of the input signal.

31. The apparatus of claim 27 in which the control signal is a keyboard unlock signal.

32. The apparatus of claim 27 in which the control signal is an enter signal.

33. An input signal device for a computer system having a main computer and at least one terminal connected thereto, the computer system having a signal system for output data signals to be transmitted from the computer to the terminal and input data signals to be transmitted from the terminal to the computer, the terminal having means for receiving output data signals from the computer and means for transmitting input data signals to the computer and the terminal having means for generating data encoded in a predetermined data signal format, the input device comprising:: (a) means for receiving an additional information signal; (b) means for converting the additional information signal into the predetermined data signal format; (c) means for connecting the information signal converting means to the terminal for use therein or for transfer to the computer by the input data signal transmitting means of the terminal.

34. An input device in accordance with claim 33 and further comprising: the information signal converting means and the output of the data generating means being connected to the terminal in alternation.

35. An input device in accordance with Claim 34 and further comprising: means responsive to a control signal for initiating connection in alternation.

36. An input device in accordance with Claim 35 and further comprising the control signal being received from the computer.

37. An input device for a computer system having a main computer and at least one terminal connected thereto, the computer system having a predetermined data signal format for output data signals to be transmitted from the main computer to the terminal and for input data signals to be transmitted from the terminal to the main computer, the terminal having means for receiving output data signals from the main computer, means for receiving terminal input information, means for adapting the terminal input information into terminal input date signals, and means for delivering the terminal input data signals in the predetermined format to the main computer, the input device comprising:: (a) means for generating additional information for insertion into at least one of the terminal and the main computer, (b) means for conditioning the additional information into terminal input data signals, and (c) means for connecting the additional information conditioning means to the terminal for use of a terminal input data signal therefrom in at least one of the terminal and the delivering means of the terminal.

38. An input device in accordance with claim 37 in which the means for connecting the additional information conditioning means to the terminal includes means for alternately connecting the terminal input information adapting means and the input device information conditioning means.

39. An input device in accordance with claim 38 comprising: (a) a second means for generating additional information for insertion into at least one of the terminal and the main computer, (b) means for conditioning the additional information from the second means into terminal input data signals, and (c) means for presenting terminal input data signals containing terminal imput information or additional information from the first and second additional information generators to the delivery means in sequence.

40. An apparatus for inserting data into a computer terminal having a keyboard and a display, the keyboard generating a data stream in the form of a series of coded signals generated by successive key strokes comprising a data input, each keystroke also generating a data avilable strobe, and the display receiving the coded signals and the data available strobes and generating a data acknowledge strobe, comprising: a coupling unit for connecting the keyboard to the display to transmit the stream of codes signals and the data available strobes from the keyboard to the display; and switching means in the coupling unit for inserting additional input data into the data stream being transmitted in response to a readout signal and a data acknowledge strobe, the additional input data comprising at least one additional signal encoded in the same manner as signals from the keyboard, each such additional signal being accompanied by a data available strobe.

41. The apparatus of Claim 40 further comprising: means for generating the additional data from a measurement of a computer performance parameter.

42. An input device for use in a computer terminal, the terminal having an input means for converting input data into a stream of coded signals, each such coded signal being accompanied by a data available strobe, and having means for receiving the stream of coded signals and for initiating transfer of each coded signal by a data acknowledge strobe the input device comprising:: a coupling unit for connecting the input means to the receiving means to transmit the stream of coded signals from the input to the data receiver; means for converting additional input data into additional coded signals accompanied by data available strobes for insertion into the stream of coded signals being transmitted; switching means in the coupling unit for inserting the additional coded signals into the stream being fed to the receiving means in response to a readout signal and a data acknowledge strobe.

43. The apparatus of Claim 42 further comprising: means in the coupling unit coupled to the switching means for providing a measurement of computer performance as additional input data.

44. The method of inserting additional input data into a computer terminal having input means for converting input data into a stream of coded input data signals, each coded signal being accompanied by a data available strobe, and having means for receiving the stream of coded signals and for initiating transfer of each coded signal into the receiving means in response to a data available signal by transmitting a data acknowledge signal to the input means, comprising: converting additional input data into additional coded input data signals and generating a data available signal with each such coded signal; and coupling the additional coded input data signals into the stream of coded input data signals in response to a readout signals and a data acknowledge signal.