GB2052154A - Improved field-effect transistors and methods of constructing such transistors - Google Patents
Improved field-effect transistors and methods of constructing such transistors Download PDFInfo
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- GB2052154A GB2052154A GB8020981A GB8020981A GB2052154A GB 2052154 A GB2052154 A GB 2052154A GB 8020981 A GB8020981 A GB 8020981A GB 8020981 A GB8020981 A GB 8020981A GB 2052154 A GB2052154 A GB 2052154A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 150000002500 ions Chemical class 0.000 claims abstract description 34
- 238000000137 annealing Methods 0.000 claims abstract description 19
- 150000001875 compounds Chemical class 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 30
- -1 neon ions Chemical class 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 229910052754 neon Inorganic materials 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000002178 crystalline material Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 238000002955 isolation Methods 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000002808 molecular sieve Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 229910001414 potassium ion Inorganic materials 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- URGAHOPLAPQHLN-UHFFFAOYSA-N sodium aluminosilicate Chemical compound [Na+].[Al+3].[O-][Si]([O-])=O.[O-][Si]([O-])=O URGAHOPLAPQHLN-UHFFFAOYSA-N 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
Abstract
A method of making an insulated gate field-effect transistor is described in which first (12) and second (22) insulating layers are formed in semiconductor crystalline material (11) by ion implantation, the ions being such as to disrupt the crystal structure to form an amorphous insulating material or to form an insulating compound with the semiconductor material, and, if necessary, annealing, further crystalline material being grown, if necessary, after the first layer has been implanted. Source (18) and drain (19) regions are defined in the material between the first and second insulating layers, the second layer (22) providing the gate insulation, a portion of the semiconductor material (20) being doped to form the gate electrode, and metallisation (27) to form contacts for the gate and the source and drain regions is deposited. Field-effect transistors made by the method are described and circuits containing such transistors can be separated by etching down to the first layer or by regions of amorphous material. <IMAGE>
Description
SPECIFICATION
Improved field-effect transistors and methods of constructing such transistors
The present invention relates to a method of constructing field-effect transistors (FETs), particularly but not exclusively, metal oxide semiconductor transistors (MOSTs) which can be constructed as either single polarity devices or as complementary devices (CMOS) to operate in high performance integrated circuits or as discrete devices.
A type of MOST which has many advantages is one in which the source and drain regions and the region separating the source and drain regions are formed in silicon deposited on sapphire, this structure being known as. silicon on sapphire (SOS) (See "Sapphire Brings Out the Best in
CMOS" by S. Sheffield Eaton, Electronics, June
12th 1975, page 11 5). However such devices are expensive to manufacture since sapphire is required as a starting material and suffer from the disadvantage that high leakage currents flow between the source and drain because of crystal distortion at the interface where during
manufacture silicon is grown on a sapphire crystal.
According to a first aspect of the present
invention there is provided a method of
constructing a field-effect transistor comprising
implanting ions in crystalline semiconductor material to form a relatively high ion
concentration layer buried in the semiconductor
material, the ions being either of a first type which
disrupts the crystal structure of the semiconductor
material to form an amorphous first insulating layer, or of a second type which is capable of
forming an insulating compound with the semi
conductor material, the-method then including
annealing the semi-conductor material to form the
first insulating layer by reacting the ions with the semiconductor material; implanting further ions in
the semi-conductor material to form a further
relatively high ion concentration layer buried in the
semiconductor material between the surface
thereof and the first insulating layer, the ions being of either a third type which disrupts the crystal
structure of the semiconductor material to form an
amorphous second insulating layer, or of a fourth
type which is capable of forming an insulating
compound with the semiconductor material, the method then including annealing the
semiconductor material to form the second
insulating layer by reacting the further ions with
semi-conductor material, forming source and drain
regions in the semi-conductor material between the two insulating layers, defining a gate region
and a gate insulation region in the semiconductor
material above the second insulating layer and in
the second insulating layer, respectively, and
forming both a protective layer and metallisation for electrical connections.
If the thickness of semiconductor material
above the first insulating layer is insufficient to
accommodate the drain, source, gate insulation
and gate of a field-effect transistor, a layer of the same or a different crystalline semiconductor material is formed on that surface adjacent to the first insulating layer, before the implantation of ions in forming the second insulating layer. The layer of crystalline semiconductor material, formed before the second ion implantation step, is preferably grown epitaxially.
Either the third type of ion is preferably the same as the first type, or the fourth type is preferably the same as the second type, but alternatively one insulating compound and one amorphous region may be employed.
Where annealing is required to form both the first and second layers both annealing operations may, in some circumstances, be carried out at the same time.
According to a second aspect of the present invention there is provided a field-effect transistor comprising a crystalline semi-conductor substrate, a first insulating layer buried in the substrate, source and drain regions formed between a surface of the transistor and the first insulating layer, the source and drain regions being separated by a region which is of different conductivity from the source and drain regions, a second insulating layer buried beneath a gate region for the transistor, but above the region separating the source and drain regions, a protective layer of insulating material formed over the source, gate and drain regions with apertures for connections to these three regions, and metallisation forming the said connections, the first and second insulating layers having been formed either by implanting ions which form an insulating compound of the semiconductor material and annealing to form the compound, or by implanting ions which disrupt the crystalline semiconductor material to provide the insulating layers in the form of amorphous semi-conductor material.
In both first and second aspects of the invention the semi-conductor is usually silicon but other semiconductors such as germanium and gallium arsenide may be used.
The region separating the source and drain regions is of the opposite conductivity type to the source and drain regions in an enhancement FET but of the same type in a depletion FET.
Isolation between devices on the same
substrate is provided by the first insulating layer
and around the device either by conventional
means such as a back biassed PN junction; or
preferably by "air" isolation achieved by photo
engraving or alternatively by a wall of amorphous semiconductor material formed by aion implantation.
Usually the ions implanted to form the insulating layers are oxygen or nitrogen toions so that where the semiconductor material is silicon, the where theinsulating compound is silicon dioxide or
silicon nitride. Ifthe insulating layer or region oxideis
formed nitride.by theamorphous silicon the ions used to
disrupt bycrystal structure may, for example,be neo ions.
The insulating layers may each be formed by ar insulating compound or by amorphous-silicon.
Where both the layers are formed by compounds, the compounds may be the same or different, and where both are amorphous the type of ion used to disrupt the crystal structure may be the same or different.
In the method and apparatus of the invention the substrate is either N or P type with the region between the source and drain regions doped during production to produce the required type of
FET.
The dose implantations required to form the first and second insulating layers are very heavy in comparison with those required for doping to form source and drain regions, as can be seen from the specific examples given later.
An advantage of the present invention is that the gate silicon is monocrystalline giving lower resistivity than the polycrystalline silicon gate formed in the usual silicon gate process. This
results in superior properties for example in relation to switching time.
The silicon gate process mentioned above suffers from the further disadvantage that the chemical processes associated therewith contaminate the gate oxide with mobile ions such as potassium and sodium ions which are detrimental to the stable operation of the FET. In order to reduce this effect phosphorus stabilisation is used but the resulting phosphorus doped glass (that is silicon dioxide) is difficult to photo-engrave. In the present invention since the oxide is buried below the top surface during chemical processing the mobile ions do not contaminate the gate oxide. Hence yield is improved and the resulting device is of higher stability since ionic contamination has been largely eliminated.
The present invention does not suffer from disadvantages in relation to the silicon gate process since the total number of photo-engraving steps required in both processes is four. Further, the gate is "auto-registered" by a non-critical
photo-engraving process as in the silicon gate process. "Auto-registration" means that when the gate oxide is defined during photo-engraving, "windows", for doping the source and drain
regions, are laid down at the same time so that the
source and drain regions automatically "register" with the gate oxide.
Since the present invention can be applied to
either enhancement or depletion FETs (including
deep depletion FETs) and each device is isolated
from the substrate by means of the insulating layer, CMOS devices of superior performance can
be constructed on the same substrate. Briefly, an
enhancement FET is so constructed that the
source and drain regions (both of same polarity)
are separated by a region of opposite polarity. In a depletion FET, the source and drain regions (again
of same polarity) are separated by a region of
same polarity but of higher resistivity. In the
present invention, due to the isolation layer below
the device, a deep depletion FET (see the above mentioned paper by Sheffield Eaton) can be constructed on the same polarity type of silicon layer as the enhancement MOST thereby simplifying the process very considerably.
However, the threshold voltage of this deep depletion MOST is of opposite sign to that of the enhancement MOST which gives a complementary operation sometimes called pseudo complementary mode. However, the method of the invention may be used to produce true CMOS N and P enhancement devices, and devices according to the invention include true 'CMOS' enhancement devices.
A further major advantage of field-effect transistors according to the present invention is that a device having the advantages of an SOS structure is produced without the strained or polycrystalline structure leading to high leakage currents which occurs in SOS devices. The source and drain regions and the region separating the source and drain regions are formed in the present device in silicon which is part of the original crystal structure which was present before the insulating layer was formed by ion implantation
and, usually, annealing. It is this insulating layer which is equivalent to the sapphire layer and there is no strained crystal structure between this layer and the silicon above it. Hence leakage current is much reduced allowing dynamic logic circuits to be produced.As has been mentioned, more silicon is grown on the silicon layer above the insulating layer in order to make it thick enough to accommodate the source and drain regions, the gate insulation and the gate region but since silicon is then grown on silicon a monocrystalline structure can be achieved without a strained crystal structure.
Where air isolation is used, the invention allows high density of circuits since no guard ring of the type usually required in conventional bulk CMOS is needed. High yields are possible since when
using air isolation a 'mesa island' is formed in which the active device is made, the quality of the
buried dielectric layer is therefore non-critical
outside the island.
High speed devices can be produced since
nodal capacitance is low (due to dielectric
isolation and auto-registration of the gate), the
threshold voltage is low and complementary
operation is possible.
Sidewall isolation with amorphous material
prevents 'spurious' or phantom MOSTs appearing
and leads to simpler design, and the small step
height in the metallisation with this type of
isolation improves yield.
More flexible design techniques are possible
since four conductive layers exist in the device and
this is important for interconnection in Very Large
Scale Integration (VLSI) devices.
Certain embodiments of the invention will now be described by way of example with reference to
the accompanying drawings, in which:
Figure 1 is a cross-section of a portion of a
silicon substrate after the formation of a buried
oxide layer by ion implantation and annealing,
Figure 2 is a cross-section of the substrate portion of Figure 1 after a further silicon layer has been grown on the upper surface,
Figure 3 is a view of the substrate portion of
Figure 2 after a further oxide layer has been buried by ion implantation snd annealing,
Figures 4 and 5 show two stages in photoengraving a substrate portion of Figure 3 to define gate and gate oxide regions,
Figure 6 shows the substrate of Figure 4 after doping to provide source and drain regions,
Figure 7 shows a cross-section of an MOST formed by the steps illustrated in Figures 1 to 6,
Figure 8 shows the substrate of Figure 3 after
the implantation of an amorphous isolating region,
in an alternative structure,
Figure 9 shows the substrate of Figure 8 after
photo-engraving to define gate and gate oxide
regions, and doping to form source and drain regions, and
Figure 10 shows the cross-section of an MOST formed by the steps illustrated in Figures 1 to 3 and Figures 8 and 9.
The steps in the construction of an N channel enhancement MOST according to one embodiment of the invention will now be described. A P type silicon substrate is first subjected to ion implantation using known apparatus such as that described in "Electronic
Engineering" for December 1977, pages 43 to 47.
In this example oxygen ions are used but other ions such as nitrogen may be used as an alternative. High dosages of about
1.2 x 1018 cm-2 molecular oxygen ions were
implanted at an energy of 400 keV, that is effectively 200 keV for atomic oxygen with a substrate orientation of < 1111 The result of the ion implantation procedure is a
Gaussian distribution of concentration of oxygen
ions with distance from the substrate surface which reaches a peak concentration at about 0.30
to 0.80 microns from the top surface 10 of the
silicon substrate 11 (see Figure 1). - The next stage in construction is the annealing
of the substrate and this results in a layer 12 of silicon dioxide being formed where the implanted
oxygen ions combine with the silicon.Although
the Gaussian distribution extends above and
below the layer 12, it is only within this layer that
practically all silicon atoms are converted to silicon dioxide and thus an insulating layer about
0.3 to 0.5 microns in thickness is formed. Outside
the layer 12 the silicon can be regarded as
remaining unchanged.
Annealing is carried out at 000C for a minimum of fifteen minutes in oxygen-free and dry
hydrogen which is prepared by passing hydrogen
through palladium catalyst and a molecular sieve.
In addition to forming the silicon dioxide,
annealing repairs the monocrystalline structure of the silicon layer 13 above the layer 12 in Figure 1
where it is damaged due to ion bombardment.
Since the layer 13 is usually too thin (about 0.1
microns) for the construction of the gate, the drain
and the source of an MOST, an epitaxial
monocrystalline silicon layer 14 1 to 5 microns in thickness is grown on the surface 10 (see Figure
a conventional way, such as is described in the "Microelectronics Journal", Volume 9, No. 2,
pages 8 to 12. Substrates with the structure shown in Figure 1 are placed in a horizontal chemical vapour deposition in a reactor and heated vapour gas then being andpassed over the substrate. This process can be combined with the previous annealing which may be carried out in the CVD before the silane is introduced.
With higher implant energies the insulating layer 12 can be more deeply theburied, and the epitaxial growth of further silicon as described in the preceding paragraph is further silicon not required.
A further stage of ion implantation, again using
oxygen ions but using the lower energies and
dosage as for the layer 1 2, is now carried out so
that a region of high concentration of oxygen ions
that implanted into the layer 14 (which is shown in Figure 3 as including into the layer 14 13). An energy of
about 50 keV with a dose of 5 X 1017 13). atenergy of oxygen ions is expected to be suitable. Another stage ions of annealing for one hour at 11 Another nitrogen is carried out, using the same conditions
as for the carried and as a result another silicon
oxide layer 15 about 0.1 microns thick is formed
in the layer 1 5 about 14.
in the layer 14.
The device shown in Figure 3 is now photoengraved using known techniques to remove parts of layers 14 and 1 5 and provide the "mesa" structure shown in Figure 4. This structure gives "air" isolation to thedevice 4. when finished. A further photo-engraving step defines the gate region and the gate oxide by removing parts of the upper layer 14 and the gate oxide by layer 1 5 with orthe resulting outline shown in Figure layer 5. Again using known techniques, regions 1 8 and 1 9 (see Figure 6) are doped to form regions and drain regions,
respectively. At the same time the portion 20 of
the layer 14 also becomes same doped and forms the gate electrode for the MOST under
construction.Hence the region 22 of the layer 1 5 forms the insulating gate theoxide for the gate 20.
A useful description of the techniques used in integrated circuit or theprocessing is given in the book integrated User's Handbook of Integrated
Circuits" published by John Wiley of Sons.
A protective layer 23 (see Figure 7) of silicon
dioxide is now grown over the upper surface of the
whole device shown over in Figure 4using the known silox process which is described by W. Kerin and Fl. C. Heim, Journal of the Electrochemical Society,
Vol. 117, p. the 1970. After the growth of the layer 23 further photo-engraving provides wells
24, 25 and 26 which extend to the source, gate
and drain regions respectively. Metallisation is
then added regions required pattern to form
interconnections between various devices on the same substrate. This metallisation is indicated by
way substrate. of example using the designation 27.
The complete MOST is shown in section in
Figure 7; it has the is source region 18 and the drain region 19 separated by a P type silicon 18 andtheregion, with these regions isolated from the substrate 11 with these regions isolated from the substrate 11 by the insulating layer 12. The gate region 20 is insulated by the gate oxide region 22.
In an alternative method of isolating devices, ion implantation using, for example, neon or xenon ions is used to form an amorphous region 30 (see
Figure 8) surrounding those parts of the layers 14 and 15 which are to form the gate, source and drain of the device. This implantation is carried out when the region 15 has been produced, that is the device has reached the stage shown in Figure 3.
For neon a dose of about 1 x 1015 cm~2 at a typical maximum energy of about 300 keV is expected to be suitable for forming the region 30.
Photo-engraving followed by doping defines a gate region 20', gate oxide 22', a source region 1 8' and a drain region 1 9', as shown in Figure 9.
The completed device (see Figure 10) is realised after growing a thick protective layer 23' of silicon dioxide, photo-engraving to provide wells 24', 25' and 26', and metallising to form contacts 27'.
While two embodiments of the invention have been specifically described it will be clear from other possibilities mentioned in more general terms that FETs according to the invention may be constructed in other ways, have different structures and be formed from different materials.
In particular if N type silicon is used as the starting substrate, enhancement P MOSTs can be made, or both enhancement and deep depletion types (for pseudo complementary operation) can be made on the same substrate if doping is used to provide the required relatively positive and negative conduction regions. Alternatively, enhancement N and P type devices, for true complementary operation, can be made on the same substrate using two separate epitaxial process stages to produce layers of opposite conductivity types in which the two FETs are created.
Claims (16)
1. A method of constructing a field-effect transistor comprising implanting ions in crystalline semiconductor material to form a relatively high ion-concentration layer buried in the semiconductor material, the ions being either of a first type which disrupt the crystal structure of the semiconductor material to form an amorphous first insulating layer, or of a second type which is capable of forming an insulating compound with the semiconductor material, the method then including annealing the semiconductor material to form the first insulating layer by reacting the ions with the semiconductor material, implanting further ions in the semiconductor material to form a a further relatively high ion concentration layer
buried in the semiconductor material between the surface thereof and the first insulating layer, the ions being of either a third type which disrupt the crystal structure of the semiconductor material to form an amorphous second insulating layer, or of a fourth type which is capable of forming an insulating compound with the semiconductor material, the method then including annealing the semiconductor material to form the second insulating layer by reacting the further ions with semiconductor material, forming source and drain regions in the semiconductor material between the two insulating layers, defining a gate region and a gate insulation region in the semiconductor material above the second insulating layer and in the second insulating layer, respectively, and forming both a protective layer and metallisation for electrical connections.
2. A method according to Claim 1 wherein a layer of the same or a different crystalline semiconductor material is formed on that surface adjacent to the first insulating layer before the implantation of ions forming the second insulating layer:
3. A method according to Claim 1 or 2 wherein the ions implanted to form the first layer are the same as those implanted to form the second layer.
4. A method according to Claim 1, 2 or 3 wherein the ions implanted are at least one of the following types: oxygen, nitrogen and neon ions.
5. A method according to any preceding claim in which the ions implanted to form the first and second layers require that annealing is carried out to form insulating layers, wherein annealing both first and second layers is carried out at the same time.
6. A field-effect transistor comprising a crystalline semiconductor substrate, a first insulating layer buried in the substrate, source and drain regions formed between a surface of the transistor and the first insulating layer, the source and drain regions being separated by a region which is of different conductivity from the source and drain regions, a second insulating layer buried beneath a gate region for the transistor, but above the region separating the source and drain regions, a protective layer of insulating material formed over the source, gate and drain regions with apertures for connections to these three regions, and metallisation forming the said connections, the first and second insulating layers having been formed either by implanting ions which form an insulating compound of the semiconductor material and annealing to form the compound, or by implanting ions which disrupt the crystalline semiconductor material to provide the insulating layers in the form of amorphous semiconductor material.
7. A field-effect transistor according to Claim 6 wherein first and second insulating layers are formed of the same insulating compound or the same amorphous material.
8. A field-effect transistor according to Claim 6 wherein the one of the said insulating layers is formed by an insulating compound and the other one of the said insulating layers is formed by amorphous material.
9. A field-effect transistor according to any of
Claims 6, 7 or 8 wherein the substrate is formed by silicon or germanium or gallium arsenide.
10. A field-effect transistor according to any of
Claims 6 to 9 wherein the region separating the source and drain regions is either of opposite polarity to, or is of the same polarity but higher resistivity than, the source and drain regions.
1 1. A circuit comprising a plurality of fieldeffect transistors each according to any of Claims 6 to 10 wherein insulation between the said transistors is achieved by engraving down to the said first layer.
12. A circuit comprising a plurality of field- effect transistors each according to any of Claims 6 to 10 wherein insulation between the said transistors comprises regions of amorphous
material.
13. A method of making a field-effect transistor
as hereinbefore described with reference to Figures 1 to 7 of the accompanying drawings.
14. A method of making afield-effect transistor as hereinbefore described with reference to
Figures 1 to 3 and 8 to 10 of the accompanying drawings.
15. A field-effect transistor as hereinbefore described with reference to, and as shown in, Figure 7 of the accompanying drawings.
16. A orthefield-effect transistor as hereinbefore described with reference to, and as shown in, Figure 10 of the accompanying drawings.
Figure 107. A circuitaccompanying apluralityoffield- effect transistors according to Claim 1 5 or 16.
effect transistors according to Claim 15 or 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8020981A GB2052154B (en) | 1979-07-04 | 1980-06-26 | Field-effect transistors and methods of constructing such transistors |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7923235 | 1979-07-04 | ||
| GB8020981A GB2052154B (en) | 1979-07-04 | 1980-06-26 | Field-effect transistors and methods of constructing such transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2052154A true GB2052154A (en) | 1981-01-21 |
| GB2052154B GB2052154B (en) | 1983-11-02 |
Family
ID=26272061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8020981A Expired GB2052154B (en) | 1979-07-04 | 1980-06-26 | Field-effect transistors and methods of constructing such transistors |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2052154B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0301223A2 (en) * | 1987-07-31 | 1989-02-01 | Motorola Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
| EP0442144A2 (en) * | 1990-02-16 | 1991-08-21 | Hughes Aircraft Company | Manufacturing high speed low leakage radiation hardened CMOS/SOI devices |
-
1980
- 1980-06-26 GB GB8020981A patent/GB2052154B/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0301223A2 (en) * | 1987-07-31 | 1989-02-01 | Motorola Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
| EP0301223A3 (en) * | 1987-07-31 | 1990-07-04 | Motorola Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
| EP0442144A2 (en) * | 1990-02-16 | 1991-08-21 | Hughes Aircraft Company | Manufacturing high speed low leakage radiation hardened CMOS/SOI devices |
| EP0442144A3 (en) * | 1990-02-16 | 1992-08-05 | Hughes Aircraft Company | Manufacturing high speed low leakage radiation hardened cmos/soi devices |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2052154B (en) | 1983-11-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |