GB2050738A - Switching inductive loads - Google Patents

Abstract

A transistor switching circuit for switching current from a d.c. supply to an inductive load ZL comprises a switching transistor T in series with the load and a series connected diode D1 and capacitor C1 connected across the transistor in order to absorb the inductive energy of the load during transistor off periods. When the transistor T switches on, the charge stored in capacitor C1 is transferred, via a diode D3, to a capacitor C2 whereafter it is transferred back into the d.c. supply via diode D4 which becomes forward biassed during the succeeding transistor off period. In a further embodiment, energy stored in capacitor C2 is transferred to a base drive power supply for transistor T, rather than back to the d.c. supply. <IMAGE>

Description

SPECIFICATION Improvements in electrical switching circuits using transistors This invention relates to electrical switching circuits using transistors, for example such as are used to provide a chopped d.c. supply or a pulse width modulated a.c. supply to a load.

Transistors used in switching circuits must operate within a set operating area, prescribed by the manufacturer for each device. Figure 1 of the accompanying drawings is a graph of collector current lc against collector/emitter voltage VCE for a typical switching transistor in which the safe operating area is defined by the curve ABCDE. The transistor must operate within the boundary OABCDEO during the turn-off period. Also shown on the graph of Figure 1 is the "worst case" resistive load line R max extending between 1cmax and VcEmax. It will be seen that, even when operating at these maximum limits, the resistive load line is well within the safe operating area.The effect of a partially inductive load is illustrated in Figure 1 by the load line R max + L from which it will be seen that the addition of inductance into the load circuit causes the load line to curve towards the limit of safe operation defined by curve ABCDE.

When the load is purely inductive the locus of 1coax and VCEmax will extend outside the safe operating area, as shown by the load line L. When the transistor is operated in switching mode it can be destroyed by internal secondary breakdown effect during the transistor turn-off period, due to the simultaneous presence of high collector current and high collector voltage. Hence if the transistor is to be used to switch current to a load which is largely or purely inductive, the transistor must be operated at a lower current or voltage, thus limiting the useful power handling capabilities of the transistor.

A known circuit for overcoming this problem is shown in Figure 2 of the accompanying drawings. In Figure 2 there is shown a switching transistor T which switches current to an inductive load ZL from a d.c. supply (not shown). A freewheel diode D2 is connected across the load to absorb the energy due to the self-inductance of the load during the transistor "off" periods. A diode D1 and series connected capacitor C1 are connected across the transistor and a resistor R1 is connected in parallel with diode D1.

The circuit operates as follows: during the period when transistor T is turned off, the collector/emitter voltage (VCE) of the transistor is prevented from rising rapidly due to capacitor C1.

Capacitor C1 is chosen such that, at the peak value of load current 1, to be switched off, the rate of rise of collector voltage is limited to such a value that, when transistor T switches off, the load current 1L flows through the series-connected capacitor C1 and diode D1 instead of through transistorT, thereby reducing the turn-off transient power dissipation in transistor T to a safe level. Load current, instead of flowing through the transistor, flows through diode D1 to charge the capacitor C1. This keeps the effective load line within the safe operating area, thus allowing full utilisation of the transistors capability.

When the transistor turns on again, the capacitor C1 discharges through the resistor R1 at a rate determined by the time constant Fl Cl. For correct operation of the circuit, this time constant must be such that capacitor C1 has discharged before the transistor turns off again.

It will be seen that all of the energy diverted from the load ZL into capacitor C1 during the turnoff period is dissipated as heat in resistor R1 and, to a lesser extent, in the transistor during its on periods. Thus the circuit shown in Figure 2 is inherently inefficient and is really only suitable for low power switching applications. This becomes a particularly serious problem at high switching frequencies.

A further disadvantage is that the discharge current flowing through transistor T is at its peak value immediately after switch-on, at a time when the base-drive of transistor T is being starved. This results in transistor T coming out of the saturated condition needed for efficient switching, thus giving a considerable increase in power loss within the transistor. Hence the overall efficiency is further reduced and so is the transistor utilisation due to thermal effects.

The present invention seeks to provide a circuit giving the same protective function as the known circuit, whilst recovering at least some of the energy stored in the capacitor C1.

According to the invention there is provided a transistor switching circuit for switching current from a d.c. supply to an inductive load, said circuit comprising a switching transistor connected in series with the load, first storage means for receiving inductive energy from the load during transistor off periods, second storage means for receiving energy from the first storage means during transistor on periods, and means for transferring the energy stored by t'ne second storage device either back into the d.c. supply or into the base drive power supply of the switching transistor.

The base drive power supply of the switching transistor is used to supply to the transistor base a pulse waveform which is operable to switch the transistor on and off in order to supply a chopped circuit to the load.

A typical sequence of events could thus be as follows:-- transistor switches off and energy is diverted from the load to capacitor C1; transistor switches on, and capacitor C1 discharges into said further capacitor; transistor switches off again and capacitor C1 begins to charge again as aforesaid.

Also, the further capacitor is discharged into the d.c. supply or into the transistor base drive power supply, as appropriate.

In an embodiment of the invention said further capacitor is connected so that, above a certain level of charge of capacitor C1, the energy of the load is additionally diverted, during transistor "off" periods, directly through the further capacitor and back into the d.c. supply. This feature provides a more effective load current diversion than the known circuit of Figure 2.

In order that the invention may be better understood, two embodiments thereof will now be described by way of example only and with reference to Figures 3 and 4 of the accompanying drawings in which: Figure 3 is a circuit diagram of a first embodiment of a transistor switching circuit according to the present invention; and Figure 4 is a circuit diagram of a second embodiment of a transistor switching circuit according to the present invention.

The reference numerals used in Figures 3 and 4 are, where appropriate, identical with those of Figure 2.

Referring to Figure 3, the discharge resistor R1 of Figure 2 is replaced by a further capacitor C2, of greater value than capacitor C1, together with diodes3, D4, D5, resistor R2 and inductor L1, connected as shown.

In order to explain operation of the circuit it is first assumed that both the capacitors C1 and C2 are fully discharged and that the transistor T is conducting. The first time that the transistor turns off, the circuit will operate in the same manner as that described above in relation to Figure 2. In other words, capacitor C1 charges up through diode Dl thus preventing a sudden rise of collector/emitter voltage. No current flows in the circuit comprising capacitor C2 since diode D3 is reverse biased.

When the transistor next turns on, capacitor C1 discharges via diode D3, now forward biassed, and inductor L1 into capacitor C2. During this time, diodes D1, D and D5 are all reverse biassed.

The combination of diode D3 and inductor L1 in the discharge path of capacitor C1 ensures that the stored energy in capacitor C1 is completely removed and transferred to capacitor C2 The value of inductor L1 is selected so as to limit the transistor collector current to a safe value. The time constant of capacitor C1 and irductor L1 must be such that the capacitor C1 is discharged before the transistor turns off again.

As soon as the capacitor C1 has discharged the voltage on the anode of diode D3 becomes zero.

The diode D3, previously forward biassed suddenly sees a reverse bias voltage equal to the difference between the voltages on capacitors C1 and C2. The diode D3 thus reverts to its blocking condition, but in so doing a reverse current spike is caused to flow in inductor L1. The diode D5 provides a conduction path for this current to the positive rail of the d.c. supply. The current spike decays very rapidly, however, due to the large potential difference across inductor Ll. The resistor R2 is connected across the inductor L1 to damp out oscillatory currents generated by the recovery of diode D5.

The circuit is now in its quiescentstate, where it remains until the transistor next switches off. At the time of the next switch off, the circuit conditions can thus be summarised as follows: 1) All diodes non-conducting; 2) Capacitor C1 discharged; 3) Capacitor C2 charged; 4) Inductor L1--zero current; 5) Transistor collector current lc equal to load current; VCE approximately equal to Vc SAT The value of capacitor C2 is chosen such that, when charged, its terminal voltage is some value less than the d.c. supply voltage. For convenience of description, it will be assumed that the terminal voltage of capacitor C2 is, in the quiescent condition of the circuit, half that of the supply.

At the next switch off of the transistor load current is diverted through diode Dl, which becomes forward biassed again, to charge capacitor Cl. The collector/emitter voltage of the transistor thus starts to rise. When the collector/emitter rises to greater than half the d.c.

supply voltage, diode D4 becomes forward biassed.

Thereafter, as the collector/emitter voltage rises still further, some of the load current can flow along the path comprising capacitor C2 and diode D4 back to the positive supply rail. Hence as the transistor load line approaches the curve defining the safe operating area (curve BCD) the load current is diverted into two paths, one consisting of diode D1 and capacitor C1, and one consisting of diode D4 and capacitor C2, thus more effectively sinking the load current than the known circuit of Figure 2. As the capacitor C2 discharges to the positive supply rail, its stored energy (i.e. the energy transferred from capacitor C1 during the previous turn-off period) is recovered, thus giving high efficiency.

By the end of the turn-off period the capacitor C1 is charged and capacitor C2 is discharged awaiting the next transistor turn on to re-establish the quiescent condition.

A second embodiment of the invention will now be described with reference to Figure 4.

In the circuit of Figure 4, load current 1, is diverted during transistor off periods to the series circuit capacitor Cl - diode D1 -- capacitor C2.

When the transistor turns off, its collector voltage will be driven rapidly towards +VDC by the load inductance Z,. However, the circuit C1, D1, C2 has a low impedance under these conditions and the load current 1, flows preferentially through this circuit during the transistion of transistor T collector voltage from VICE SAT to +VDC, ensuring that there is minimal power dissipation in the transistor during the turn-off period. Although the capacitor C2 is also in the divert path, this capacitor is so large in value

(approx. ] 2 C C1) that it does not charge significantly during the turn-off (i.e. divert period. A series-connected diode D3 and inductor L2 in parallel with diode D1 and capacitor C2 form the discharge path for capacitor C1 during turn-on of transistor T.

Inductor L2 acts to limit the peak collector current during transistor turn-on. A resistor RD in parallel with inductor L2 acts as a damping resistor for inductor L2 to prevent the occurrence of highfrequency oscillations. Inductor L3 and capacitor C3 act as a smoothing network for a driver power supply 20, as will be explained below.

Operation of the circuit will now be explained.

Transistor T is assumed to be initially on (i.e.

VCE - VCE SAT) with its collector current equal to load current 1,. Capacitor C1 and C2 are assumed to be not charged.

When transistor T turns off, its collector voltage starts to rise, and load current flows into capacitor C1 to thus charge same. As soon as the collector voltage of transistor T attempts to exceed +VDC, diode D2 becomes forward biassed, clamping the collector voltage to +VDC. At this point capacitor C1 is charged to VDC- Next time the transistor is turned on by the driver supply 10 its collector voltage will rapidly switch from VDC to approx. VICE SAT and its collector current will rise rapidly to 1,. At this point capacitor C1 will commence to discharge via the circuit T1, L2, D3, C1.

The discharge current is a single pulse of quarter sine wave shape whose duration, t, is given by

and whose peak value is given by:

This current pulse adds to the transistor collector current, reaching its peak value at time t after turn on.

During C1 discharge period diode D1 diode is driven more negative than the DC negative supply line and diode D1 therefore becomes reverse biassed.

At the point where the discharge current reaches its peak value there will be no charge on capacitor C1 and all of its stored energy will have been transferred to inductor L2. After this point the current in inductor L2 must find a current path and the anode of D1 is therefore driven positive relative to the DC negative supply line.Diode D1 conducts and capacitors C1 and C2 charge in parallel (C1 now charging in reverse). inductor L1 empties all of its stored energy into capacitor C2 (that stored in capacitor C1 being negligible in comparison, see above) and as soon as the current in inductor L2 reaches zero the energy recovery circuit is in a state of equilibriurn, capacitor C2 containing the energy originally stored in capacitor Cm, but at a much lower voltage.

Inductor L3 is chosen to have a large enough value to transport the energy from capacitor C2 into the driver power supply at a substantially constant current Hence capacitor C2 voltage falls linearly towards zero, in readiness for the next influx of recovered energy.

The benefits of the Figure 4 arrangement are that: 1. Energy which would have been wasted every time that the power transistor turned on is used for base drive instead, improving the efficiency of the switch-mode system and 2. The time delay introduced into the divert capacitor (C1 ) discharge current pulse results in a considerable reduction in the switching transistor (T) power dissipation during the discharge period, compared with a resistive discharge method. This produces a further increase in switch-mode system efficiency.

Claims (10)

1. A transistor switching circuit for switching current from a d.c. supply to an inductive load, said circuit comprising a switching transistor connected in series with the load, first storage means for receiving inductive energy from the load during transistor off periods, second storage means for receiving energy from the first storage means during transistor on periods, and means for transferring the energy stored by the second storage device either back into the d.c. supply or into the base drive power supply of the switching transistor.

2. A transistor switching circuit as claimed in claim 1 wherein said first and second storage means respectively comprise first and second capacitors.

3. A transistor switching circuit as claimed in claim 2 wherein the capacitance of said second capacitor is greater than that of said first capacitor.

4. A transistor switching circuit as claimed in either one of claims 2 or 3 wherein said first capacitor is connected in series with a first diode across the switching transistor and wherein said second capacitor is connected to the junction between the first capacitor and first diode via a second diode, and wherein means are provided for biassing said second diode off during transistor off periods.

5. A transistor switching circuit as claimed in claim 4 further including means for detecting the level of charge of said second storage means, and means for directing, above a predetermined level of charge of said second storage means, at least part of the energy of the load, during transistor off periods, directly through said second storage means and back into the d.c. supply.

6. A transistor switching circuit as claimed in claim 5 wherein the value of said second capacitor is such that, when fully charged, its terminal voltage is a predetermined value less than that of the d.c. supply and wherein one side of said second capacitor is connected to receive current from the load, and the other side of said second capacitor is connected, via a third diode, to the d.c.

supply, the arrangement being such that, as the potential at said one side of the second capacitor rises above said predetermined value, said third diode becomes forward biassed and allows energy to be transferred from said second capacitor back into the d.c. supply.

7. A transistor switching circuit as claimed in either one of claims 2 or 3 wherein said first capacitor is connected in series with a first diode, which diode is itself connected in series with said second capacitor, the series circuit of the first and second capacitors and first diode being connected across said transistor, and wherein a second diode is connected across the series combination of said first diode and second capacitor, the arrangement being such that during transistor on periods, said first capacitor discharges through the transistor and said first and second diodes into the second capacitor.

8. A transistor switching circuit as claimed in claim 7 wherein an inductor is connected in series with said second diode across the series combination of the first diode and second capacitor.

9. A transistor switching circuit as claimed in any one of claims 2, 3, 7 or 8 wherein said transferring means includes a smoothing network connected across said second capacitor to provide a substantially constant current output from the varying voltage across said second capacitor, the output of said smoothing network being passed to the base drive power supply.

10. A transistor switching circuit substantially as hereinbefore described with reference to Figure 3 or.Figure 4 of the accompanying drawings.