GB2050100A - Integrated output amplifier stage - Google Patents

Abstract

An integrated amplifier output stage is of the kind in which a pair of output transistors (T1, T2) connected across a power supply drive an output terminal (1) in push-pull when a signal is applied to an input terminal (4). The output transistors are biased by means of a biasing circuit (D3, D4, D5) fed from a constant current source (5, D6, T6, T7). In order that the output current (I0) of the current source can be chosen just sufficient to fully drive the first output transistor (T1) when the voltage at its emitter becomes limited by the supply voltage (+ VB), thereby reducing the high-frequency distortion produced when this situation occurs, the current gain from the current source to the first output transistor (T1) is made independent of the current gain of the first transistor by including a diode-connected transistor (D1) in parallel with the base-emitter junction of the first transistor. The maximum current fed to the base of the first transistor (T1) is made independent of the current gain of a driver transistor (T3) by constructing a resistor (5) included in the current source as a buried resistor having the same structure as the base region of the driver transistor (T3). As an alternative to the buried resistor 5 a further diode-connected transistor (not shown) may be included across the base-emitter junction of the driver transistor (T3). As a further alternative the driver transistor (T3) and the transistor structure (D1) may be omitted and the base of the first transistor (T1) may be connected directly to the output of the current source. <IMAGE>

Description

SPECIFICATION Integrated output amplifier stage The invention relates to an output-amplifier stage which is constructed as an integrated circuit and which has first and second power supply terminals and an output terminal, said stage comprising a first output transistor whose emitter is connected to the output terminal and whose collector is connected to the first power supply terminal, a second output transistor whose main current path is included between the output terminal and the second power supply terminal, a biasing circuit an output of which is d.c.-coupled to the base electrode of the first transistor, and a constant current source an output of which is connected to the biasing circuit for supplying direct current thereto, which current source is included between the biasing circuit and the first power supply terminal.

One known such integrated output amplifier stage is disclosed in United States Patent Specification 4,078,207.

In contradistinction to correctly designed output amplifier stages using discrete components it is found that integrated output amplifier stages, when overdriven, are liable to give rise to such distortion that high-frequency interference is produced. If such output amplifier stages are used in radio receivers this interference may be transmitted back to the input of the amplifier via a built-in ferrite aerial.

It has now been recognised that this property of integrated amplifier output stages is due to the fact that current gain factors of transistors in integrated amplifiers are subject to a substantial spread. Each value of base current for the first transistor in an output amplifier stage of the kind defined in the first paragraph normally results from a corresponding portion of the output current of said current source being fed to the d.c.-coupling.

Said base current increases with increasing transistor output current and the corresponding portion of the output current of the current source may become equal to the total current produced by said current source when a specific transistor output current is reached.

The output stage should be designed so that the output current of the first transistor when all the current from the current source is fed into the d.c.-coupling is sufficient to allow a load to be driven to the point at which the output voltage of the first transistor is limited by the supply voltage. In the interests of minimising the dissipation in the circuit the output current of the current source should, however, not be greater than that which is necessary to allow this drive point to be reached. The optimum situation is that in which the output voltage of the first transistor becomes limited by the supply voltage just at the instant when its base current results from the total output current from said current source being fed to the d.c.-coupling.In practice it is found that this optimum setting cannot be attained with conventional integrated amplifiers, because allowance has to be made in the design for spreads in the current gain factor of the first transistor, more specifically for the situation when said gain factor has its smallest possible value. Moreover, if the d.c.-coupline includes a further transistor, for example in Darlington configuration with the first transistor, allowance has to be made in fact for the smallest possible value of the product of the current gain factors of these two transistors which is likely to occur in the integraton process used, in order to ensure that the maximum rated output power can be obtained.

As a result of this the output current of the current source has to be set to a value which is sometimes a factor of four too high or, if a Darlington arrangement is used, even a factor of sixteen too high, so that when the output volgage of the first transistor becomes limited by the supply voltage the current fed by the current source into the d.c.-coupling is still not its total output current. At maximum drive the output voltage of the first transistor is therefore limited in such circumstances much more abruptly than would have been the case if the setting of the current source had been the optimum, as a result of which the distortion of the output signal which accompanies this limitation contains far more and stronger high-frequency components than would have been the case if the setting of the current source had been the optimum.

It is an object of the invention to mitigate these disadvantages.

According to one aspect the invention provides an output amplifier stage which is constructed as an integrated circuit and which has first and second power supply terminals and an output terminal, said stage comprising a first output transistor whose emitter is connected to the output terminal and whose collector is connected to the first power supply terminal, a second output transistor whose main current path is included between the output terminal and the second power supply terminal, a biasing circuit an output of which is d.c.-coupled to the base electrode of the first transistor, and a constant current source an output of which is connected to the biasing circuit for supplying direct current thereto, which current source is included between the biasing circuit and the first power supply terminal, characterised in that a semiconductor junction is included in parallel with the base-emitter junction of the first transistor, or in parallel with the base-emitter junction of a further transistor (if present) included in the d.c.-coupling, with such a sense that it has the same forward direction as has the base emitter junction of the first transistor or the further transistor, so that the current gain factor of the combination of the first or further transistor and the semiconductor junction will be substantially equal to the ratio of the effective emitter area of said first or further transistor to the effective area of said semiconductor junction said ratio being smaller than the current gain factor of the first or further transistor alone.

The combination of the first or further transistor and the semiconductor junction (which in practice will normally be constituted by a diode-connected transistor, i.e. a transistor with short-circuited collector-base junction), constitutes a current mirror whose current gain factor is determined by a ratio of areas.

As in integrated circuits area ratios need be subject to hardly any spread, the provision of such a current mirror enables the output current of the current source to be selected substantially closer to the optimum setting.

The fact that the current mirror should have a current gain factor which is substantially greater than unity need present no problem, if the semiconductor junction is connected in parallel with the base-emitter junction of the first transistor, because the first transistor will normally occupy a large area in the integrated circuit in any case, for reasons of power.

The provision of such a current mirror can have an additional effect which enables the afore-said interference to be reduced still further. It is found that the internal base resistance of the first transistor can give rise to a significant voltage loss at large base currents.

As a result of this voltage loss the current gain factor of the current mirror may decrease when high output currents occur (if the semiconductor junction is connected in parallel with the bse-emitter junction of the first transistor), which can have a favourable effect on the said distortion.

If the semiconductor junction is included in parallel with the base-emitter junction of the first transistor, and if the base-emitter junction of a third transistor, which is connected to form a Darlington arrangement with the first transistor, is included between the biasing circuit and the base electrode of the first transistor a second semiconductor junction may be included in parallel with the baseemitter junction of the third transistor with such a sense that it has the same forward direction as has the base-emitter junction of the third transistor, so that the current gain factor of the combination of the third transistor and the second semiconductor junction will be substantially equal to the ratio of the effective emitter area of said third transistor to the effective area of said second semiconductor junction, said ratio being substantially greater than unity but smaller than the current gain factor of the third transistor alone.

As an alternative to this, the current source may include a buried resistor and means for applying a fixed voltage across said buried resistor, the buried resistor being included in the current source in such manner that the output current of the current source will be inversely proportional to the resistance of the buried resistor, said buried resistor being constituted by a diffused zone of the same type as a diffused zone which forms the base region of the third transistor, a diffused zone of the same type as a diffused zone which forms the emitter region of the third transistor being provided over the diffused zone which constitutes the buried resistor.

The resistance of said buried resistor, is likely to vary due to manufacturing process variations in the same way as does the current gain factor of the third transistor. Thus the value of this resistance is likely to be inversely proportional to the current gain factor of the third transistor, so that variations in said current gain factor will be compensated for.

However, this form of compensation can only be used to compensate for gain-factor process variations with respect to one transistor.

According to another aspect the invention provides an output amplifier stage which is constructed as an integrated circuit and which has first and second power supply terminals and an output terminal, said stage comprising a first output transistor whose emitter is connected to the output terminal and whose collector is connected to the first power supply terminal, a second output transistor whose main current path is included between the output terminal and the second power supply terminal, a biasing circuit an output of which is d.c.-coupled to the base electrode of the first transistor, and a constant current source an output of which is connected to the biasing circuit for supplying direct current thereto, which current source is included between the biasing circuit and the first power supply terminal, characterized in that the current source includes a buried resistor and means for applying a fixed voltage across said buried resistor, the buried resistor being included in the current source in such manner that the output current of the current source will be inversely proportional to the resistance of said buried resistor, said buried resistor being constituted by a diffused zone of the same type as a diffused zone which forms the base region of the first transistor, a diffused zone of the same type as a diffused zone which forms the emitter region of the first transistor being provided over the diffused zone which constitutes the buried resistor.

Embodiments of the invention will be described, by way of example, with reference to the accompanying diagrammatic drawing, in which: Figure 1 shows a first embodiment, Figure 2 shows a second embodiment, and Figure 3 schematically represents how part of the embodiment of Fig. 2 can be constructed in practice.

Fig. 1 shows the circuit diagram of an output amplifier stage integrated on a single semiconductor chip. The stage includes a first output transistor T1, whose collector electrode is connected to a terminal + V5 for a positive supply voltage and whose emitter electrode is connected to an output terminal 1. The base electrode of the transistor T, is connected to the emitter electrode of a transistor T3, the two transistors T3, T, forming a Darlington arrangement. A bias constant current source 3, which carries a current lo, is included between the base electrode of transistor T3 and the power supply terminal + VB.

In the present example the output stage is a so-called "quasi-complementary" output stage, the output terminal 1 being connected to a power supply terminal - V5 for a negative supply voltage via the main current path of an npn-transistor T2. The base electrode of transistor T2 is connected to the collector electrode of a pnp-transistor T4, whose emitter electrode is connected to output terminal 1. In the present example the output stage is biased by including three diodes D3, D4 and D5 between the base electrodes of transistors T3 and T4, through which diodes quiescent current flows from the source 3. The main current path of a driver transistor T5, whose base electrode is connected to an input terminal 4, is included between the base electrode of transistor T4 and the negative power supply terminal - Vs.

If a current lu flows through the output terminal 1 to a load resistor 2 having a resistance RL, this current being a function of the drive on input 4, the maximum possible value I of current lu is given by V5 1um,x RL If the maximum output power of the amplifier is specified the maximum value of the current lu will, in effect, also be specified. If the presence of diodes D, and D2 is neglected for the moment, the corresponding maximum base current 1lama, of transistor T3 is then: Ii,,a = luax/PiP3 where ss, is the current gain factor of transistor T, and P3 the current gain factor of transistor T3.

The current 1o should be sufficiently large to provide this maximum base current. As the current gain factors ss, and ss3 are subject to manufacturing tolerances in the absence of the diodes D, and D2, 1o should satisfy.

1o > lumax/Pi minP3min where Pimin and P3min are the lowest values which the current gain factors of the transistors T, and T3 can have. Thus in the absence of the diodes D, and D2 the current 1o must always be selected to be greater than necessary (the necessary value in a given case is given by 1o = lu,,,ax/PlP3, where P and ss3 are the actual values of the current gain factors), which means that, the output voltage of the transistors T, and T3 will be abruptly limited by the supply voltage when the maximum output current is reached, which event will be accompanied by considerable distortion.Accordingly the "diode" D, is included in parallel with the base-emitter junction of transistor T, and the "diode" D2 is included in parallel with the base-emitter junction of transistor T3.

In fact the "diodes" D, and D2 will normally be diode-connected transistors, i.e. transistors having their collectors connected to their bases. The current gain factor of the arrangement comprising transistors T, and T3 and diode-connected transistors D, and D2 is: lx - = n.m 1, where n is the ratio of the effective baseemitter area of transistor T3 to the effective base-emitter area of diode-connected transistor D2 and m is the ratio of the effective baseemitter area of transistor T, to the effective base-emitter area of diode-connected transistor D,. This equation for lu/l, is valid only when n and m are large compared with unity and when the base currents of transistors T, and T3 are ignored, the latter fact resulting in a requirement that n and m be chosen smaller than the current gain factors of the associated transistors T3 and T, themselves.It is obviously desirable that n and m are chosen to be substantially greater than unity, for example so that lU/I, is at least ten, in order that the amplifier stage will have a worthwhile current gain. The area ratios n and m can be realized very accurately in integrated circuits, especially when the transistors D, and D2 have similar configurations to the transistors T, and T3 respectively. As a result of this the maximum value lumax/n.m. for the current 1, and hence the value required for 1o is accurately defined and is hardly subject to any spread. n may, for example, have a value of 1 2 and m may, for example, have a value of 40---owing to the comparatively large area which is required for output transistor T,.

An additional advantage is that, as a result of the inevitable internal base resistance of transistors T, and T3, the current gain factor n.m decreases with increasing output current lu, because a voltage loss occurs across said internal base resistances. This decrease of the current gain factor n.m with increasing output current lu also has an advantageous effect on the degree of distortion with which the limitation of the output voltage of the transistors T, and T3 is accompanied.

Fig. 2 shows an alternative to the circuit arrangement of Fig. 1, diode-connected transistor D2 being omitted and constant current source 3 being constituted by a pnp-transistor Tû, whose collector electrode is connected to the base electrode of transistor T3, whose emitter electrode is connected to the positive supply terminal + V5 and whose base is connected to the collector of a current source transistor T7. A diode D6, preferably a diodeconnected transistor is included in parallel with the base-emitter junction of transistor T6.

The base electrode of transistor T7 is connected to a point of reference voltage Vref and the emitter electrode thereof is connected to the negative power supply terminal - V5 via a resistor 5 having a resistance Rb.

If the base-emitter voltage of transistor T7 is ignored, the collector current of transistor T7 is equal to Vr,,f/Rb This collector current is applied to the base electrode of transistor T3 in mirror-inverted form by means of the current mirror constituted by diode D6 and transistor T6, so that the current 1o is inversely proportional to Rb. If m is as defined previously the base current 1, of transistor T3 is: 1, = lU/ss3 so that the base current of transistor T3 is inversely proportional to the current gain factor of transistor T3 if the output current lu has a specific value.

If a buried resistor is employed for resistor 5, a diode D6 is a diode-connected transistor manufacturing process variations will have the same influence on the resistance Rb, and thus inversely on the current 10, as they do on the current gain factor ss3, and thus on the current I,. Thus the influence of process variations on the current gain factor ss3 can again be ignored when selecting the nominal strength of the current 10.

In the circuit arrangement of Fig. 1 the realisation of a sufficiently large current gain factor m (D1, T,) presents no problem because the area of transistor T, has to be large in any case in view of the required power. However, realisation of a sufficiently large current gain factor n may involve making transistor T3 larger than would otherwise be necessary. The arrangement of Fig. 2 does not suffer from this possible disadvantage because the provision of the buried resistor 5 eliminates the need to include transistor T3 in a current mirror arrangement.

Fig. 3 shows how a buried resistor may be constructed adjacent a bipolar transistor. On a substrate 6, for example of the type, an ntype epitaxial layer is formed which is divided into separate regions 8 and 1 3 by means of isolation diffusions 7, p-type diffusions 9 and 10 are formed in the regions 8 and 1 3 respectively and n-type diffusions 11 and 1 2 are formed in the diffusions 9 and 10 respectively. The region 13, the diffusion 10 and the diffusion 1 2 constitute the collector, base and emitter respectively of a bipolar npntransistor, (the transistor T3 or T, of Fig. 2).

The p-type diffusion 9 bounded by the diffusion 11 and the region 8 constitute a buried resistor (resistor 5 of Fig. 2) whose resistance is inter alia determined by the dimensions of the diffusion 11 and the distance from this diffusion to the region 8 of the epitaxial layer.

The current gain factor of said bipolar transistor depends in a similar way on the dimensions and location of the emitter diffusion 1 2 relative to the region 1 3 of the epitaxial layer.

As the buried resistor and the bipolar transistor are formed by means of the same steps in the manufacturing process, process variations will have substantially the same influence on said resistance value as they do on said current gain factor.

It will be obvious that there are many alternatives to the arrangements described.

For example, the transistor T, need not form part of a Darlington arrangement. Furthermore, the conductivity types of the transistors and diodes and the polarity of the supply voltage may be reversed. Moreover, the output stage may be of a type other than the quasi-complementary output stage shown.

It will be appreciated that compensation for variations in the current gain factor of transistor T3 by the provision of the buried resistor 5 of Fig. 5 may be provided in a similar way for variations in the current gain factor of transistor T1, if transistor T, does not form part of a Darlington arrangement. If this is the case diode-connected transistor D, of Fig. 2 may be omitted and the base of transistor T, may be connected directly to the collector of transistor T6.

It will also be appreciated that the diodeconnected transistor D, of Fig. 2 may be connected across the base-emitter junction of transistor T3 instead of across the base-emitter junction of transistor T,.

It will also be appreciated that the diodes D1, D2 and D6 of Figs. 1 and 2 may be formed by extensions to the base-emitter junctions of the corresponding transistors (T, T3 and T6 respectively), in particular by merely providing the corresponding transistor with a second collector connected to its base.

Claims (5)

1. An output amplifier stage which is constructed as an integrated circuit and which has first and second power supply terminals and an output terminal, said stage comprising a first output transistor whose emitter is connected to the output terminal and whose collector is connected to the first power supply terminal, a second output transistor whose main current path is included between the output terminal and the second power supply terminal, a biasing circuit an output of which is d.c.-coupled to the base electrode of the first transistor, and a constant current source an output of which is connected to the biasing circuit for supplying direct current thereto, which current source is included between the biasing circuit and the first power supply terminal, characterised in that a semiconductor junction is included in parallel with the base-emitter junction of the first transistor, or in parallel with the base-emitter junction of a further transistor (if present) included in the d.c.-coupling, with such a sense that it has the same forward direction as has the baseemitter junction of the first transistor or the further transistor, so that the current gain factor of the combination of the first or further transistor and the semiconductor junction will be substantially equal to the ratio of the effective emitter area of said first or further transistor to the effective area of said semiconductor junction said ratio being smaller than the current gain factor of the first or further transistor alone.

2. An output amplifier stage as claimed in Claim 1 wherein the semiconductor junction is included in parallel with the base-emitter junction of the first transistor and wherein the base-emitter junction of a third transistor, which is connected to form a Darlington arrangement with the first transistor, is included between the biasing circuit and the base electrode of the first transistor, characterised in that a second semiconductor junction is included in parallel with the base-emitter junction of the third transistor with such a sense that it has the same forward direction as has the base-emitter junction of the third transistor, so that the current gain factor of the combination of the third transistor and the second semiconductor junction will be substantially equal to the ratio of the effective emitter area of said third transistor to the effective area of said second semiconductor junction, said ratio being smaller than the current gain factor of the third transistor alone.

3. An output amplifier stage as claimed in Claim 1, wherein the semiconductor junction is included in parallel with the base-emitter junction of the first transistor and wherein the base-emitter junction of a third transistor, which is connected to form a Darlington ar rangement with the first transistor, is included between the biasing circuit and the base electrode of the first transistor, characterised in that the current source includes a buried resistor and means for applying a fixed voltage across said buried resistor, the buried resistor being included in the current source in such manner that the output current of the current source will be inversely proportional to the resistance of the buried resistor, said buried resistor being constituted by a diffused zone of the same type as a diffused zone which forms the base region of the third transistor, a diffused zone of the same type as a diffused zone which forms the emitter region of the third transistor being provided over the diffused zone which constitutes the buried resistor.

4. An output amplifier stage which is constructed as an integrated circuit and which has first and second power supply terminals and an output terminal, said stage comprising a first output transistor whose emitter is connected to the output terminal and whose collector is connected to the first power supply terminal, a second output transistor whose main current path is included between the output terminal and the second power supply terminal, a biasing circuit an output of which is d.c.-coupled to the base electrode of the first transistor, and a constant current source an output of which is connected to the biasing circuit for supplying direct current thereto, which current source is included between the biasing circuit and the first power supply terminal, characterized in that the current source includes a buried resistor and means for applying a fixed voltage across said buried resistor, the buried resistor being included in the current source in such manner that the output current of the current source will be inversely proportional to the resistance of said buried resistor, said buried resistor being constituted by a diffused zone of the same type as a diffused zone which forms the base region of the first transistor, a diffused zone of the same type as a diffused zone which forms the emitter region of the first transistor being provided over the diffused zone which constitutes the buried resistor.

5. An output ampliier stage which is constructed as an integrated circuit, substantially as described herein with reference to Fig. 1 or Fig. 2 of the drawing.