GB2045562A - Improvements in or relating to driver circuits for automatic digital testing apparatus - Google Patents

Abstract

A driver circuit for use in testing either ECL (emitter-coupled logic) or TTL (transistor-transistor logic) devices. The circuit has a pair of variable reference voltages (VH, VL) for determining the logic levels 0 and 1. The circuit also has two termination networks (8, 9) for ECL and TTL, which are selectively connected to the output of the driver circuit according to the value of one of the reference voltages (VL). Preferably the circuit is formed as a hybrid network in which transistors from the same semiconductor slice are mounted on the same ceramic substrate. <IMAGE>

Description

SPECIFICATION Improvements in or relating to driver circuits for automatic digital testing apparatus BACKGROUND OF THE INVENTION This invention relates to driver circuits for automatic digital testing apparatus.

One known form of digital test apparatus comprises a plurality of driver circuits which, in use, are connected to respective terminals of the equipment under test, so as to permit test signals to be injected into the equipment.

Some of the terminals may alternatively be used to receive response signals from the equipment under test, for comparison with the expected responses.

The equipment under test may be of a variety of different types. For example it may comprise ECL (emitter-coupled logic) or TTL (transistor-transistor logic) circuits. Different types of logic circuit generally use different voltage levels to represent the binary digits "0" and "1". Moreover, different types of logic generally also require different termination networks to be connected to terminals which receive response signals from the equipment under test.

In the past, these requirements have meant that different driver circuits have had to be provided for different types of logic. This is very expensive. The object of the present invention is therefore to provide a driver circuit which is capable of being used with more than one type of equipment.

SUMMARY OF THE INVENTION According to the invention, a driver circuit for automatic digital testing apparatus comprises a switching circuit arranged to produce a binary output signal at an output terminal, the signal having two levels representing the binary digits 0 and 1, the levels being determined by two variable reference voltages, characterised by at least two terminator circuits containing different termination networks, and a termination control circuit responsive to one of the reference voltages, for connecting one or other of the terminator circuits to the output terminal in accordance with the magnitude of that reference voltage.

Thus, the terminator circuit selected automatically in accordance with the type of logic under test, as specified by the reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS One driver circuit in accordance with the invention will now be described by way of example with reference to the accompanying drawings of which Figure 1 is an overall block diagram of the circuit; Figure 2 shows the switching circuit in more detail; Figure 3 shows the termination control circuit in more detail; and Figures 4 and 5 show TTL and ECL termination circuits respectively.

DESCRIPTION OF THE PREFERRED EMBODI MENT Referring to Fig. 1, the driver circuit comprises a switching circuit 1 which produces output signals at an output terminal 2. In use, this terminal is connected to a terminal of the equipment under test (not shown).

The switching circuit is controlled by input binary signals at an input terminal 3. These input signals may, for example, be generated by a digital computer. The input signals are fed to the switching circuit 1 by way of a level shifting circuit 4, and cause the switching circuit to be switched into a first or second state according to whether the input signal represents ''0" or "1".

The voltage levels of the output of the switching circuit are accurately controlled by two reference voltages VH and V, from external variable voltage sources 5 and 6. When the switching circuit is in its first state (corresponding to input value "0"), the output assumes the lower voltage level V,. When the switching circuit is in its second state (corresponding to input "1"), the output assumes the higher voltage level VH. The two reference voltages VH and V, may be adjusted within the range - 2 volts to + 4 volts.This permits the driver circuit to be adjusted for testing either TTL or ECL equipment as follows: V, VH TTL 0 volts + 4 volts ECL - 1.8 volts - 0.8 volts Instead of injecting a signal into the equipment under test, it may be desired to receive a response signal from the equipment and to compare it (by means of a comparator, not shown) with the expected response. For this purpose, the switching circuit 1 can be put into a "tristate" condition, by means of a control signal TRI. In this condition, the voltage at the output terminal 2 is not affected by changes of the input signal, but is determined solely by the level of the response signal from the equipment under test.

The tristate control signal TRI is also applied to a termination control circuit 7, causing it to produce one of two signals EN(TTL and EN(ECL) which respectively enable a TTL terminator circuit 8 or an ECL terminator circuit 9. Which of these two circuits is enabled depends on the magnitude of the lower reference voltage V,: when V,= 0 volts (the TTL lower logic level), the TTL terminator circuit 8 is enabled, and when V, = - 1.8 volts (the ECL lower logic level), the ECL terminator circuit 9 is enabled.

The termination control circuit 7 can be inhibited, by means of a control signal TERM, and when it is inhibited neither of the terminator circuits 8, 9 is enabled.

Referring now to Fig. 2, this shows the switching circuit 1 in more detail. The output voltage of the switching circuit is produced by an output stage consisting of a first pair of parallel-connected transistors T1 and T2, connected in series with a second pair of parallelconnected transistors T3, T4 between a power supply PS2 and a - 5.2 volt supply. The input signal from the level shifter 4 (Fig. 1) is applied to a pair of switching transistors T5, T6, arranged as a differential amplifier.

When the input signal is low, T5 is switched off, and T6 is switched on. In this state, current flows from a power supply PS1, through transistors T7 and T8 (connected as diodes), and through transistor T6, to the - 5.2 volt supply. Current also flows from the V, reference supply, through a transistor T9 (connected as a diode) and through the transistor T6. In this state, therefore, the voltage at the terminal 2 is VL - Vj9 + Vj8 + Vj7 - Vji Where Vj9 is the voltage drop across the junction of transistor T9, and so on. If all the transistors are accurately matched, the voltage drops across their junctions will all be equal, i.e.

Vj9 = Vj8 = Vj7 = Vji.

The voltage drops across the transistors will therefore cancel each other out, and the volt age at output terminal 2 will equal V,.

When the input signal from the level shifter 4 is high, transistor T6 is switched off. Cur rent therefore now flows from the power sup ply PS1 through a transistor T10 (connected as a diode) to the higher reference voltage VH.

The voltage at the output terminal is therefore equal to VH + VJ1O - VJ1 which is simply equal to VH if the transistors are accurately matched.

As shown in Fig. 2, the tristate control signal TRI is applied to one input of a comparator Ci, the other input of which is connected to an internally generated - 1.3 volt supply.

The signal TRI has two significant levels, - 0.8 volts and - 1.8 volts. When TRI = ~0.8 volts, the output from the com parator C1 is negative, and has no effect on the switching circuit. However, when TRI = - 1.8 volts, the output of the comparator C1 becomes positive, and this causes two transistors T11 and T12 to become saturated.

Saturation of T11 causes the switching transistor T6 to be turned off, while saturation of Tri 2 causes the output transistors T3, T4 to be turned off. The result is to put the switching circuit in the desired tristate condition.

Referring now to Fig. 3, the termination control circuit comprises three comparators C2-C4. The positive input of C2 receives the reference voltage V, and compares it with a D.C. threshold level of - 1.3 v. If V, is greater than - 1 .3v, the output of C2 rises to + 0.8v, while if V, is less than - 1 .3v, the output of C2 drops to - 5 v. The output of C2 provides the control signal EN(TTL) which, when positive, enables the TTL terminator circuit 8.

The output of C2 is also applied to the negative input of C3 where it is compared with the - 1.3 v threshold level. Thus, when the output of C2 rises to + 0.8 v, the output of C3 goes negative, and when the output of C2 drops to - 5 v. the output of C3 goes positive. The output of C3 is therefore, in effect, the logical inverse of the output of C2, and provides the control signal EN(ECL) which, when positive, enables the ECL terminator circuit 9.

In summary, it can be seen that when V,= O v, EN(TTL) goes positive and the TTL terminator circuit 8 is enabled, and when V,= - 1.8 v, EN(ECL) goes positive and the ECL terminator circuit 9 is enabled.

The operation of the comparators C2, C3 as described above can be overridden by the comparator C4. When the output of C4 goes negative, two transistors T13, T14, connected as diodes, become forward biased. T13 pulls the positive input voltage to C2 down to - 5 v, while T14 pulls the output of C3 down to 5v. The effect is therefore to force both the signals EN(TTL) and EN(ECL) to negative values, disabling both the terminator circuits.

The comparator C4 receives the control signals TERM and TRI at its positive and negative inputs respectively. Normally, TERM is permanently wired to the internally generated - 1 .3v. DC suupply. Hence, the output of C4 is determined by the state of the TRI signal. However, when it is desired to inhibit both the terminator circuits, TERM is connected to a - 5.2v. supply. In this case, the output of C4 is held at - 5v, irrespective of the value of TRI.

Fig. 4 shows the TTL terminator circuit 8. It consists of a switching transistor T15 and another transistor T16 connected as a diode, so as to prevent undershoot of the signal from the equipment under test, without causing any DC loading on the equipment.

Fig. 5 shows the ECL terminator circuit 9. It consists of a 750hm resistor which is switched to a - 2.4v supply by means of a transistor Tri 6.

In the driver circuit described above, it is required that the output signals should be similar to those that the equipment under test would encounter in actual operation. In particular, where the equipment under test consists of high speed circuitry, the rise and fall times of the signals should be vary small, typically of the order to a few nanoseconds.

Moreover, it is desirable that the circuit should be physically small, since a typical test apparatus normally contains a large number of driver circuits.

To meet these requirements, the circuit is preferably implemented as a hybrid network, consisting of a plurality of integrated circuit chips mounted directly on a ceramic substrate and connected by conductive tracks on the substrate. Preferably, all the chips forming the transistors are fabricated from the same area of a single silicon slice. This ensures that the characteristics of the transistors are accurately matched, as described above. Moreover, since the chips are mounted on the same ceramic substrate, they are all held within a small temperature range, so that there is little temperature variation of their characteristics.

Claims (9)

1. A driver circuit for automatic digital testing apparatus, comprising a switching circuit arranged to produce a binary output signal at an output terminal, the signal having two levels representing the binary digits 0 and 1, the levels being determined respectively by two variable reference voltages, characterised by at least two terminator circuits containing different termination networks, and a termination control circuit responsive to one of the reference voltages, for connecting one or other of the terminator circuits to the output terminal in accordance with the magnitude of that reference voltage.

2. A driver circuit according to Claim 1 wherein the output terminal is connected to the reference voltages by way of paths containing a plurality of transistors, the transistors being so arranged that, in operation, the voltage drops across their junctions cancel out, such that the voltage at the output terminal is substantially equal to one or other of the reference voltages.

3. A driver circuit according to Claim 2 wherein the transistors are all fabricated from the same area of a single silicon slice, thereby ensuring that the characteristics of the transistors are accurately matched.

4. A driver circuit according to Claim 3 wherein the transistors are all mounted on a common ceramic substrate, thereby ensuring they are all kept at substantially the same temperature.

5. A driver circuit according to any preceding claim wherein each variable reference voltage is adjustable in the range - 2 volts to + 4 volts.

6. A driver circuit according to any preceding claim wherein the terminator circuits contain networks suitable for terminating ECL and TTL devices respectively.

7. A driver circuit according to any preceding claim wherein the switching circuit is implemented as a hybrid network, consisting of a plurality of integrated circuit chips mounted directly on a ceramic substrate and connected by conductive tracks on the substrate.

8. A driver circuit according to any preceding claim further including means for placing the switching circuit in a condition in which the voltage at the output terminal is independent of the reference voltages, being determined solely by external voltages received by the terminal.

9. A driver circuit substantially as hereinbefore described with reference to the accompanying drawings.