GB2045479A - Formatting arrangement for disc memories - Google Patents

Abstract

Formatting circuitry is arranged between a disc controller and computer interface to permit formatting of the disc without the interface being unavailable during this time to other units connected to it. The formatting circuitry includes memories 80, 81 for fixed and variable codes to be recorded, registers R1-R5 containing address sector length and lay-out confirmation and a counter 82 incremented as each format item is recorded. <IMAGE>

Description

SPECIFICATION Formating arrangement for disc memories The present invention relates to digital computers and in particular, in such computers, to an arrangement for formating disc memories.

A digital computer principally comprises a central unit which is connected to peripheral units via interfaces. The peripheral units may be formed for example, by control consoles, printers, punched card readers, memories, etc. The memories, which may be magnetic tapes, magnetic discs etc., enable varous kinds of data to be recorded, this data being data to be processed or data for controlling the processing which is to be performed.

It will be appreciated that this data needs to be recorded in such a way that it can be retrieved easily and quickly. For this reason, the items of data are assigned addresses which give their location. Thus, in a disc memory, data is located by designating a face of the disc, a track on this face, and a sector along the track, each sector allowing a number of binary codes to be recorded which depends on the format adopted. To enable a given sector to be located along a track, each sector is allotted an identity code which is recorded on the track before the beginning of that part of the sector in which is recorded the data proper. Identity codes of this kind for the sectors are recorded on all the tracks before any data proper is recorded.This operation, which is termed "formating" the disc, is generally performed by means of an integrated circuit which is controlled by a microprocessor situated in the interface lying between the central unit and the peripheral units, which microprocessor is also intended to control other peripheral units. The operations of formating a track, and even more so a disc, call for a large number of actions by the microprocessor and the interface, and the time taken to perform these actions reduces by a corresponding amount the time for which the microprocessor is available to deal with the other peripheral units.

The object of the present invention is to provide a formating arrangement which enables a track on a disc to be formated without requiring the intervention of the microprocessor in the interface situated between the central unit and the peripheral units.

The present invention provides a formating arrangement for a disc memory which forms one of the peripheral units of a digital computer. The formating arrangement is arranged as a shunt between a unit for controlling the peripheral units and a circuit for controlling recording and reading in the disc memory. It is adapted to format one entire track of the disc without having to interrupt the operation of the unit for controlling the peripheral units.

The formating arrangement includes registers to receive from the unit for controlling the peripheral units codes which give formating details such as the face of the disc concerned, the track concerned, the first sector to be formated, the length of the sector, and the layout of the sectors along the track. It also includes a first memory which contains so-called fixed codes which are intended to be recorded in certain spaces along the track and a second memory which contains so-called variable codes which represent the identity codes for the sectors along a track.

These first and second memories are addressed by signals supplied by a logic circuit which receives on the one hand the codes contained in certain registers and on the other hand signals representing the decoded count in a counter which goes from one count to the next each time a fixed or variable code supplied by one of the two memories is recorded on the track concerned.

The present invention will be better understood with the help of the following description of a particular embodiment, which is given by way of example and which is shown in the accompanying drawings, in which: Figure 1 is a simplied block diagram of a computer and its peripheral units, Figure 2 is a block diagram showing the layout of the formating arrangement according to the present invention, Figure 3 is a diagram showing the various spaces along a track, Figure 4 is a block diagram of the formating arrangement according to the present invention.

In Fig. 1, a digital computer comprises a central unit 11 which is connected on the one hand to a control unit 12 and on the other to peripheral units 13, 14 and 15 via an interface 16.

Peripheral unit 15 is for example a disc memory unit, employing, for example, flexible magnetic discs 21 and 17. Unit 15 also includes two input/output units 18 and 19 which control recording on and reading from flexible discs 21 and 17 respectively and which are controlled by an adapter or matching circuit 20.

The adapter circuit 20, which is shown in greater detail in Fig. 2, comprises a control circuit 30 whose outputs are connected to the inputs of input/output circuits 18 and 19 and whose inputs are connected to the outputs of interface 16. The control circuit 30 may, for example, be formed by a commercially available integrated circuit (type 8271 made by Messrs. Intel Corporation). Similarly, other commercially available integrated circuits may be used to form the interface 16. Amongst other functions, the integrated circuits forming the control circuit and the interface are intended to be used to format the discs 21 and 17 prior to the operation of recording any data.

Using the integrated circuits in this way for formating purposes means that the interface 16 is unavailable for a fairly long time at the expense of the other peripheral units to which it is connected. Thus, in accordance with the present invention, the discs are formated by a formating arrangement which is connected as a shunt to a connecting bus 32 linking the interface 16 to the control circuit 30. Also, the Intel Corporation 8271 integrated circuit is replaced by a simpler integrated circuit such as the FD 1771 made by Messrs. Western Digital Corporation. There are other buses and other conductors linking the interface 16 to the control circuit 30 but only those which are used at the time of formating have been shown here.Thus, in addition to the bus 32, which in this new configuration is connected to the formating arrangement 31, there is a conductor 33 along which the control circuit 30 transmits to the formating arrangement a signal DRQ which indicates the recording of a code on a track on disc 21 or 17. There is also a conductor 34 which connects circuit 30 to interface 16 and which enables the interface to be informed that the formating of a track has been completed. The other conductors and buses between circuit 30 and interface 16 are represented as a group by a connection 35. Finally, a bus 36 connects the output of the formating arrangement 31 to an input of the control circuit 30 and transmits the codes which are to be recorded on the tracks on a disc when the said tracks are being formated.

Before the formating arrangement is described in any greater detail with reference to Fig. 2, the items of data which have to be recorded on a track in order to format it will be described with reference to Fig. 3. The beginning of each track is indicated by an index marker 51 (GO).

Physically, the index markers for all the tracks on a disc are situated along the same radius and each marker is formed for example by forty-seven binary codes. The index marker 51 is followed by a space 52 (or G1) in which are recorded thirty-two eight-digit binary codes for example. In what follows, such eight-digit binary codes will be termed octets. Space 52 is followed by a space 53 (or ID1) in which are recorded a number of octets to indicate the address of sector No.1 along the track. Space 53 (or ID1) is followed by a space 54 (or G2) in which are recorded seventeen octets for example. This space 54 (or G2) is followed by a space 55 (or S1) in which are to be recorded the octets representing the data proper. Depending on the format adopted for the track, the length of this space 55 (or S1) may be such as to allow 128, 256 or 512 octets to be recorded.In what follows, this space in which the data proper is recorded will be referred to as a sector, followed by its serial position along the track, S1 being the first sector after the index marker.

Space 55 or sector S1 is followed by a space 56 (or G3) in which twenty-seven octets are recorded. Space 56 (or G3) is followed by a space 57 (or ID2) in which are recorded a number of octets to indicate the address of sector No.2 (or S2) along the track. This space is followed in succession by spaces 58 (or G2), 59 (or S2), and 60 (or G3), spaces 58 and 60 (or G2 and G3) being separating spaces which divide sector S2 (or any sector) from its address code lD2 (space 57) or from the address code ID3 (space 61) for the next sector S3 (space 63).

When the format adopted for the sectors of a track involves 128 octets, the number of sectors along a track is twenty-six. The track will thus end in a space 65 for an address code ID 26, followed by a space 66 for G2, followed by a space 67 for sector S26 and followed by a final space 68 (or G4) which precedes the index marker 51 for the beginning of the track. The space G4 allows approximately 320 octets to be recorded in the case of a track with twenty-six sectors. It is a buffer space containing a number of octets which depends on the variations in the speed of the disc.

In the course of the formating operation, the octets which are recorded in the various spaces represent specific codes which will be detailed below. These codes will be defined by doublets of numbers and/or letters, the numbers and letters corresponding to four digit codes as shown in table 1.

TABLE 1 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F The address code ID for each sector S is formed by seven octets (Fig. 3). The first octet 70 corresponds to the code FE = 11111110 and is the same for all the sector address codes.

Octets 71 to 74 are codes which vary with the address of the sector and which respectively represent the track number (71), the number of the recording head, i.e. the face of the disc, (72), the sector number (73), and the length of the sector (74). Octets 75 and 76 are codes for detecting errors in the address code ID; they may be obtained, for example, by applying the various octets of the address code to a circuit for calculating polynomials which emits the said codes 75 and 76 from its output. The calculating circuit does in fact form an integral part of the control circuit 31 and will not be described in detail here. It is merely necessary to know that the octets which it emits are recorded on the track when the formating arrangement 31 transmits the code F7, as will be described below.

Each sector S for recording data, no matter what its length, begins with an octet 77 which corresponds to the code FB = 11111011, and ends with two octets 79 and 69 which correspond to error codes. Octets 79 and 69 are calculated by the same polynomial calculating circuit as was mentioned above and they are recorded on the track when the formating arrangement 31 transmits the code F7. The calculation is performed on all the octets contained in the sector. As far as formating is concerned, the data octets are all identical and correspond to the code E5 = 11100101. It is clear that when a data recording operation takes place, the octets which are then recorded in the sectors depend on the items of data themselves and are thus variable.

As table 2 shows, the index marker 51 (GO) for each track is formed by recording forty-seven octets, such as forty octets FF = 11111111, six octets 00 = 00000000, and one octet FC= 11111100.

Space G1 is formed by a recording of twenty-six octets FF and six octets 00.

Space G2 is formed by a recording of eleven octets FF and six octets 00.

Space G3 is formed by a recording of twenty-seven octets FF.

Space G4 is formed by a recording of at least 247 octets FF in the case of 128-octet sectors, a recording of at least 197 octets in the case of 256-octet sectors, and a recording of at least 257 octets in the case of 512-octet sectors.

On a track is is possible to record twenty-six 128-octet sectors, fifteen 256-octet sectors or eight 512-octet sectors.

From the description which has just been given of the track it will be seen that the formating operation consists in recording fixed codes or octets, such as FF, E5, 00 etc., and variable codes or octets on each track, the latter codes representing address spaces and error codes.

The numbers of octets quoted for the various spaces along the track and the values for the codes used have been given merely by way of illustration and may thus vary between different embodiments. The same is true of the number of data octets per sector and of the makeup of the sector address codes and so on.

TABLE 2

26 sectors 15 sectors 8 sectors 128 Octets 256 octets 512 octets Number Number Number from to of of of octets from to octets from to octets FF 40 1 40 GO :00 6 41 46 G1 : FC 1 47 47 G1 :FF 26 48 73 100 t00 6 # < 779 1 t marker :FE 1 80 80 track :v 1 81 811 face :v 1 82 82 1 D sector :v 1 83 83 1 length :v 1 84 84 error :F7 1 85 85 GAP2 :FF 11 86 96 :00 6 97 102 1 marker ::FB 1 103 1031 S data :E5 128 104 2311 256 104 359 512 104 615 error :F 1 232 2321 1 360 3601 1 616 616 G3 :FF 27 233 42 361 \4O21 60 617 76 AP4 G4 :FF > 247 260 > 197 403 > 257 677 These various codes, whether fixed or variable, are produced by the formating arrangement 31 (Fig. 2) according to the present invention. To allow a disc to be formated the interface 16 transmits along the bus 32 to the formating arrangement 31 a number of codes which are recorded in five registers R1 to R5 (Fig. 4).Register R1 contains the code for the track, which is one of the seventy-six tracks on one face of a disc. Register R2 contains the code for the face of the disc and thus identifies the recording head. register R3 contains the code for the sector of the track which is to be formated first, this code generally being the code for the first sector.

Register R4 contains the code for the format of the sectors, i.e. their length. Finally, register R5 contains the code for the layout of the sectors along the track, to allow the sectors to be laid out in different ways.

In cases where there are twenty-six sectors, there are thirteen different ways of arranging them or laying them out along a track, such as in the sequence 1, 2, 3, 4 . . 26 (interval of 1), or in the sequence 1, 3, 5 . . 24, 26 (interval of 2), or again in the sequence 1, 14, 2 13, 26 (interval of 13). In cases where there are fifteen sectors, there are eight different ways, such as in the sequence 1, 2 . 14, 15, or the sequence 1, 3, 5 . . . 12, 14. or again the sequence 1, 9, 2 . . 15, 8. In cases where there are eight sectors, there are four different ways, such as in the sequence 1, 2 . . 7, 8 or the sequence 1, 5 . . . 4, 8.

The track and face codes will remain the same throughout the operation of formating a track and thus will not need to be changed. The sector codes on the other hand will alter in the course of the operation and the original code will have to change as dictated by the format code and the layout code. These changes to the original code are performed by means of a circuit 33 (shown in a broken out-line) to which are applied the codes contained in registers R3, R4 and R5. Circuit 33 is also intended to produce or generate the fixed codes FF, 00, FC, FE, F7, FB and E5 for the octets depending on whether what is involved is a space GO, G1, G2, G3 or G4 or the beginning or end of the address code ID or the sector S.

In accordance with the present invention, circuit 33 comprises chiefly, as shown in Fig. 4, a memory 80 which contains the various fixed codes, a memory 81 which contains the various variable codes, a counter 82, a decoding circuit 83 which decodes the numbers contained in the counter 82, and a logic circuit 84 which receives on the one hand the decoded signals and on the other hand the signals coming from registers R3, R4 and R5. The signals which appear on the output conductors 85 of logic circuit 84 are applied to memories 80 and 81 to enable them to be addressed. The signals produced by reading memories 80 and 81 appear on readout conductors 86 and 87 respectively, which unite to form a bus 36. Counter 82 is incremented by means of a signal DRQ which is emitted by the control circuit 30 along conductor 33 (Figs.

2 and 4) each time an octet has been recorded. The count in counter 82 thus indicates the serial position along the track of the octet which has just been recorded.

Before giving an explanation of the operation of the circuit in Fig. 4, the items of data which have to be recorded along a track as a function of its position and the length of its sectors will be detailed with reference to table 2. In table 2, the first two columns will be found to contain the references which were used when referring to Fig. 3 to describe the content of a track. The next columns are three in number, the first corresponding to organisation into twenty-six 128octet sectors, the second to organisation into fifteen 256-octet sectors, and finally the third to organisation into eight 512-octet sectors.Each column in turn consists of three columns containing numbers which indicate the number of octets to be recorded in the space given in the first column of the table in the case of the first column, the serial position along the track of the octet at the beginning of the space in the case of the second column, and the serial position of the octet at the end of the space in the case of the third column.

In table 2, the arrow 100 indicates that when the 259to octet has been recorded, i.e. at the end of the first sector, the operations then performed to format the seond sector are identical to those for the first sector except that they begin at serial position 74. A loop is thus made each time a sector is formated. Arrows 101 and 102 represent the loops for the other sector lengths.

In the second column, the lower-case letter v indicates that the content of the octet is variable and that what is involved are certain octets forming the address code ID for each sector.

It will be seen from perusal of the table that the first forty octets on the track are FF's. They may thus be obtained by recording this octet on the first row of the memory 80, which row will be read forty times in succession by means of the code supplied by counter 82.

Similarly, the next octets in serial positions 41 to 46 are 00's and they may for example be obtained by recording this octet on another row of the memory 80, which row will be read six times in succession by means of the code supplied by counter 82.

One possible organisation for the memory 80 is shown in table 3.

TABLE 3 Row 0 1 2 3 0 1 2 3 Code 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 FF 5 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 7 1 1111 8 0 0 0 0 0 0 0 0 00 9 1 1 1 1 1 1 0 0 FC 10 1 1 1 1 1 1 1 0 FE 11 1 1 1 1 0 1 1 1 12 1 1 1 1 0 1 1 1 F7 13 1 1 1 1 0 1 1 1 14 1 1 1 1 0 1 1 1 15 1 1 1 1 1 0 1 1 FB 16 1 1 1 0 0 1 0 1 17 1 1 1 0 0 1 0 1 18 1 1 1 0 0 1 0 1 19 1 1 1 0 0 1 0 1 20 1 1 1 0 0 1 0 1 21 1 1 1 0 0 1 0 1 E5 22 1 1 1 0 0 1 0 1 23 1 1 1 0 0 1 0 1 24 1 1 1 0 0 1 0 1 25 1 1 1 0 0 1 0 1 26 1 1 1 0 0 1 0 1 27 1 1 1 0 0 1 0 1 28 1 1 1 0 0 1 0 1 The memory 81 for the variable codes is organised in a similar way to memory 81 in that each row contains one octet and each row is addressed by an output signal provided by logic circuit 84. Memory 81 does however differ greatly from memory 80 in that it contains a far larger number of octets. In effect, with a given layout for sectors of 128 octets, the number of different octets is equal to the number of address codes since, in an address code, only the octet representing the sector number varies. With the thirteen different I'ay,out's for the twenty-six sectors, there are 26 x 13 = 338 octets or rows to be read.With the eight different layouts for the fifteen sectors, there are 26 x 8 = 208 octets or rows to be read. Finally, with the four different layouts of eight sectors, there are 26 X 4~104 octets or rows to be read. The memory 81 for the variable codes thus contains 338 + 208 + 104 = 650 octets or rows to be read.

It will be appreciated that the memories 80 and 81 rnay be organised in different ways to suit the possible decoding results and the capacity of the memories available.

The contents of memory 81 have not been shown in a table in the same way as the contents of memory 80, but the explanation given above will be adaquate to enable a person skilled in the art to produce the said memory.

Thus, the manner in which the formating arrangement shown in- Fig. 4 operates is as follows.

The control unit 16 issues a fdrmating instruction to the formating arrangement and at the, same time transmits along bus 32 the data needed for this operation, namely the codes for track, face (or head), sector the first), format (length i s-ectors), and sector layout (the interval between one sector number and the next). This data- is recorded in registers R1 tollS. Counter 82 is reset to zero. The formating arrangement is then ready to perform forníating operations on the track identified-- by the codes contained in registers R 1 and R2.The first operation takes place as soon as the control circuit 30 emits the first signal DRQ along the conductor 33 which is connected to counter 82. The- decoding of the code from the counter by the decoding circuit 83 produces a signal which is applied to logic circuit 84 and which enables the first row of memory 80 (table- 3)-to be addressed. The- output code FF from memory 80- is transmitted to the control circuit 16 along bus 36. Once this first octet FF has bee#n recorded, the control circuit 30 emits a second signal DRQ which increments the counter 82 by one unit. The decoded signal again addresses the same row in memory 80 and the memory thus emits the same octet FF.

Operations continue in this way under the timing of the signals DRQ, which increment the counter 82, and the decimal equivalents of the codes from the counter are shown in table 2.

When the counter 82 reaches a count of 81, the result of this count being decoded is that register R1 is addressed (bus 88) and its content is transferred to control circuit 30 to be recorded-on the track. It is the number of the track currently being formated.

At the next DRQ signal the counter goes to a count of 82 which, when decoded, enables register R2 to be addressed (bus 88) and the content of register 82 -(face or head code) is transferred to the control circuit to be recorded on the track.

At a count -of -83, the signal for the decbding of this count enables a row in memory 81 to be addressed whose content;(sectof code) is-transferred on the one hand to the control circuit 30 for recording on the tracklan-dn~the other hand to register R3 (bus 89).

At a count of 84, it is the turn of the sector length code in register R4 to be transferred (bus 88) to control circuit 30.

At a count of-85, the signal produced by decoding enables a row in memory 80 to be addressed which contains the code F7 and this code is transferred to control circuit 30 to cause the two error codes 75 and 76 (Fig. 3) to be recorded on the track.

At each subsequent signal DRQ, the counter 82 moves up onte unit and enables one row of the memory 80 to be addressed and read out and its content to be transferred to the control circuit 30 for recording on the track whose number is provided by register R1.

At a count of 259 in the case of a 128-octet sector, or at a count of 402 in the case of a 256-octet sector, or at a count of 676 in the case of a 512-octet-sector, counter 82 is driven to a count of 74 by-means of a signal RAZ 74 which is generated by logic circuit 84 and transmitted along the conductor 90. The effect of this is to initiate the operations involved in formating the next sector, which-#operations are identical to those which have just been described, except for the sector code. In effect, at a count of 83, the decoding of this count and of the codes from registers R3 (previous sector), R4 (sector length), and R5 (sector layout) enables that row in the memory 81 to be addressed which contains the code for the next sector.

On completion of the formating of the twenty-sixth sector, or the fifteenth sector, or the eighth sector, depending on the length of the sectors, the counter 82 is not reset to a count of 74 but continues to move up to allow the octets for space FF to be recorded, and does so until the index marker for the beginning of the track is detected. The index marker s#ignal brings the operation of formating the track to a close and notifies the interface, via conductor 34 (Fig. 2), that anoter track can be formated.

It will be seen that formating can begin at whatever sector is recorded in register R3.

The invention has been described with reference to one specific embodiment but it is clear that it can be used in various embodiments and in particular with discs of different kinds, different space and sector layouts, snd different organisations for memories 80 and 81.

Claims (5)

1. Formating arran-gern-ent for a disc-memory which forms one of the peripheral units of a digital computer, recording in and read-out from the disc memory being accomplished by a control circuit which is connected to a unit for controlling the said peripheral units, characterised in that the said formating arrangement is arranged as a shunt between the unit for controlling the peripheral units and the control circuit for the disc memory and in that it is adapted to format one complete track on the disc without needing to interrupt the operation of the unit for controlling the peripheral units.

2. Formating arrangement for a disc memory according to claim 1, characterised in that it comprises a plurality of registers adapted to receive codes defining the formating details, a memory for the codes capable of being recorded in the course of the formating of all the tracks on the disc, a bidirectional counting circuit adapted to move up one unit each time a code is recorded in the disc memory, and a logic circuit for addressing the said memory for the codes which receives on the one hand the decoded signals and on the other the codes contained in the said registers.

3. Formating arrangement according to claim 2, characterised in that the memory for the codes capable of being recorded in the course of formating a disc comprises a first memory containing the fixed codes to be recorded in certain spaces along the track and a second memory containing so-called variable codes which represent the numbers of the sectors.

4. Formating arrangement according to claim 2 or claim 3, characterised in that the registers are five in number, namely a first register for the code indicating the track, a second register for the code indicating the face of the disc, a third register for the code indicating the sector to be formated, a fourth register for the code indicating the length of the sectors, and a fifth register for the code indicating the layout of the sectors along a track.

5. A formating arrangement, substantially as hereinbefore described with reference to the accompanying drawings.