GB2045000A - An asymmetric thyristor - Google Patents
An asymmetric thyristor Download PDFInfo
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- GB2045000A GB2045000A GB8009260A GB8009260A GB2045000A GB 2045000 A GB2045000 A GB 2045000A GB 8009260 A GB8009260 A GB 8009260A GB 8009260 A GB8009260 A GB 8009260A GB 2045000 A GB2045000 A GB 2045000A
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- 230000001154 acute effect Effects 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 181
- 239000012535 impurity Substances 0.000 claims description 27
- 230000005684 electric field Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 11
- 239000000969 carrier Substances 0.000 claims 4
- 230000000977 initiatory effect Effects 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7432—Asymmetrical thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/1016—Anode base regions of thyristors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
In a thyristor having an n<+>pn<->n<+>p<+> structure, the junction 30 between the n-base 26 and the p<+>-type anode-emitter 31 terminates at the lower surface of the thyristor. The interface 32 between the n<-> and n<+> regions 27,28 of the n-base 26 also terminates at the lower surface. This arrangement provides a high blocking voltage and a low forward voltage drop. A p<+> field- dividing ring 37 is formed in the lower surface of the thyristor n<-> between the interface 32 and the edge. The edge is negatively bevelled such that the angle between the top surface and the edge is acute. The n<+> type cathode emitter 20 is annular and surrounds the gate electrode 44. <IMAGE>
Description
SPECIFICATION
An asymmetric thyristor
This invention relates to four-layer semiconductor thyristors and in particular to asymmetric four-layer semiconductor thyristors.
A semiconductor thyristor commonly comprises four layers of semiconductor material including a cathode emitter, a cathode base, an anode base, and an anode emitter. In typical applications, a blocking voltage is applied across the two emitters of the thyristor and under particular biasing conditions, little or no current passes through the device until a signal is applied to a gate which is normally coupled to the cathode base. It is well known that the anode base width of a thyrister must be increased proportionally with the blocking voltage requirement. It is also known that a very large anode base width leads to an increased # j forward voltage drop and thereby lowers the device efficiency and power handling capability.
A proposed solution to minimize the cathode base uses an n+pnn+p+ asymmetric structure. However, one problem with the asymmetric thyristor is that the device is likely to break down at the surfacem After the space-charge region penetrates into the n+ anode-base layer, the electric field tends to peak at the nn+ juntion and causes surface breakdown there possibly destroying the thyristor.
It is the principal object of the invention to increase the blocking voltage of a thyristor.
The invention resides broadly in a five-region semiconductor device having top and bottom surfaces and an edge, said device comprising: a first and second semiconductor region defining a first p-n junction; semiconductor means forming a second p-n junction with said second semi-conductor region, said semiconductor means including third and fourth semiconductor regions creating a semiconductor boundary; and a fifth semiconductor region coupled to said semiconductor means creating a third p-n junction; said semiconductor means having first and second dissimilar portions, said first portion extending from said second p-n junction to aid third p-n junction, said second portion extending from said second p-n junction to said bottom surface.
An asymmetric thyristor having top and bottom surfaces and an edge therebetween including four layers of semiconductor material having alternate type conductivity, a p-n junction formed between each adjacent pair of layers. The four layers are interdisposed between the top and bottom surfaces and are commonly referred to in sequence of dispostion from the top surface as the cathode-emitter layer, the cathode-base layer, the anode-base layer, and the anode-emitter layer.In its broadest concept, the anode-base layer of the thyristor of the present invention comprises two anode-base regions including a semiconductor region having a low impurity concentration commonly designated by affixing a minus (-) sign superscript to an n-type or a p-type semiconductor designation (n-, p-) and including a region having a high impurity concentration commonly designated by affixing a plus (+) sign superscript to an n-type or a p-type semiconductor designation (n+, p+). A semiconductor boundary which terminates at the bottom surface is formed between the two anode-base regions. The low impurity anode-base region is adjacent to the cathode-base layer and forms a p-n junction therewith which extends to the edge. The high impurity region is adjacent to the anode-emitter layer and forms a p-n junction therewith which terminates at the bottom surface.
More particularly, the cathode-emitter may be ring-shaped having outside and inside perimeters and is centrally disposed in the cathode-base layer. A ring-shaped cathode electrode having outer and inner perimeters is centrally disposed on the top surface such that the outer perimeter of the cathode electrode is between the outer perimeter of the cathode emitter and the edge of the thyristor and such that the inner perimeter of the cathode electrode is between the inner and outer perimeters of the cathode emitterm A disc-shaped gate electrode having an outer perimeter is centrally disposed on the top surface such that the outer perimeter of the gate electrode is within the inner perimeter of the cathode emitter. A disc-shaped emitter electrode is centrally disposed on the anode-emitter layer.The semiconductor boundary formed by the two anode-base regions does not extend to the edge of the thyristor but curves away from the top surface such that the boundary terminates at the bottom surface.
In one embodiment of the thyristor of the present invention, a field-dividing ring of semiconductor material having the same type conductivity as the anode-emitter layer is disposed in the low impurity region of the anode-base layer between the anode-base boundary and the edge. The field dividing ring has a surface coplanar with the bottom surface.
In another embodiment of the thyristor of the present invention, the edge is negatively bevelled such that the angle between the top surface and the edge is acute and the angle between the bottom surface and the edge is obtuse.
Figure 7 is a sectional view of a thyristor according to the teachings of the present invention;
Figure 2 is a sectional view of a disc-shaped semiconductor device having one type of bevelled sides;
Figure 3 is a sectional view of a disc-shaped semiconductor device having another type of bevelled sides;
Figure 4 is a view of the top surface of a thyristor according to the teachings of the present invention;
Figure 5 is a view of the bottom surface of a thyristor according to the teachings of the present invention;
Figure 6 is a graph of the electric field within the bulk of the thyristor of Figure 1;
Figure 7 is a graph of the eletric field outside the bulk of the thyristor of Figure 1::
Figure 8 is a sectional view of the thyristor of Figure 1 showing the boundaries of a space-charge region for voltages less than and greater than Vrnax; and
Figures 9 through 12 show a preferred method of allowing the electrodes for the thyristor of Figure 1.
Figure 1 shows a sectional view of a thyristor 10 according to the teachings of the present invention taken along the lines I-I of Figure 4. The thyristor 10, which is center fired, comprises a top surface 11 and a bottom surface 12 extending betwen which is an edge 13 connecting the surfaces 11 and 12. Between the top and bottom surfaces 11 and 12 and within the edge 13 are an n±type anode-emitter layer 20 preferably 10 calm thick and a p-type cathode-base layer 21 preferably 40 calm thick between which layers 20 and 21 is formed a p-n junction 22. The p-n junction 22 has at the top surface 11 an outer perimeter 23 and an inner perimeter 24.
The n+ layer 20 has an impurity concentration between about 1018 donor atoms/cm3 and 1020 donor atoms/cm3 but is preferably about 1020 donor atoms/cm3. The p layer 21 has an impurity concentration of between 1015 acceptor atoms/cm3 and 1018 acceptor atoms/cm3 but is preferably about 1016 acceptor atoms/cm3. An anode-base layer 26 having an n- region 27 preferably about 1501lem thick through the center of the thyristor 10 and an n+ region 28 preferably about 35 cm thick forms a p-n junction 29 with the cathode-base layer 21 and forms a p-n junction 30 with a p±type anode-emitter layer 31 preferably about 201lm thick. The p-n junction 29 extends across the thyristor 10 and terminates at the edge 13.The p-n junction 30 terminates at the bottom surface 12. the n- region 27 has an impurity concentration between about 1013 donor atoms/cm3 and 1015 donor atoms/cm3 but is preferably 1013 donor atoms/cm3. The n+ region 28 has an impurity concentration between about 1015 donor atoms/cm3 and 1018 donor atoms/cm3 but is preferably about 1016 donor atoms/cm3. The p+ layer 31 has an impurity concentration between about 1018 acceptor atoms/cm3 and 1020 acceptor atoms/cm3 but is preferably about 1020 acceptor atoms/cm3. In any event, the impurity concentration of the p+ layer 31 should be greater than the impurity concentration of the n region 28.
A semiconductor boundary 32 is formed between the n- region 27 and n+ region 28 and terminates at the bottom surface 12. A p-type semiconductor region 37 having a thickness equal to the thickness of the p+ layer 31 forms a field-dividing ring in the n- region 27 between the semiconductor boundary 32 and the edge 13 and also forms a p-n junction 39 with the n- region 27. The field-dividing ring 37 also has a surface 41 coplanar with the bottom surface 12 and has an impurity concentration similar to that of the p+ layer 31, i.e.
between about 1018 acceptor atoms/cm3 and 1020 acceptor atoms/cm3, but is preferably about 1020 acceptor atoms/cm3.
A A 10 Rm thick aluminum cathode electrode 43 is ohmically coupled to the surface 11 and may extend from near the edge 13 across a portion of the n+ layer 20 such that the n+ cathode emitter 20 and the p cathode base 21 are shunted. A 10 cm thick aluminum gate electrode 44 is ohmically coupled to the p-layer 21 in the center of the top surface 11. A 10 Fm thick aluminum anode electrode 45 is ohmically coupled to a portion of the p+ layer 31 in the center of the bottom surface 12 such that the p+ anode emitter 31 and the n+ anode base 28 are not shunted.
The edge 13 is bevelled such that the intersection of the top surface 11 and the edge 13 makes an acute angle a and the intersection of the bottom surface 12 and the edge 13 makes an obtuse angle . Bevelling in this fashion causes a space-charge region boundary 50 in the n layer 27 to bend downward away from the p-n junction 29 providing improved protection to the p-n junction 29 from the breakdown due to high electric fields FEl. The improvement in protection can be explained with the aid of Figures 2 and 3. Figure 2 shows a sectional view of a disc-shaped semiconductor device 100 comprising a top surface 111 and bottom surface
111 and bottom surface 112 extending between which surfaces 111 and 112 is and edge 113 connecting the surfaces 111 and 112.The edge 113 is bevelled such that an angle a1, between the top surface 111 and the edge 113 is obtuse and an angle P1, between the bottom surface 112 and the edge 113 is acute. Between the top and bottom surfaces 111 and 112 and within the edge 113 are an n--type layer of semiconductor material
127 adjacent to a p-type layer of semiconductor material 121 between which layers 121 and 127 is formed a
p-n junction 129 extending to the edge 113. When a space charge region having a boundary 150 in the layer
127 and having a boundary 151 in the layer 121 is created around the p-n junction 129, the boundaries 150 and 151 bend upward toward the p-n junction 129 in areas near the edge 113, finally terminating at the edge 113 a distance X1 from the p-n junction 129.This concavity occurs because the boundaries 150 and 151 will always terminate so as to be perpendicular to the edge 113. The electric field E1 across p-n junction 129 at the edge 113 for a given voltage V across the junction 129 can be computed as E1 aV/X1. Figure 3 shows a sectional view of a disc-shaped semiconductor device 200 having a structure generally similar to the structure of the device 100 of Figure 2 with the exception that the device 200 of Figure 3 has an edge 213 bevelled like the edge 13 of Figure 1 such that an angle a2 between the top surface 211 and the edge 213 is
acute and an angle P2 between a bottom surface 212 and the edge 213 is obtuse.When a space-charge
region having a boundary 250 in an n-type semiconductor layer 221 is created around a p-n junction 229, the
boundaries 250 and 251 bend downward away from the p-n junction 229 in areas near the edge 213, finally terminating at the edge 213 a distance X2 from p-n jujnction 229. This convexity occurs because the
boundaries 250 and 251 will always terminate so as to be perpendicular to the edge 213. The electric field E2
across the p-n junction 229 at the edge 213, assuming the voltage V is applied thereacross, can be computed
as E2aV/X2. Since the boundary 250 is convex elementary geometry proves that the distance X2 is necessarily
larger than the distance X1 and it follows that E2 necessarily smaller than E1. The resulting smaller electric field E2 for the given voltage V provides an added margin of protection for the p-n junction 229.
As can be seen from Figure 3, the smaller the angle a2 is, the more convex the boundary 250 will become in order to be perpendicular at the edge 213 and the larger distance X2 becomes. Similarly, in Figure 1, the smaller the angle a, the greater the margin of breakdown protection provided to the junction 29. The angle a is preferably 309 but can be typically any angle from 30 to 609 Any angle a less that 30 may unduly limit conducting area and any angle a greater than 600 may not provide adequate protection to the junction 29.
Figure 4 shows a top view of the surface 11 of the thyrister 10. The gate electrode 44 is disc-shaped having a radius r44 = 0.10". The cathode electrode 43 is ring-shaped having an inside radius ri43 = 0.12" and an outside radius ro43 = 0.90". The n+ layer 20 is also ring-shaped having an inside radius ri20 = 0.11" where the p-n junction 22 terminates at the surface 11 at one circle and having an outside radius ro20 = 0.70" where the p-n junction 22 terminates at the surface 11 at another wider circle. The surface 11 has a radius r11 = 1.0".
Figure 5 shows a top view of the surface 12 of the thyristor 10. The anode electrode 45 and the p+ layer 31 are disc-shaped having radii r45 = 70" and r31 = 0.75", respectively. The n+ region 28 and the p+ region 37 are both ring-shaped at the surface 12. The n+ region 28 has an inside perimeter coincident with the perimeter of the p+ anode-emitter region 31 and has an outside perimeter having a diameter ro28 = 0.80".
The p+ field-dividing ring 37 has an inside perimeter having a radius ri37 = 90 um and has an outside perimeter having a radius ro37 = 110 Fm. The outside perimeters of the p+ anode-emitter region 31 and the n+ cathode-emitter region 20 have equal radii in order to optimize current flow in the thyristor 10. The surface 12 has a radius r12 = 966 mils. A feature of the negatively bevelled edge 13 is that the surface 11 has a larger radius than the surface 12.
Referring back to Figure 1, in operating the thyristor 10, a negative potential V- is applied to the cathode electrode 43 and the anode electrode 45 is grounded. A potential Vg is applied to the gate electrode 44. The potential V- is variable having a range from Vlmost negative to Vzleast negative and creates a depletion region or space-charge region around the p-n junction 29. As the potential V - becomes more negative, the depletion region extends farther and farther into the n- region 27 while extending only slightly farther into the p-region 21. At a potential Vso within the range of V-, the space-charge region crosses the semiconductor boundary 32 and begins to extend into the n+ region 28. An edge of the space charge region at Vso is shown in Figure 6 by the dashed lines at 60.Any further increase in V- over the potential Vso extends the depletion region farther into the n+ region 28 but only slightly since the rate at which the depth of the depletion region in a semiconductor layer increases is inversely proportional to the doping concentration in the semiconductor layer. The presence n+ layer 28 allows a higher reverse voltage to be applied across the thyristor 10 given an anode-base layer 26 having a predetermined thickness since the depletion region advances more slowly through the n+ region 28 than through then region 27 as the potential V- increases.
At some potential V, within the range of V- and more negative than Vs-o, the depletion region will "punch through" the p-n junction 30 to the p+ layer 31 and the p-n junction 30 will be shorted out causing the device to destroy itself. The n+ region 28 is preferably between 35 um thick and 45 um thick but can be narrower so long as it is thick enough so that the depletion region will not punch through the p-n junction 30 to the p+ region 31 prematurely, i.e., before the maximum rated voltage Vmax is reached within the range of V-.
Alternatively, for a given thickness of the n+ region 28, the concentration can be increased in order to avoid or present premature punch-through. Expressed alternatively, Vot and Vmax have a relationship such that: I Vot > Vmax
The n+ region 28 can also be thicker but the higher impurity concentration causes a low carrier lifetime and an n region 28 too thick may affect the forward voltage drop capability of the thyristor 10.
Then region 27 typically has a thickness between lOOum and 150 cm in order to block 1000V where an region 28 is not present. For the thyristor 10, however, the thickness of the n- region 27 can be reduced from the anode-base layer in a conventional thyristorto between 50 ism and 75ym in order to block 1000V.
This can be understood more readily by referring to Figures 6 and 7. Figure 6 shows a graph of a function F1 representing the intensity E of the electric field (ordinate) in the bulk of the anode-base layer 26 between the lines 74 and 75 as a function of the distance p (abscissa) from the p-n junction 29. The function F1 of Figure 6 includes intersecting curve segments 70 and 71 both of which have negative slopes. The slope of curve 71 is more negative than the slope of curve 70. Curve segment 70 shows the intensity of the electric field in then layer 27 and curve segment 71 shows the electric field intensity in the n+ layer 28. The constant pl of Figure 6 is the total thickness of the anode-base layer 26 in the bulk of the thyristor 10.The blocking voltage capability of the thyristor 10 having an anode-base layer characterized by the electric field distribution of Figure 6 is proportional to the area under the function F1 of Figure 6. This voltage blocking capability of the thyristor 10 has been achieved with an anode-base layer having a thickness pl = 185 cm.
Figure 7 shows a graph of a function F2 representing the the intensity (E) of the electric field (ordinate) near the surface of the anode-base layer 26 outside the lines 76 and 77 as a function of the distance p (abscissa) from the p-n junction 29. The function F2 includes a curve segment 72 having a slope equal to the slope curve segment 70 of Figure 6.
Generally, a p-n junction is more vulnerable to voltage breakdown at a surface than in the bulk of the device because the surface is more likely to have discontinuities that may cause failure. Within its bulk, a semiconductor device is more likely to be more homogeneous and is, therefore, less vulnerable to voltage breakdown. A particular problem arises to the extent that the breakdown voltage VBB of a p-n junction in the bulk of a device may be different from the breakdown voltage VBS of a p-n junction at the surface of the same device i.e., at the edge 13 of the thyristor 10. However, it is more important to protect a p-n junction at the surface since a voltage breakdown there is more likely to be irrecoverable and destroy the device.Assuming the p-n junction 29 of Figure 1 breaks down at the edge 13 at the voltage VBS, it is common practice to subject the junction 29 to the maximum voltage Vmax within the bulk of the thyristor 10 having a margin of safety such that: (2) Vmax = Ves + Ve where V, is the desired voltage margin of safety. In the thyristor 10 of Figure 1, any increase AV- in voltage over the voltage Vss appears across the p-n juntion 39. An edge 61 of the space-charge region under such a condition is depicted in Figure 8. The voltage Vss can be controlled by the depth of the region p+ such that the deeper the p+ region 37 is diffused, the smaller the voltage V85.The distance of the p-n junction 39 from the p-n junction 32 is preferably of a relationship: (3) (ri37 - r28) = 5d or in any event, (4) (ri37 - r28) > > d where d is the smallest distance between the p-n junction 39 and the p-n junction 29.The distance d in the embodiment of Figure 1 is approximately 185 cm. In addition, the space (ri37-r28) between the p-n junction 39 and the p-p junction 32 should be as narrow as possible to conserve space but should be wide enough to allow the space charge region attributable to AV to expand without punching through the p-n junction 32 to the n+ region 28 within the desired range of EV-. The width of the field-dividing ring 37 can vary from 20 mills to 50 mils but generally should be as narrow as possible in order to conserve space but should be no narrower than the maximum width of the space-charge region in the region 37 within the desired range of AV#. The p+ region 37 is typically at least as deep as the p+ layer 31, but can be deeper depending on the voltage Vmax desired. The p+ region 37 should be as close to the edge 13 as possible so as to conserve surface area. The n+ anode-base 28 and the p+ anode-emitter 31 can be formed by the planar technology.
The alloying contacts for both the anode and cathode emitters can be modified as follows. Figure 9 shows a silicon wafer 300 including the semiconductor elements of the thyristor 10 which will be aluminized at the anode emitter 31 and sintered at 5000C to 550 C to form the anode electrode 45. A molybdenum disc 301 covering the anode electrode 45 and having the same radius will be fused thereto at 700 C to 7500C as shown by Figure 10. The wafer 300 will be metallized again on the cathode emitter and by shadow evaporation and sintered to form the gate electrode 44 and the cathode electrode 43 as shown in Figure 11. Finally, Figure 12 shows a separately metallized and sintered silicon disc 302 having an opening at the center to provide access to the gate electrode 44. The silicon disc 302 will be fused onto the cathode 43 at a temprature of about 600 C to 650 C much below the temperature of the molybdenum fusion. A lower fusion temperature will prevent deep alloying penetration at the cathode emitter and the silicon disc 302 at the cathode emitter will provide mechanical supportforthe surface bevelling operation and improve the surge capability of the thyristor 10.
Claims (17)
1. Afive-region semiconductor device having top and bottom surfaces and an edge, said device comprising:
a) a first and second semiconductor region defining a first p-n junction;
b) semiconductor means forming a second p-n junction with said second semiconductor region, said semiconductor means including third and fourth semiconductor regions creating a semiconductor boundary; and
c) a fifth semiconductor region coupled to said semiconductor means creating a third p-n junction;
said semiconductor means having first and second dissimilar portions, said first portion extending from said second p-n junction to aid third p-n junction, said second portion extending from said p-n junction to said bottom surface.
2. A semiconductor device according to claim 1 further including:
biasing means responsive to an electrical biasing condition for injecting current carriers from said first semiconductor region into said second semiconductor region.
3. A semiconductor device according to claim 2 wherein said biasing means includes:
a) shunting means for shunting said first and second semiconductor regions, said shunting means including means for providing current carriers in said first semiconductor region in response to a first electrical signal;
b) gate means for initiating the injecting of current carriers from said first semiconductor region to said second semiconductor region in response to a second electrical signal; and
c) anode means for providing current carriers to be injected from said fifth semiconductor region into said semiconductor means in response to a third electrical signal.
4. A semiconductor device according to claim 3 wherein.
a) said first portion is responsive to said electrical biasing condition for creating an electric field the intensity of which is characterized by at least first and second intersecting lines on a first graph, said first graph having an ordinate constituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said first line having a first slope, said second line having second slope, said first slope being negative, said second slope being more negative than said first slope; and
b) said second portion is responsive to said electrical biasing condition for creating an eletric field the intensity of which is characterized by a third line on a second graph, said second graph having said ordinate and said abscissa, said third line having said first slope.
5. A semiconductor device according to claim 4 wherein said second portion partially confines said first portion.
6. A semiconductor device according to claim 3 wherein:
a) said first portion is responsive to said electrical biasing condition for creating an electric field having an intensity characterized by a continuous function on a graph, said graph having an ordinate constituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said function having a discontinuous first derivative at at least one predetermined point, said function having a negative slope at all points other than said predetermined point; and
said second portion is responsive to said electrical biasing condition for creating an electric field having an intensity characterized by a continuous function on a graph, said graph having an ordinate constituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said function having a negative and continuous first derivative at all points.
7. A five-region semiconductor device comprising:
a) first and second semiconductor regions defining a first p-n junction;
b) a semiconductor means forming a second p-n junction with said second semiconductor region, said semiconductor means including a first portion responsive to an electrical biasing condition for creating an electric field the intensity of which is characterized by at least first and second intersecting lines on a first graph, said first graph having an ordinate constituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said first line having a first slope, said second line having a second slope, said first slope being negative, said second slope being more negative than said first slope; and a second portion responsive to said electrical biasing condition for creating an electric field the intensity of which is characterized by a third line on a second graph, said second graph having said ordinate and said abscissa, said third line having said first slope; and
c) a fifth semiconductor region defining a third p-n junction with said semiconductor means.
8. A five-region semiconductor device comprising:
a) first and second semiconductor regions defining a first p-n junction;
b) a semiconductor means forming a second p-n junction with said second semiconductor region, said semiconductor means including a first portion responsive to said electrical biasing condition for creating an electric field having an intensity characterized by a continuous function on a graph, said graph having an ordinate consituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said function having at least one discontinuous first derivative at a predetermined point, said function having a negative slope at all points other than said predetermined point; and a second portion responsive to said electrical biasing condition for creating an electric field having an intensity characerized by a continuous function on a graph, said graph having an ordinate constituting a measure of said intensity and having an abscissa constituting a measure of the distance from said second p-n junction, said function having a negative and continuous first derivative at all points; and
c)a fifth semiconductor region defining a third p-n junction with said semiconductor means.
9. A body of semiconductor material comprising:
a) top and bottom surfaces and an edge extending between said top and bottom surfaces;
b) a first semiconductor layer between said top and bottom surfaces;
c) a second semiconductor layer in said first semiconductor layer and forming a first p-n junction therewith, said second semiconductor layer having a surface coplanarwith said top surface, a portion of said first semiconductor layer extending to said top surface about said second semiconductor layer;
d) a third semiconductor layer adjacent said first semiconductor layer and forming a second p-n junction therewith; ;
e) a fourth semiconductor layer in said third semiconductor layer and forming an interface therewith, a portion of said third semiconductor layer extending to said bottom surface about said fourth semiconductor layer, said third semiconductor layer having a first impurity concentration, said fourth semiconductor layer having a second impurity concentration;
f) a fifth semiconductor layer in said fourth semiconductor layer and forming a third p-n junction therewith, said fifth semiconductor layer having a surface coplanar with said bottom surface, a portion of said fourth semiconductor layer extending to said bottom surface about said fifth semiconductor layer and
10.A body of semiconductor material according to claim 2 wherein:
a) said first p-n junction terminates at said top surface;
b) said second p-n junction terminates at said edge; and
c) said interface and said third p-n junction terminates at said bottom surface.
11. A body of semiconductor material comprising:
a) top and bottom surfaces and an edge extending between said top and bottom surfaces;
b) a first semiconductor layer having a first conductivity type;
c) a second semiconductor layer in said first semiconductor layer, said second semiconductor layer having a second conductivity type, said second semiconductor layer having a surface coplanar with said top surface, a portion of said first semiconductor layer extending to said top surface about said second semiconductor layer;
d) a third semiconductor layer adjacent said first semiconductor layer, said third semiconductor layer having said second conductivity type;;
e) a fourth semiconductor layer in said third semiconductor layer, said fourth semiconductor layer having said second conductivity type, a portion of said third semiconductor layer extending to said bottom surface about said fourth semiconductor layer; and
f) a fifth semiconductor layer in said fourth semiconductor layer, said fifth semiconductor layer having said first conductivity type, said fifth semiconductor layer having a surface coplanar with said bottom surface, a portion of said fourth semiconductor layer extending to said bottom surface and surrounding the surface of said fifth semiconductor layer.
12. A body of semiconductor material comprising:
a) top and bottom surfaces and an edge extending between said top and bottom surfaces;
b) a first semiconductor layer having a first conductivity type, a first impurity concentration, and a first thickness;
c) a second semiconductor layer in said first semiconductor layer and forming a first p-n junction therewith, said first p-n junction terminating at said top surface, said second semicondcutor layer having a second semiconductivity type, a second impurity concentration, and a second thickness less than said first thickness, said second semiconductor layer having a ring-type configuration such that said first p-n junction has at said top surface an inner circumference and an outer circumference larger than said inner circumference, a middle portion of said first semiconductor layer extending to said top surface inside said inner circumference, a side portion of said first semiconductor layer extending to said top surface between said outer circumference said edge, said second semiconductor layer having a surface coplanar with said top surface.
d) a third semiconductor layer adjacent said first semiconductor layer and forming a second p-n junction therewith, said second p-n junction terminating at said edge, said third semiconductor layer having said second conductivity type, a third impurity concentration, and a third thickness;
e) a fourth semiconductor layer in said third semiconductor layer and forming an interface therewith, said interface terminating at said bottom surface, said fourth semiconductor layer having said second conductivity, a fourth impurity concentration, and a fourth thickness, said interface having at said bottom surface an inner circumference and an outer circumference, said outer circumference bounded by said interface, said third semiconductor layer extending to said bottom surface about said fourth semiconductor layer; and
f) a fifth semiconductor layer in said fourth semiconductor layer and forming a third p-n juncton therewith, said third p-n junction terminating at said bottom surface and bounding the inner circumference of said fourth semiconductor layer, said fifth semiconductor layer having said first conductivity type, a fifth impurity concentration, and a fifth thickness, said fifth semiconductor layer having a surface coplanar with said bottom surface.
13. A body of semiconductor material ccording to claim 12 wherein the inner and outer circumference of said fourth semiconductor layer are both concentric with said second semiconductor layer.
14. A semiconductor body according to caim 12 further including:
a sixth semiconductor layer in said third semiconductor layer and forming a fourth p-n junction therewith, said fourth p-n junction terminating at said bottom surface, said fourth p-n junction having at said bottom surface an inner circumference and having an outer circumference larger than said inner circumference, the inner circumference of said sixth semiconductor layer larger than the outer circumference of said interface, the outer circumference of said sixth semiconductor layer a first distance from said edge, said sixth semiconductor layer having said first conductivity type, said fifth impurity concentration, said fifth thickness, and having a surface co-planar with said bottom surface.
15. A body of semiconductor material according to claim 13 wherein the inner and outer circumferences of said sixth semiconductor layer are both concentric with said second semiconductor layer.
16. A semiconductor body according to claim 13 wherein:
said edge is negatively bevelled such that a first angle measured within said semiconductor body between said edge and said top surface is acute and a second angle measured within said semiconductor body betwen said edge and said bottom surface is obtuse.
17. A semiconductor thyristor comprising:
a) top and bottom surfaces and an edge extending between said top and bottom surfaces;
b) a first semiconductor layer having a first conductivity type, a first impurity concentration, and a first thickness;
c) a second semiconductor layer in said first semiconductor layer and forming a first p-n junction therewith, said first p-n junction terminating at said top surface, said second semiconductor layer having a second semiconductivity type, a second impurity concentration, and a second thickness less than said first thickness, said second semiconductor layer having a ring-type configuration such that said first p-n junction has at said top surface an inner circumference and an outer circumference larger than said inner circumference, a middle portion of said first semiconductor layer extending to said top surface inside said inner circumference, a side portion of said first semiconductor layer extending to said top surface between said outer circumference and said edge, said second semiconductor layer having a surface coplanar with said top surface;
d) a third semiconductor layer adjacent said first semiconductor layer and forming a second p-n junction therewith, said second p-n junction terminating at said edge, said third semiconductor layer having said second conductivity type, a third impurity concentration, and a third thickness;;
e) a fourth semiconductor layer in said third semiconductor layer and forming an interface therewith, said interface terminating at said bottom surface, said fourth semiconductor layer having said second conductivity, a fourth impurity concentration, and a fourth thickness, said interface having at said bottom surface an inner circumference and an outer circumference, said outer circumference bounded by said interface, said third semi-conductor layer extending to said bottom surface about said fourth semiconductor layer;;
f) a fifth semiconductor layer in said fourth semiconductor layer and forming a third p-n junction therewith, said third p-n junction terminating at said bottom surface and bounding the inner circumference of said fourth semiconductor layer, said fifth semiconductor layer having said first conductivity type, a fifth impurity concentration, and a fifth thickness less than said fourth thickness, said third p-n junction layer having a circumference colinear with the inner circumference of said fourth semiconductor layer and having a surface coplanar with said bottom surface; ;
g) a cathode electrode having inner and outer circumferences and disposed on said top surface concentric with said second semiconductor layer, the inner circumference of said cathode electrode larger than the inner circumference of said second semiconductor layer, the outer circumference of said cathode electrode larger than the outer circumference of said second semiconductor layer;
h) a gate electrode having a circumference and disposed on said top surface concentric with said second semiconductor layer, the circumference of said gate electrode smaller than the inner circumference of said second semiconductor layer; and
i) an anode electrode having a circumference and disposed on said bottom surface concentric with said second semiconductor layer, the circumference of said anode electrode smaller than the inner circumference of said fourth semiconductor layer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2165979A | 1979-03-19 | 1979-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2045000A true GB2045000A (en) | 1980-10-22 |
Family
ID=21805453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8009260A Withdrawn GB2045000A (en) | 1979-03-19 | 1980-03-19 | An asymmetric thyristor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2045000A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0039509A2 (en) * | 1980-05-06 | 1981-11-11 | Siemens Aktiengesellschaft | Thyristor with high blocking voltage and method of making same |
| EP0144876A2 (en) * | 1983-12-07 | 1985-06-19 | BBC Brown Boveri AG | Semiconductor device |
| EP0343797A1 (en) * | 1988-05-25 | 1989-11-29 | Powerex, Inc. | Field grading extension for enhancement of blocking voltage capability of high voltage thyristor |
| EP0399476A2 (en) * | 1989-05-26 | 1990-11-28 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Thyristor |
| WO1998057377A1 (en) * | 1997-06-11 | 1998-12-17 | Abb Research Ltd. | A semiconductor device with a junction termination and a method for production thereof |
-
1980
- 1980-03-19 GB GB8009260A patent/GB2045000A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0039509A2 (en) * | 1980-05-06 | 1981-11-11 | Siemens Aktiengesellschaft | Thyristor with high blocking voltage and method of making same |
| EP0039509A3 (en) * | 1980-05-06 | 1982-04-07 | Siemens Aktiengesellschaft | Thyristor with high blocking voltage and method of making same |
| EP0144876A2 (en) * | 1983-12-07 | 1985-06-19 | BBC Brown Boveri AG | Semiconductor device |
| EP0144876A3 (en) * | 1983-12-07 | 1985-07-03 | Bbc Aktiengesellschaft Brown, Boveri & Cie. | Semiconductor device |
| EP0343797A1 (en) * | 1988-05-25 | 1989-11-29 | Powerex, Inc. | Field grading extension for enhancement of blocking voltage capability of high voltage thyristor |
| EP0399476A2 (en) * | 1989-05-26 | 1990-11-28 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Thyristor |
| EP0399476A3 (en) * | 1989-05-26 | 1992-10-14 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG | Thyristor |
| WO1998057377A1 (en) * | 1997-06-11 | 1998-12-17 | Abb Research Ltd. | A semiconductor device with a junction termination and a method for production thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |