GB2042812A - Artificial electromagnetic delay lines - Google Patents

Abstract

An artificial delay line, suitable for operation at microwave frequencies and for fabrication in miniaturised form, comprises a substrate (1) bearing first and second electrically insulated conductive layers (3, 11) providing alternating spaced locations of capacitive and inductive impedance. The layers (3, 11) are arranged on either side of a layer (9) of dielectric material, the overlapping portions providing shunt capacitance and the loops joining these portions providing series inductance. Concentration of capacitance may also be achieved by variation of dielectric constant or thickness of layer (Figs. 7, 8). Straight inductive strips alternating with capacitive electrodes are described (Fig. 6). <IMAGE>

Description

SPECIFICATION Artificial electromagnetic delay lines This invention relates to artificial delay lines.

It is an object of the present invention to provide an artificial electromagnetic delay line suitable for operation at microwave frequencies and suitable for fabrication in miniaturised form.

According to the present invention an artificial delay line comprises: a first electrically conductive layer; and a second electrically conductive layer electrically insulated from the first layer; the two layers together providing, at each of a plurality of spaced locations, a capacitive impedance constituting a shunt capacitance of the delay line, and the parts of the first layer andlor the second layer between each adjacent pair of said locations providing inductive impedances constituting series inductances of the delay line.

The two conductive layers may be carried by a substrate.

In one particular arrangement in accordance with the invention the two layers are in the form of conductive tracks which at each said spaced location overlap and are separated by a layer of dielectric material. The dielectric layers may be constituted by respective parts of a single continuous layer.

In a preferred form of such an arrangement portions of one track between the overlapping portions are arranged to be tightly inductively coupled with similar portions of the other track.

In one such preferred particular arrangement each track comprises a series of spaced first portions each adjacent pair of which is electrically inter-connected by a respective U-shaped second portion with successive second portions extending outwardly from the series of spaced first portions in opposite directions, the spaced first portions of the one track respectively overlapping the spaced first portions of the other track with the second portions of one track lying in the spaces between alternate second portions of the other track and vice versa. In such an arrangement the first and second portions are suitably of rectangular form.

In a second particular arrangement in accordance with the invention, the first layer is of generally planar form, and the second layer is in the form of a track overlying the first layer and separated therefrom by a dielectric layer all along its length.

In one such second particular arrangement, in order to provide the required capacitive impedance at each said spaced location said track is of increased width at each said spaced location.

In another such second particular arrangement, in order to provide the required capacitive impedance at each said spaced location the dielectric layer is of reduced thickness at each said spaced location.

In a further such second particular arrangement, in order to provide the required capacitive impedance at each said spaced location the dielectric layer is of increased dielectric constant at each said spaced location.

Four delay lines in accordance with the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a plan view of a section of the first delay line; Figure 2 is a sectional view along the line Il-Il in Figure 1; Figures 3 and 4 illustrate separately two conductors incorporated in the delay line of Figure 1; Figure 5 is a diagram of the equivalent circuit of the delay line of Figure 1; and Figures 6, 7 and 8 are perspective views of the second, third and fourth delay lines respectively.

Referring to Figures 1 to 4 of the drawings, the first delay line to be described is constructed on a substrate 1 of suitable electrically insulating material such as quartz.

On one main face of the substrate 1 there is disposed a metallised track 3 (see also Figure 3).

The track 3 comprises a series of spaced identical square portions 5 each adjacent pair of which is electrical!y connected by a respective rectangular U-shaped loop 7, successive loops 7 extending outwardly from the series of square portion 5 in opposite directions. Each loop 7 thus comprises three limbs A, B, and C, as indicated in Figure 3.

Overlying the track 3 and the surrounding substrate surface there is a thin iayer 9 of dielectric material, such as silicon dioxide.

On the exposed surface of the dielectric layer 9 there is a second metallised track 11 (see also Figure 4) which is identical in shape with the first track 3. The square portions 13 of the second track overlie and are in register with the square portions 5 of the first track and the loops 1 5 on the second track lie in the spaces between alternate loops 7 on the first track 3 and vice versa.

In operation an input signal is applied between one pair of corresponding ends of the two tracks 3 and 11 and an output signal is derived from hetween the other pair of corresponding ends.

Referring to Figure 5, each pair of overlapping square portions'5 and 13 with the intervening portion of the layer 9 constitutes a respective shunt lumped capacitance C of the delay line, and the limbs A, B and C of each of the loops 7 and 15 constitute respective series inductances LA, LB and LC. The total inductance per section of the line is further increased due to tight inductive coupling M between the limb A of each loop 7 or 1 5 and the limb C of the adjacent loop 1 5 or 7. Taking LA = LB = LC =M, the total inductance per section thus approaches 10 LA.

In one particular design, the dimensions of the delay line are as follows: Thickness of tracks 3 and 11 1 ssm Thickness of dielectric layer 9 (SiO2) 0.5 ym WidthoflimbsA,B,Cof loops 7 and 15 35 'um Length of sides of square portions 5 and 13 70 ssm Outside length of limbs A 78 ,um Outside length of limbs B 95 ym Outside length of limbs C 78 ,um With these dimensions a capacitance of 0.32 pF and inductance of 0.2 nH per section of the delay line is obtained.

For a 25 ohm, 10 ns delay line having a cut-off frequency of 40 GHz, 1257 sections are required.

For tracks 3 and 11 consisting of silver, the calculated insertion loss of the delay line is 33 dB.

To accommodate the 1257 sections in line, a substrate of length 12.0 cms is required. However, by folding the line along its length, it may be accommodated on a substrate 0.6 cm square.

To reduce insertion loss amplifying stages, e.g.

comprising field effect transistors, may be provided at points along the length of the delay line.

It will be appreciated that the structure results in a balanced delay line but suitable microstrip baluns may easily be provided at the ends of the line if required.

Similarly quarter wave impedance matching transformers may be provided at the ends of the line, if required. These may suitably be constructed as lengths of artificial delay line of the same form as the main delay line.

Referring now to Figure 6, the second delay line to be described comprises a substrate 1 7 of insulating material the whole of one main face of which is covered by a metallised layer 1 9.

Overlying the layer 19 there is a thin layer 21 of dielectric material and on the exposed surface of the dielectric layer there is a metallised track 23.

The track 23 comprises a series of regularly spaced rectangular portions 23A which are interconnected by portions 23B of relatively small width.

In operation an input signal is applied between one end of the track 23 and the layer 19 and an output is derived from between the other end of the track 23 and the layer 1 9.

Each of the portions 23A of the track 23 with the underlying part of the layer 1 9 and the intervening part of the dielectric layer 21 presents a shunt capacitive impedance to the applied signal, whilst the interconnecting portions 23B provide ssries inductive impedances to the applied signal.

Thus the arrangement operates as an artificial delay line.

Referring now to Figure 7, the third delay line comprises a substrate 25, and a plane conductive layer 27 as in the arrangement of Figure 6.

Overlying the layer 27 there is a layer 29 of dielectric material which at regularly spaced locations has square portions 29A of reduced thickness. On the exposed surface of the dielectric layer 29 there is a metallised track 31 which is of uniform width along its length and extends centrally across each portion 29A of the dielectric layer 29.

The portions 31 A of the track 31 on the portions 29A of the dielectric layer together with the underlying parts of the layer 27 provide the required shunt capacitive impedances of the delay line and the portions 31 B of the track interconnecting the portions 31 A provide the required series inductive impedances.

Referring to Figure 8, the fourth delay line comprises a substrate 33, and a planar conductive layer 35 as in Figures 6 and 7, and a conductive track 37 of uniform width, as in Figure 7.

However, in this delay line there is provided between the layer 35 and the track 37 a dielectric layer 39 which is of uniform thickness throughout, but of relatively high dielectric constant in square areas 39A spaced regularly along the length of the track 37.

The required shunt capacitive impedances are thus provided by the portions 37A of the track on the areas 39A of the dielectric layer together with the underlying parts of the layer 35, whilst the parts 378 of the track 37 interconnecting the portion 37A provide the required series inductive impedances.

In the delay lines described above by way of example the substrates serve only as supports. In other delay lines in accordance with the invention the dielectric layer and/or the conductive layers may have sufficient mechanical strength to render a substrate unnecessary.

Claims (12)

1. An artificial delay line comprising: a first electrically conductive layer; and a second electrically conductive layer electrically insulated from the first layer; the two layers together providing, at each of a plurality of spaced locations, a capacitive impedance constituting a shunt capacitance of the delay line, and the parts of the first layer and/or the second layer between each adjacent pair of said locations providing inductive impedances constituting series inductances of the delay line.

2. An artificial delay line according to Claim 1 wherein the two layers are in the form of conductive tracks which at each said spaced location overlap and are separated by a layer of dielectric material.

3. An artificial delay line according to Claim 2 wherein the dielectric layers are constituted by respective parts of a single continuous layer.

4. An artificial delay line according to Claim 3 wherein portions of one track between the overlapping portions are arranged to be tightly inductively coupled with similar portions of the other track.

5. An artificial delay line according to Claim 4 wherein each track comprises a series of spaced first portions each adjacent pair of which is electrically interconnected by a respective Ushaped second portion with successive second portions extending outwardly from the series of spaced first portions in opposite directions, the spaced first portions of one track respectively overlapping the spaced first portions of the other track with the second portions of one track lying in the spaces between alternate second portions of the other track and vice versa.

6. An artificial delay line according to Claim 4 wherein the first and second portions are of rectangular form.

7. An artificial delay line according to Claim 1 wherein the first layer is of generally planar form, and the second layer is in the form of a track overlying the first layer and separated therefrom by a dielectric layer all along its length.

8. An artificial delay line according to Claim 7 wherein in order to provide the required capacitive impedance at each said spaced location said track is of increased width at each said spaced location.

9. An artificial delay line according to Claim 7 wherein in order to provide the required capacitive impedance at each said spaced location the dielectric layer is of reduced thickness at each said spaced location.

10. An artificial delay line according to Claim 7 wherein in order to provide the required capacitive impedance at each said spaced location the dielectric layer is of increased dielectric constant at each said spaced location.

11. An artificial delay line according to any one of the preceding claims wherein the two conductive layers are carried by a substrate.

12. An artificial delay line substantially as hereinbefore described with reference-to Figures 1 to 5, Figure 6, Figure 7 or Figure 8 of the accompanying drawings.