GB2042776A - Improvements in or relating to digital data recording and decoding systems - Google Patents

Abstract

A digital data recording and decoding system is particularly applicable to single track magnetic recording and decoding. The recording system includes means for dividing a data stream into n bit length data words (where n is an integer), and a parity generator for generating for each data word a parity bit to be appended to the data word to form a primary codeword wherein the parity bit is generated from n spaced bits of the data stream preceding the data word, and wherein the spacing between the spaced bits corresponds to m data words plus one bit, where m is an integer and is sufficiently large to avoid a burst error from spanning two or more spaced bits. The decoding system for decoding data recorded by the recording system includes a plurality of shift registers in series for serial reception of the primary codewords, wherein each shift register has a bit length of m(n+1)+1 and has a correction register connected thereto, and means for applying correction signals via the correction register to erroneous data bits of the primary codewords when the parity bits are at the shift register inputs.

Description

SPECIFICATION Improvements in or relating to Digital Data Recording and decoding systems.

The present invention relates to digital data recording and decoding systems and particularly relates to single track magnetic recording and decoding systems with error detection and correction facilities.

In a digital recording system a single bit error can result in a large change in the value of the word which includes the error. Such errors arise either as flaws in the physical properties of the recording tape or as dropouts i.e.: faults arising in the interface between a magnetic tape and a recorder head due to, for example, the presence of foreign matter such as dust located between the head and the tape.

Errors often occur in clusters or bunches separated by relatively long error free runs of data, and are termed 'burst errors'.

One solution which has been employed to detect and correct errors in digital data systems includes the use of multitrack recording tape with redundant tracks where it is assumed that if only one track includes an error in a given period than another parallel track on the tape will contain the correct digital information for the period. Such a system uses a large number of redundant tracks. For example, a multichannel recording system which employs this solution uses twelve channels and three parallel tracks per channel, and of these twenty four tracks are redundant.

The present invention provides systems with error detection and correction facilities suitable for use with single track tape.

According to the present invention a data recording system includes, means for dividing a data stream into n bit length data words (where n is an integer), a parity generator for generating for each word a parity bit to be appended to the word to form a primary codeword wherein the parity bit is generated from n spaced bits of the stream preceding the word, and wherein the spacing between the spaced bits corresponds to m data words plus one bit, where m is an integer and is sufficiently large to avoid a burst error from spanning two or more spaced bits.

Preferred values of n and m are n = 12 and m = 80. In general, values of n and m are chosen so that the expected maximum burst error length cannot span two spaced bits and thus each primary codeword is either correct or contains only one erroneous bit. The erroneous bit in each primary codeword may be corrected by parity error correction provided that the position of the erroneous bit is first determined. For a codeword m1m2m3m4p where p = m, m2 m3 m4.

A parity check is performed thus:~ C = m, m2 m3 m4 p and if an error is suspected in m1, put m, = O, so that C = m2 m3 m4 p and, substituting for p, C = m2 m3 m4 m, m2 m3 m4.

If a modulo two addition is performed C=m1, i.e.: the result of the parity check C can be used to replace the erroneous bit.

In order to enable the position of an erroneous bit of a codeword to be determined the data handling system for single track recording may further include a first Hamming code generator for generating a first codeword from a group of the primary codewords, and means for appending the first codeword to the group of the codewords to form a first coded group.

According to a further aspect of the invention the data recording system further includes, a second Hamming code generator for generating a second codeword from the first coded group, means for appending the second codeword to the first coded group to form a second coded group, a third Hamming code generator for generating a third codeword from the second coded group, thereby forming a dual Hamming code, and means for appending the third codeword to the second coded group to thereby form a third coded group.

Hamming codes produce a binary sequence when they are decoded called a syndrome which indicates error position. An error pattern must correspond to a unique state of the syndrome so that it can be identified. The dual Hamming code enables multiple errors to be diagnosed as single bit errors occurring in a different position from the actual error or errors. The relative position of the actual error pattern and its indicated error is a function only of the generator polynomial used to generate the code and is independent of the absolute position of the error, provided it is confined entirely within the codeword. If two parity words are generated for the same data block, therefore, using different generator polynomials, the indicated positions of single bit errors will be the same, whereas those for multiple errors will be different.It is thus only necessary to compare two indicated error positions to distinguish between a single error and a multiple bit error. If a first parity word generated is included in the block of a second, single errors occurring within the first parity word can also be corrected. Greater elaboration is required, however, if single errors occurring in the second word are to be recognised as such. The multiple error detection properties of this code are good, since to remain undetected, an error must correspond to a codeword of both systems, i.e.: it must be divisible by both generator polynomials.

Since the generator polynomials are by definition irreducible, they can have no common factors, hence their lowest common multiple is obtained by multiplying them together. This means that the parity words will have the same effect as one word of twice the length when used for burst error detection, i.e.

the probability of a random burst error not being detected by the code is:

where r = the length of each parity word.

The data recording system may further include interleaving means for interleaving the bits of each group of primary codewords so that each bit of a primary codeword is separated from its neighbouring bit by a plurality, p, of bits from other primary codewords of the group. In a preferred embodiment p = 3.

According to the present invention a decoding system for decoding data recorded on a recording system in accordance with the invention includes a plurality of shift registers in series for serial reception of the primary codewords, wherein each register has a bit length of m (n + 1) + 1, and has a correction register corrected thereto, and means for applying correction signals via said correction registers to erroneous data bits of the primary codewords when the parity bits are at the shift register inputs.

The decoding system may also include means for deriving a first syndrome from each of the first codewords for indicating the position of erroneous bits in groups of the primary codewords.

The decoding system may further include as a primary correction stage, parity divider means for deriving from the second and third codewords second and third syndromes respectively, means for deriving a multiple error syndrome from the second and third, syndromes, a comparator for comparing the derived multiple error syndrome with stored syndromes and for producing an output error pattern associated with the one of the stored syndromes which corresponds to the derived multiple error syndrome.

The comparator may include a read only memory which is programmed to recognise multiple error syndromes corresponding to multiple error conditions which it is required to correct.

The decoding system may further include an error correction circuit and error position correction circuit, each arranged to receive error pattern output from the comparator. The error correction circuit adds the difference between the apparent error position and the actual error position to one of the second and third syndromes to obtain the actual position of the error. The comparator may be programmed to detect as many error conditions as there are multiple error syndromes but this requires an increase in the complexity of the correction circuitry to correct all the detected error conditions.

Further, each burst error condition corrected reduces multiple error detection capability since a family of errors exist for every multiple error syndrome, and the use of the syndrome to detect a multiple error condition implies that a correctable error condition has occurred.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawing of which:~ Figure 1 is a diagram which illustrates the formation of a codeword in accordance with the invention.

Figure 2 is a diagram which illustrates the formation of a frame from codewords of Figure 1.

Figure 3 is a diagram which illustrates the formation of parity words A and B and the insertion of synchronisation information.

Figure 4 to 10 are schematic circuit diagrams of which:~ Figure 4 shows a recording system in accordance with the invention.

Figure 5 shows a parity bit generation circuit which forms parts of the system of Figure 4.

Figure 6 shows a module-two division circuit using a generator polynominal x8 + x4 + x3 + X2 + 1.

Figure 7 shows a further module-two division circuit using a generator polynominal x8 + xss + x5 + X4 + 1.

Figure 8 shows an interleaving circuit used in the recording system of Figure 4.

Figure 9 shows an interleaving store write circuit which forms part of the circuit of Figure 8.

Figure 10 shows an interleaving store read circuit which also forms part of the circuit of Figure 8.

Figure 11 is a flow chart showing error correction logic used in a decoding system in accordance with the invention.

Figure 12 is a continuation of the flow chart of Figure 11.

Figure 13 is a flow chart showing syne word detection logic used in a search mode of the decoding system.

Figure 14 is a flow chart showing sync word detection logic used in a run mode of the decoding system.

Figure 1 5 is a graph which shows the theoretical response of the decoding system to random single errors.

Figure 16 is a graph which shows the theoretical response of the decoding system to burst errors.

Figure 17, 19, 20 and 21 are schematic circuit diagrams of which.~ Figure 17 shows sync word detection and frame recognition circuits of the decoding system.

Figure 19 shows error detection and correction circuits of the recoding system.

Figure 20 shows the primary correction circuit of the decoding system.

Figure 21 shows the secondary correction circuit of the decoding system.

Figure 18 shows a histogram of a pattern of co-incidences between sync words and rasks for worst case data.

Figure 1 shows the formation of a codeword 232 from a 12 bit data word by the addition of a parity bit, p. The parity bit, p, is formed by parity operation on 12 bits of preceding data stream (not shown), each of the bits being (80 x 12) + 1 bits from its neighbouring bit.

Figure 2 shows the formation of a group 234 of sixteen of the codewords from which an 8 bit check word, parity word C, is formed using the generator polynominal, x8 + X4 + x3 + x2 + 1. The parity word C and 8 bit word, D, comprising documentary data is appended to the group to form a frame 235.

Referring to Figures 4 and 5, a parity bit generator circuit for generating parity bits from a digital data stream includes a parity bit generation register 3 which comprises twelve 1041-bit shift registers, 19 to 30, connected to an input line 1 and to one another in series, and a parity bit generator 16 comprising eleven modulo-two adders, 31 to 41, and having inputs from a corresponding one of the shift register as shown in Figure 5. Parity bits, p, generated by the generator 16 by modulo-two addition are fed into shift register 19 via a two-way multiplexer 2, after the entry of each 12-bit data word from the data stream. An input data stream ....M(i)M(i+1)M(i+2)....

becomes M(i) p(i) M(i + 1) p(i + 1) M(i + 2) p(i + 2) where Mi = M(i,1) M(i,2) .... M(i,1 2) and p(i) = M(i-80,1 2) ~ M(i-1 60,11) ~.... M(i-880,2) i) M(i-960,1).

Each data bit associated with a given parity bit comes from a different word to provide spreading of bits required for burst error correction without spreading the data words themselves. The number of data words affected by burst errors is minimised by using the above described circuit.

The output from the parity generation register 3 is fed to a parity word divider,15, which includes a modulo-two division circuit shown in Figure 6. The divider 1 5 divides the stream of words and appended parity bits from the register 3 into sets of sixteen words, termed frames, F. For the jth frame: Fl = fJ(1)fj(2) .... f(208) and Fj = M(1)p(1) My(2) Pj(2) .... My(16) p(16).

These frames are then used as blocks for the generation of a Hamming code, using a generator polynominal, x8 + x4 + x3 + x2 + 1.

The modulo-two division circuit shown in Figure 6 includes eight D-type bistable elements 287a to 287h, and four modulo-two addition elements 285, 288, 289 and 290 connected as shown in Figure 6 so as to produce an eight-bit parity word, C, (designated C for the jth frame). Referring to Figure 4, the output from the parity word divider 1 5 and from the parity generation register, together with a second eight-bit word, D, are fed via a three way multiplexer, 5, to interleaving means 6 which applies four-way bit interleaving of the output from the multiplexer 5 which may be represented by FjD,C,F,+t D,+1 Cj+1 F,+2 Dj+2Cj+.....

The word D includes documentary data for controlling de-multiplexing operations.

The operation of interleaving may be represented by a 52 x 4 matrix:

di(1) Mi(1) Pj( 1) d1(2) Mj(2) pj(2) dj(3) Mj(3) p(3) dj(4) M(4) p(4) dj(5) M1(5) p(5) d(6) M(6) p(6) d(7) M(7) Pj(7) d(8) M(8) p(8) c(1) M1(9) p(9) c(2) M(10) p1(lO) c1(3) Mj(11) pj(11) cj(4) Mj(12) p(12) c1(5) Mj(13) p(13) c(6) M1(l4) p(14) cj(7) M(15) p(15) c(8) M1(16) p(16) where M(i) = m(i,1), mj(1,2) .... m1(i,1 2) and each element of M(i) forms a separate column.

Interleaved frame F' may be obtained by reading sequentially down the columns of the matrix from left to right.

Four subframes G(1), G(2), G(3), G(4) may be formed from the rows of the 52 x 4 matrix above.

The above matrix for the jth frame may be written:

G(1) Gi(2) Gi(3) G(4) Referring to Figure 8, the interleaving is implemented using two 256 x 1 bit random access memories, rams, 269 and 282. Write and read processes for interleaving are illustrated with reference to Figure 9 which shows an interleaving store write circuit and Figure 10 which shows a corresponding read circuit.

Referring to Figure 9, during the write process, a memory address for each entry is selected by two counters 266 and 268. The counter 266 is a 4-bit presettable counter which has an input from a clock (not shown) via terminal 264 and a switch 265. During data entry from a terminal 273 the counter 266 is programmed to return to a count of three after reaching full scale to divide the clock rate by 2e3.

Since the data, including the parity bits, are in the form of 13-bit words M(i) p(i), the counter 266 always contains a fixed number for a data bit of given significance. At the end of a word, including its associated parity bit, the counter 266 is set to 3, and the other counter, 268, is incremented. On completion of the entry of 16 words in a given frame, the counter 266 is set to a value of two and the other counter 268 is reset. Eight documentary bits are now entered into the ram 269 via a three-way switch from an input 272. The counter 268 is incremented by one for each entry of the right bits. Parity word C, which is an 8-bit word, is then entered from a terminal 271 to the ram 269 via the switch 270 while the contents counter 266 remain at a value of 2 and counter 268 is incremented.

Referring to Figure 10, the memory addresses for the ram 282 are selected by counters 279, 280 and 281. Counters 279 and 281 divide by four counters, and counter 280 is programmed to return to a count of 2 at the end of its count and thus performs a divide by 14 function. It can be seen that the arrangement of counters shown in Figure 10 will result in the memory being read out in such an order as to produce frame F'.

Figure 8 illustrates how the rams 269 and 282 are connected so that they are each used for both write and read functions. The counters 266 and 268 of Figure 9 are shown as write address counters 70 and the counters 279, 280 and 281 of Figure 10 are shown as read address counters 71 in Figure 8.

To obtain a smooth data flow the reading and writing functions are required simultaneously, hence the rams 269 and 282 interchanger read/write functions at the end of each frame, the interchange being effected by a multiplexing circuit shown in Figure 8 which includes switches 72 and 73.

Parity words A and B are generated as follows:~ Referring to Fig. 3, two 8-bit parity words Aj and Bj are attached to the end of each interleved frame F'1. The block from which Fj is formed consists of: Gi-3(4)Gi-2(3)Gi-1(2)Gi(1), while Aj is formed from the same block plus the parity word B1, i.e.

Gj-3(4) G1#2(3) Gj-1(2) Gj(1) Bi Parity word Bj is formed by module two division of its blocks by x8 + xss + x5 + x4 + 1 by the circuit of Figure 7 which employs bistable elements 296a to 296h and modulo-two elements 292, 293, 294 and 295, while for Aj the reciprocal polynominal X8 + X4 + X3 + XZ + 1 is used (see Figure 6).

Referring to Figure 4, at the end of each frame a three bit identification count is added by counter 12 which increments by 1 for successive frames. The identification count is followed by a 13-bit Barker type sync word from a generator 9. The system timing is arranged so that the data stream is continuous at this point, the next frame following immediately after the end of the sync word as is shown in Fig 3.

The data stream is then ready for channel encoding and is of the following form.

.... F'jBjAPj S F'+1 Aj+ vj+1S where epj is the frame identification word for the jth frame.

whern0#O##7 and j+1 = j + 1 for 0 < Pj < 7 and#1+1=0 for = 7 and where S is the sync word.

The decoding system for decoding data recorded on the recording system described above employs a primary and secondary correction system which enables small errors to be corrected prior to the large burst error correction. This minimises the loss of burst error correction performance in conditions where, due to pattern sensitivity or jitter, the incidence of small burst or single-errors is higher than normal.

Small errors are detected and corrected by parity words A and B in the primary correction system.

Error combinations not correctable at this point will generally also be detected by parity word C. The information derived from the parity words A, B and C enable the error to be located to within groups of four words, for correcting by the secondary system.

Large burst errors will generally cause mis-clocking and are detected by sync detection circuitry.

This will result in an integral number of frames requiring correction by the secondary correction system.

In the primary correction system parity words A and B form a dual Hamming code which is used to correct single bit errors and small burst errors. Burst errors of up to three bits, i.e. error patterns 1, 11, 101, are converted in programmed decoder. The parity words are attached to a convolved block which extends over four frames. Each bit in the block is separated from the next by at least three bits, thus burst errors of twelve bits can be tolerated in the data as only three adjacent bits of any block are affected.

It would be possible to apply the convolved block of parity words A and B without first interleaving the data, with no loss of correction efficiency of the primary correction system. When uncorrectable errors were found, however, the affected block would encompass parts of 64 words, which would all require correction. By interleaving in such a fashion as to include whole words in the convolved blocks, the number of words affected by each block is reduced to 1 6, thus reducing the number of words required secondary correction as the result of small errors.

Parity word C is used only for error detection. As its block consists of a single complete frame of data, the four subframes included in a given parity word C block each come from a different parity word AB block. Thus if an error pattern occurs which cannot be corrected by the primary system, the erroneous frames are detected by parity word C, allowing the error to be located to groups of four words. An inportant function of parity word C is the detection of incorrect burst error corrections made by parity words A and B, since if the system makes a wrong assumption about the error pattern, the resulting erroneous blocks will be detected by parity word C.

Large burst errors will almost certainly cause mis-clocking of the replay signal. As a result, the frame(s) in which error has occurred will have an apparent 'shortening' (in terms of bit count), and the sync will not be recognised. Frames thus affected, and any frames failing the sync detection and frame recognition test will cause the sync detection circuitry to return to a search mode and will be flagged as erroneous throughout and require secondary correction.

The parity bits, p, are used for secondary correction. The subframes requiring correction are detected by the means described above. As each bit making up a given parity bit is separated from the other bits by 80 words and one bit, a burst error up to five frames long can be corrected, this length being is excess of that likely to occur in practice. The correction process is inhibited by a control circuit where more than one bit requires correction from one parity bit, as correction is not possible under these circumstances.

Error correction methods carried out during decoding are illustrated in Figures 11 and 12.

Referring to Figure 11, the first stage of decoding is the detection and checking of the synchronisation words. The validity of the data is checked by counting the number of bits separating the sync words.

This check shows up frames of incorrect length (in the data domain) which is usually caused by mis-clocking of channel decoders due to dropouts on the tape. A check carried out simultaneously on the frame identification count reveals the presence of sync words too badly corrupted to be detected by the sync detection circuits, and thus allows the system to determine the length of multiframe burst errors as illustrated in flow charts, Figures 13 and 14.

The dual Hamming code formed by parity words A and B is decoded by using decoding circuitry programmed to correct burst errors of up to three bits in length but as each bit of a given codeword is separated from the adjacent bit in the codeword by three bits from other codewords, due to the interleaving process employed during encoding, burst errors of up to 12 bits can be corrected at this stage. Errors which cannot be corrected by the dual Hamming code will generally be detected by it, thus the error position will be defined to within four subframes, each of which include four words, for each codeword in which an undetectable error occurs.

The next stage in the error detection/correction process is the decoding of the Hamming code having parity word C as its check bits which is illustrated in the flow chart of Figure 14. This code is used for error detection only and locates the error position to within one 16 word frame. Errors detected but not corrected by the dual Hamming code will also normally be detected by parity word C. By correlating the information obtained by these two tests, it is possible to define an erroneous region to within one or more four word subframes. The four subframes making up a frame will all be associated with different A and B parity word pairs, and each have a different pair of flags. If any of the four uncorrected error' flags are set, the correction request flag to the secondary correction system is set for the flagged subframes.If none of the 'uncorrected error' flags are set, any 'corrected error' flags which are set cause the 'correction request' flag for the appropriate subframes to be set in the event of an error being detected by parity word C. If none of the flags are set, correction of the entire frame is requested if parity word C indicates the presence of an error. If the sync/frame identification error flag is set, all the above is overridden, and the correction flags are set for all four subframes.

Erroneous subframes discovered inthe above test, and the frames which have failed the sync regognition tests are corrected using distributed parity bits, which allow any one of the bits associated with a given parity bit to be corrected. Assuming that about 1000 words of intact data are present on either side of the burst error, then the wide spacing of the parity bits allows burst errors of up to 80 words long to be corrected. This much greater than is likely to occur from dropouts. The theoretical performance of the system with random distributions of single errors and burst errors of the type 111-11 i.e. worst case burst errors, is illustrated in Figs. 15 and 16 respectively.

Referring to Figure 17, channel decoded replay data first enters a sync detection register assembly which includes a first 16-bit parallel output shift register 202, having an output to a 240-bit shift register 203 which has an output to a second 1 6-bit parallel output shift register 204. The sync detection register assembly has a total length of 272 bits having parallel outputs. Data is shifted serially through the register, and sync detection for frame j occurs when the register contains (Pl-1 S F'1B1A1(P15.

The sync words and frame identification words are at this time in the parallel output shift registers 202 and 204. Modulo-two addition of each of the sync words and a 'mask' consisting of a static patterns of the inverse of the sync word is carried out by adders 200 and 208. The output of the modulo-two adders 200 and 208 consists of 26 lines, each of which indicates the coincidence of a bit of the received sync words with the true sync word pattern. The outputs of the adders 200 and 208 are summed in a binary adder 197, each input being given a weight of 1. A comparator 196 then decides whether sufficient bits have been recognised for the sync to be labelled valid. Figure 18 shows a histogram of the worst case coincidence pattern for a typical sync word.A two level sync recognition system is used, initial recognition requiring both syncs to be error free (search mode), and subsequent detection being timed to the expected appearance of the sync words and allowing a total of four errors to occur in any two consecutive sync words (run mode). Frame identification counts are also used in sync verification, the loss of either one of two counts checked at any time being tolerated in the run mode. The detailed operation of the sync circuitry is shown in a flow chart given in Figures 13 and 14.

Frames which have failed the above test will often be in gross error, hence all such frames are flagged as erroneous throughout. The setting of this flag overrules the results of all subsequent error detection tests. In Figures 13 and 14, (PA denotes the frame identity count preceding frame. vB denotes the frame identity count following frame, and FC denotes the frame counter.

Referring to Figure 17, successfully identified frames are clocked into one of either 240-bit shift registers in an eight frame buffer store 209, the register selected being determined by the frame identification count. When frames are not identified, the register into which they would normally be clocked remains unloaded. The registers of the store 209 are read out in sequence, the unloaded registers providing a space in the data stream for the reconstituted data to be inserted.

Assuming that the data has been recorded on the tape using a self-clocking channel code the channel decoder will provide both the decoded data and a clock signal. This clock signal may, in principle, be used to operate the error detection and correction electronics. In practice, however, the clock signal will fail during drop-outs, causing mis-clocking and hence failure of the decoding electronics. To avoid this problem, it is necessary to use a locally generated clock signal. A clock generator 199 comprising a variable frequency oscillator whose frequency is controlled so as to keep a constant relationship between the clocking in and clocking out of the buffer store is used.

Referring to Figure 19, the primary correction system includes parity word A and B dividers 150 and 152 which operate over the same blocks that were used originally to generate the two parity words and also include the appropriate check bits. Remainders in the dividers are syndromes indicating the error condition of the respective blocks. Referring to Figure 20 the syndromes are separately decoded 256 x 8 bit Read Only Memories 169, 182 which output the apparent position of the error. The outputs are subtracted, and the result passed to the 'error type' decoder (a 256 x 4 bit ROM) 180. If a correctable error is detected, correction circuitry is activated and the 'detected and corrected' flag is set.

If the error is non-correctable the 'detected not corrected' flag is set. As parity words A and B are formed from the four frames preceding them, it is necessary to provide a store of this length for the data, since correction can only take place after the check words have been read.

Re-formatting stores 147 shown in Figure 19 are provided to return the data to the order it was in prior to the interleaving process.

The Hamming code having parity word C as it check bits is decoded using the circuit of Figure 6 which carries out modulo-two division by generator polynomial x8 + X4 + x3#+ X2 + 1. The syndrome is not used to locate a single bit error as is normal practice, but merely to test for the existence of an error.

The decoding of the syndrome thus consists only of an 8 input gate for testing all logical 0 conditions.

Referring to Figure 21, the secondary correction system consists of a main register comprising twelve 1041 bit shaft registers 51 a to 51 n each separated from the next by an arrangement of multiplexers 53a to 53n, 54b to 54m. In parallel with the 1041 bit registers are twelve 20 bit registers 56a to 56n, in which correction request flags for each subframe within the main register is held. The multiplexers are normally in the position shown in the Figure, but if a logical 1 appears at any one of taps 55a to 55n of the registers, 56 the multiplexers in the main register are switched thereby switching inputs of modulo-two adders 52e to 52m to a logical 0 and the input of the next register to the output of the modulo-two adder.Valid corrections can only be made once every 13 shifts, i.e. when a parity bit is at the input of the secondary correction register. The flags are therefore gated with a-correction enable line which inhibits corrections when data bits are at the input. A controller 57 detects the simultaneous presence of more than one correction request flag. When this condition occurs, the correction enable pulses are inhibited, and all the words in each subframe requesting correction at that time are flagged uncorrected.

The response of the system to isolated burst errors is now described.

Error in dataj parity bits and parity word C make up the interleaved frame F', and their error response is identical. Errors of t2 bits or less are corrected by the primary system. Errors greater than this will require some secondary correction, e.g. a 1 6-bit error will require secondary correction of up to four subframes.

The primary correction system can correct a burst error of three bits in parity word B which is not interleaved. Thus an error of four or more bits results in the primary system flagging an uncorrected error. As parity words A and B are not included in the block of parity word C, no error is found by parity word C, and no secondary correction is required.

For errors less than 13 bits, no correction is necessary of the error does not affect the subframe whose parity word B is in the frame which is always subframe 1. In the worst case, therefore, a 7-bit error could cause the correction of one subframe by the secondary system.

All errors in parity word A are uncorrectable by the primary system, but not secondary correction is required.

Loss of one frame identification count causes no error. If two successive frame identification counts are lose, the sync detection system goes into the search mode, and two frames require secondary correction.

Loss of four bits or less in any two successive sync words causes no error, regardless of their distribution. Loss of five bits or more results in two frames requiring secondary correction assuming that there are no sync or frame errors in the following two frames.

Large errors wholly within the data will cause the loss of one frame.

Since a large error will cause the sync detection system to go into the search mode, any error in the following sync word or frame identification count will cause the sync acquisition following the error to be invalidated, thus causing the loss of two frames.

Claims (12)

1. A digital data recording system including means for dividing a data stream into n bit length data words (where n is an integer), a parity generator for generating for each word a parity bit to be appended to the word to form a primary codeword wherein the parity bit is generated from n spaced bits of the stream preceding the word, and wherein the spacing between the spaced bits corresponds to m data words plus one bit, where m is an integer and is sufficiently large to avoid a burst error from spanning two or more spaced bits.

2. A data recording system as claimed in claim 1 further including a first Hamming code generator for generating a first codeword from a group of the primary codewords, and means for appending the first codeword to the group of the codewords to form a first coded group.

3. A data recording system as claimed in claim 2 further including a second Hamming code generator for generating a second codeword from the first coded group, means for appending the second codeword to the first coded gorup to form a second coded group, a third Hamming code generator for generating a third codeword from the second coded group, thereby forming a dual Hamming code, and means for appending the third codeword to the second coded group to thereby form a third coded group.

4. A data recording system as claimed in any of the preceding claims further including interleaving means for interleaving the bits of each group of primary codewords so that each bit of a primary codeword is separated from its neighbouring bit by plurality, p, of bits from other primary codewords of the group.

5. A data recording system as claimed in claim 4 wherein p = 3.

6. A decoding system for decoding data recorded on a recording system as claimed in any of the preceding claims including a plurality of shift registers in series for serial reception of the primary codewords, wherein each register has a bit length of m )n + 1) + 1, and has a correction register connected thereto, and means for applying correction signals via said correction register to erroneous data bits of the primary codewords when the parity bits are at the shift register inputs.

7. A decoding system as claimed in claim 6 further including means for deriving a first syndrome from each of the first codewords for indicating the position of erroneous bits in groups of the primary codewords.

8. A decoding system as claimed in claim 7 further including a primary correction stage comprising parity divider means for deriving from the second and third codewords second and third syndromes respectively, means for deriving a multiple error syndrome from the second and third syndromes, a comparator for comparing the derived multiple error syndrome with stored syndromes and for producing an output error pattern associated with the one of the stored syndromes which corresponds to the derived multiple error syndrome.

9. A decoding system as claimed in claim 8 wherein the comparator includes a read only memory which is programmed to recognise multiple error syndromes corresponding to multiple error conditions which it is required to correct.

10. A decoding system as claimed in claim 8 or claim 9 including an error correction circuit and an error position correction circuit, each arranged to receive error pattern output from the comparator.

11. A data recording system substantially as claimed herein and with reference to Figures t to 10 of the drawings.

Claim 12. A decoding system substantially as claimed herein and with reference to Figures 11 to 21 of the drawings.