GB2040616A - Improvements in and Relating to Electrical Circuit Arrangements - Google Patents
Improvements in and Relating to Electrical Circuit Arrangements Download PDFInfo
- Publication number
- GB2040616A GB2040616A GB8001168A GB8001168A GB2040616A GB 2040616 A GB2040616 A GB 2040616A GB 8001168 A GB8001168 A GB 8001168A GB 8001168 A GB8001168 A GB 8001168A GB 2040616 A GB2040616 A GB 2040616A
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- signal
- level
- control
- output
- circuit arrangement
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- 230000001419 dependent effect Effects 0.000 claims abstract description 17
- 230000008859 change Effects 0.000 claims abstract description 6
- 230000007423 decrease Effects 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 claims abstract description 4
- 230000004044 response Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000010079 rubber tapping Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
An A.G.C. circuit has first and second modulators 6, 8, and a control signal is applied to the modulator 6 through an impedance path C2, R4 having an impedance which decreases with increasing frequency, and is applied to the modulator 8 through an impedance path R5, C3 having an impedance which increases with increasing frequency. The modulators 6, 8 are connected in series to modulate the input signal and an amplifier 14 amplifies the output of the second modulator 8 and applies it to an output terminal 36. A detector 18 detects the output of the amplifier 14 and an integrator 28 compares the detected level with a reference so as to produce the control signal dependent on the error. In this way, modulator 6 performs modulation primarily dependent on the A.C. component of the control signal and modulator 8 performs modulation primarily dependent on its D.C. component of the control signal. Therefore, changes in the gain of the amplifier 14, or in the level of the input signal, which tend to alter the upper limit of the loop bandwidth of the circuit are substantially offset by the effect of the resultant change in the gain of the modulator 8. <IMAGE>
Description
SPECIFICATION improvements In and Relating To Electrical Circuit Arrangements
The invention relates to electrical circuit arrangements. One example of an electrical circuit arrangement to which the invention relates is an automatic gain control (AGC) circuit arrangement.
Various AGC circuit arrangements are known. However, a problem which can arise with known AGC circuit arrangements is that their bandwidth varies with gain and thus with the level of output signal for a given output. Where a wide loop bandwidth is required (e.g. to handle amplitude modulation up to 20 KHz or more), this variation of bandwidth can give rise to instability.
According to the invention, there is provided an automatic gain control circuit arrangement for producing an output signal which is dependent on an input signal and whose mean level has a desired value, comprising a signal path having an input for receiving the input signal and an output at which is produced the output signal, the signal path including control means controllable to vary the level of the signal in the signal path and amplifying means for amplifying the signal in the signal path, the circuit arrangement also including detecting means connected to sense the level of the signal in the signal path after its level has been varied by the control means and amplified by the amplifying means, and operative in response to variations of the sensed level from the desired value to produce a control signal dependent on the variations and which adjusts the control means in a sense such that it offsets the said variations, the control means comprising one part primarily responsive to the alternating component of the control signal and another part primarily responsive to the D.C. component of the control signal whereby changes in the gain of the amplifying means or in the level of the input signal which tend to alter the upper limit of the loop bandwidth of the circuit arrangement are substantially offset by the effect of the resultant change in the gain of the said other part of the control means.
According to the invention, there is also provided an automatic gain control circuit arrangement, comprising means for receiving an input signal, first modulating means connected to modulate the level of the input signal, second modulating means connected to modulate the output of the first modulating means, an amplifier for amplifying the output of the second modulating means and for applying it to an output terminal, a detector for detecting the level of the output of the amplifier, means operative to compare the detected level with a reference dependent on a desired value of the mean level of the signal produced at the output terminal whereby to produce a control signal dependent on the difference between the actual level of the output of the amplifier and the said desired value, and first and second frequency-dependent impedance paths for applying the control signal to the first and second modulating means respectively, one impedance path having an impedance which decreases with increasing frequency and the other impedance path having an impedance which increases with increasing frequency, whereby one modulating means performs modulation primarily dependent on the value of the alternating component of the control signal and the other modulating means performs modulation primarily dependent on the D.C. component of the control signal, so that the upper limit of the bandwidth of the circuit arrangement is substantially unaffected by changes in the gain of the amplifier or in the mean level of the input signal.
AGC circuit arrangements embodying the invention will now be described by way of example only and with reference to the accompanying diagrammatic drawings in which:
Figure 1 is a circuit diagram of one of the AGC circuit arrangements;
Fig. 2 is a Bode plot of the circuit arrangement of Fig. 1;
Figure 3 is a circuit diagram of another of the AGC circuit arrangements; and
Figure 4 is a circuit diagram of a further one of the AGC circuit arrangements.
In the following description, direct voltage signal components or constant amplitude signals are represented by upper case "V", together with a distinguishing subscript, while varying amplitude components of such direct current or constant amplitude signals are represented by a lower case "v" together with a distinguishing subscript.
The AGC circuit arrangement (Fig. 1) has an input terminal 5 at which is received the input signal Sl=Vl+v. The signal is passed to one terminal of a first modulator 6 which receives a modulating signal ci on a second input line 7. The output V6 of the modulator 6 is passed to the first input of a second modulator 8 which receives a modulating signal Sc2 on a second input line 12.
The output V8 of the second modulator 8 is passed through an amplifier 14 having an output line 1 6. The level of the signal V0 on the line 1 6 is sensed by a detector 18 which produces a resultant output on a line 20 which is applied through a resistor R2 to a point 23. Also applied to the point 23 is a reference signal 5r via a terminal 30 and a resistor R3. Therefore, the integrator input receives the algebraic sum of the signals applied to the point 23 through the resistors R2 and R3. Integrator 28 has an integrating capacitor C1 connected across it.
The output Sc of the integrator 28 provides the modulating signals SCa and Sc2 for the modulators 6 and 8. The signal Sc1 is produced via a capacitor C2 which is shunted by a resistor R4 connected to a bias supply (not shown) by a terminal 32. The signal Sc2 is produced via a resistor R5 which is shunted to ground by a capacitor C3. The result, therefore, is that the modulator 6 is responsive only to the alternating components of the signal Sc, while the modulator 8 is responsive only to the D.C. and low frequency components of the signal Sc.
The output signal, Vo, of the circuit arrangement is taken from a terminal 36 connected to the line 16 from the amplifier 14.
The AGC circuit of Figure 1 will now be analysed. In the analysis which follows, the following terms will be used (in addition to those mentioned above):
Sr=Vr+Vr;
gain of amplifier 14 is A1;
gain of the detector 18 is A2; Sc=V@+vc Sc,=Vc1+vc1 (where Vci is the bias voltage applied via resistor R4);
Sc2=Vc2+vc2;
the gain of modulator 6(v6/vi)=A3;
the gain of modulator 8 (v8/v6)=A4; and
the values of the capacitors and resistors are taken to be represented by the references identifying them in Figure 1.
Considering modulator 6, v6=A3.vi but A3=K1.VC1 where K1 is the transfer characteristic of the modulator.
Therefore,
v6=K1.Vc1.v1 =K1.Vc1.#V1
=K1.V1.#Vc1 =K1.V1.vc1 (1)
This assumes Vj is constant (vj=o).
Considering modulator 8, by analogy with Equation (1),
v8=K2.V6.vc2 (2) where K2 is the transfer characteristic of modulator 8.
But this assumes V6 is constant and is the variation due to Vc2. With Vc2 constant (vc2=o) and V6 varying, v8=A4.v6 (3)
Therefore, combining Equations (2) and (3),
v8=A4.v6+K2.V6.vc2 (4)
Now, vo.A2 vc= s.C,.R2 (5)
s.C2.R4
vc1=-.vc (6)
1 +s.C2.R4 and
vc
Vc2= (7) 1 +s.C3.R5 Initially, it has been assumed that Vl is constant.Therefore v=o. Under these conditions (and assuming
Vr is constant, Vr=O), the total loop gain G, is
1 v8
G1= -A1.A2.-.- (8)
s.C1.R2 vc
Substituting from Equations (1), (4) (6) and (7) into Equations (8), and assuming that C2=C3=C and R4=Rs=R,
Hence, 1+s.T1
G1= (9)
s.T3(1+s.T0) where T0=CR, (10)
C.R.A4.K1.V1
T1= , (11)
K2.V6
and C1.R2
T3= (12)
A1.A2.K2.V6
Fig. 2 shows a Bode plot (loop gain against the logarithm of angular frequency) of Equation (9) where the angular frequencies #0,# 1and w3 correspond respectively to the time constants T0, T1 and
T3 defined above. #2 is the angular frequency at the upper end of the frequency band of the circuit.
By geometry from Fig. 2, #3/#2 = #1/#0 Therefore,
T2 To Th T1 Thus,
T0.T3
T2= (13) T1 Substituting from Equations (10), (11) and (12) in Equations (13),
C.R.C1.R2 K2.V6
T2=
A1.A2.K2.V6 C.R.A4.K1.V1 C1R2 A1.A2.A4.K1.V1
A1.A2.A4.K1.V1 or #2= (14) O1.R2 Equation (14) therefore shows the factors which affect #2 that is, the factors which affect the upper limit of the bandwidth of the circuit. These factors are A1, A2, A4, K1 and Vi.
The operation of the circuit arrangement will be considered assuming that it is desired to keep V0 constant. and that this will be done by keeping Vr constant.
If, now, there is an increase in A1, then, due to the D.C. feedback through the modulator 8, A4 will be reduced so as to hold V0 constant. Therefore, for a given VO, A1.A4 is constant.
If now there is an increase in Vj, then again, due to the D.C. feedback path through modulator 8,
A4 will be reduced to keep V0 constant. Therefore, for a given VO, A4.V1 is constant.
Therefore, summarising, for a given V0, A1.A4.V, is constant.
In addition, A2, the gain of the detector 18, must be constant (otherwise, the circuit arrangement will not be able to maintain V0 constant).
Therefore, for a given V0, a)2=1K1, where A1.A2.A4.V1
Z= =constant (15) O1.R2 For small values of control signal V01, the factor K1 for the modulator 6 should be constant.
Therefore, overall, #2 is constant.
The foregoing assumes that V0 is constant. However it may be desired to operate the circuit arrangement so that V0 varies (by a controlled amount). This may be done by varying the reference signal Vr. However, a change in Vr will produce a change (in the opposite sense) in V0, This is achieved by the variation of A4 by means of the signal Vc2. Therefore, Equation (1 5) no longer applies, and thus #2 is not constant if V0 varies.
However, Equation (15) shows that if A2 can be made inversely proportional to V0, then A2.A4will be constant as V0 varies. In such a case, A1 .A2.A4.V1 C1.R2 will be constant for all values of V0, and so, therefore, will #2.
Figure 3 shows the circuit arrangement of Figure 1 modified in order to ensure than A2 is inversely proportional to VO. In the circuit of Figure 3, the output of detector 18 is now fed through a resistor R1 to ground, and an adjustable tapping on this resistor is fed through a buffer amplifier 40 to the resistor R2. In this circuit, therefore, the gain A2 now becomes the overall gain of the suicircuit comprising the detector 18, the resistor R1 and the buffer amplifier 40. In operation, the reference Vr is held constant (even when it is desired to vary V0), and in order to change V0, adjustments are made to the position of the tapping on the resistor R1 so as to alter the value of A2.Thus, a reduction in A2 increases V0 by producing a resultant increase in A4 (via the control signal Vc2).
Therefore, with the circuit arrangement of Figure 3, #2 remains substantially constant for all values of V0 (as well as for changes in the value of A1 and V,).
In the circuit arrangements shown in Figures 1 and 3, a problem can arise at very low modulation frequency. Under these conditions, the impedance in the path for the signal Vci becomes significant andvci tends to zero and the signal Vc2 becomes effectively equal to Vc. Therefore, the modulator 8 must be capable of applying all the necessary modulation. For high levels of pulse modulation at these low frequencies, modulator 8 becomes overloaded and ineffective principally because the circuit limits the rate at which Vc2 can increase by charging capacitor C3.
Figure 4 shows a modification to the circuit arrangement of Figure 3 (but which can also be applied to the circuit arrangement of Figure 1) in order to deal with this problem. The modification consists in the provision of by-pass circuits in series with the control inputs of the modulators 6 and 8, together with two additional resistors R6, R7. The by-pass circuits are provided by diodes D1, D2andD3.
Diode D3 is connected to the junction between the D, and D2 which are respectively directly connected to the inputs of the modulators 6 and 8.
Normally, all these diodes are non-conducting.
However, at very low frequencies where C3 prevents Vc2 from changing sufficiently rapidly, the diodes D2 and D3 conduct therefore bypassing the effect of capacitor C3.
The mathematical analysis given above is in simplified form because it ignores the interaction between the modulators at the crossover frequency (i.e. the frequency where one modulator ceases to be effective and the other begins to become effective). However, this does not have any practical affect on the analysis at other frequencies and does not affect the constancy which the circuit arrangement gives to )2 as explained above.
Claims (9)
1. An automatic gain control circuit arrangement for producing an output signal which is dependent on an input signal and whose mean level has a desired value, comprising a signal path having an input for receiving the input signal and an output at which is produced the output signal, the signal path including control means controllable to vary the level of the signal in the signal path and amplifying means for amplifying the signal in the signal path, the circuit arrangement also including detecting means connected to sense the level of the signal in the signal path after its level has been varied by the control means and amplified by the amplifying means, and operative in response to variations of the sensed level from the desired value to produce a control signal dependent on the variations and which adjusts the control means in a sense such that it offsets the said variations, the control means comprising one part primarily responsive to the alternating component of the control signal and another part primarily responsive to the D.C. component of the control signal whereby changes in the gain of the amplifying means or in the level of the input signal which tend to alter the upper limit of the loop bandwidth of the circuit arrangement are substantially offset by the effect of the resultant change in the gain of the said other part of the control means.
2. A circuit arrangement according to claim 1, in which one said part of the control means comprises first modulating means having a control input for receiving the control signal via a circuit path having an impedance which decreases with frequency and the other said part of the control means comprises second modulating means having a control input for receiving the control signal via a circuit path having an impedance which increases with frequency.
3. A circuit arrangement according to claim 2, including bypass circuits for bypassing the said circuit paths of the first and second modulating means at very low frequencies.
4. A circuit arrangement according to any preceding claim, in which the detecting means comprises a detector operative to sense the level of the signal in the signal path after its level has been varied by the control means and amplified by the amplifying means, means for comparing that level with the level of a reference signal whereby to produce the said control signal, and means for adjusting the level of the reference signal whereby to adjust the desired value of the mean level of the output signal.
5. A circuit arrangement according to any one of claims 1 to 3, in which the detecting means comprises an adjustable gain detector responsive to the level of the signal in the signal path after its level has been varied by the control means and amplified by the amplifying means and operative to produce an output dependent on this level and on its said adjustable gain, means for comparing this output with a reference signal whereby to produce the said control signal, and means for adjusting the gain of the detector whereby to adjust the desired value of the mean level of the output signal.
6. A circuit arrangement according to any preceding claim, including integrating means by which the control signal is applied to the control means.
7. An automatic gain control circuit arrangement, comprising means for receiving an input signal, first modulating means connected to modulate the level of the input signal, second modulating means connected to modulate the output of the first modulating means, an amplifier for amplifying the output of the second modulating means and for applying it to an output terminal, a detector for detecting the level of the output of the amplifier, means operative to compare the detected level with a reference dependent on a desired value of the mean level of the signal produced at the output terminal whereby to produce a control signal dependent on the difference between the actual level of the output of the amplifier and the said desired value, and first and second frequencydependent impedance paths for applying the control signal to the first and second modulating means respectively, one impedance path having an impedance which decreases with increasing frequency and the other impedance path having an impedance which increases with increasing frequency, whereby one modulating means performs modulation primarily dependent on the value of the alternating component of the control signal and the other modulating means performs modulation primarily dependent on the D.C. component of the control signal, so that the upper limit of the bandwidth of the circuit arrangement is substantially unaffected by changes in the gain of the amplifier or in the mean level of the input signal.
8. An automatic gain control circuit arrangement substantially as described with reference to
Figures 1 and 2 of the accompanying drawings.
9. An automatic gain control circuit arrangement substantially as described with reference to
Figures 2 and 4 of the accompanying drawings. ~~~~~~~
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8001168A GB2040616B (en) | 1979-01-17 | 1980-01-14 | Electrical circuit arrangements |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB7901643 | 1979-01-17 | ||
| GB8001168A GB2040616B (en) | 1979-01-17 | 1980-01-14 | Electrical circuit arrangements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2040616A true GB2040616A (en) | 1980-08-28 |
| GB2040616B GB2040616B (en) | 1983-01-26 |
Family
ID=26270247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8001168A Expired GB2040616B (en) | 1979-01-17 | 1980-01-14 | Electrical circuit arrangements |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2040616B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2498850A1 (en) * | 1981-01-29 | 1982-07-30 | Rca Corp | EXPANDER AND SIGNAL COMPRESSOR |
-
1980
- 1980-01-14 GB GB8001168A patent/GB2040616B/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2498850A1 (en) * | 1981-01-29 | 1982-07-30 | Rca Corp | EXPANDER AND SIGNAL COMPRESSOR |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2040616B (en) | 1983-01-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |