GB2039107A - Vectored interrupt in computer - Google Patents

Abstract

In a computer system including a memory, paging apparatus central processing unit and a microprocessor including a PROM and program counter, when a interrupt is generated the microprocessor addresses the memory with two consecutive addresses, the first of which is applied via the paging apparatus to read a out the high order byte of an interrupt routine address and the second of which displays the paging apparatus and permits a register containing a function code to address the the PROM to read out the low order byte of the interrupt routine address both bytes being entered at the counter to address the memory.

Description

SPECIFICATION Vectored interrupt in computer This invention relate to data processing systems and more particularly to apparatus for indicating the device having the highest priority for a given set of device request.

Computing systems, in general, include a process and a plurality of input/output devices. Since a number of devices may request operation with the processor at the same time a system of priorities must be established so that the processor can operate with the I/O devices in an orderly fashion.

Prior art systems have solved the priority problem in many ways including elaborate hardware techniques, hardware/firmware techniques, software techniques, etc.

Many systems have been designed for large computer systems and are costly in terms of hardware and in terms of time to select the input/output device. Also the priority system implemented is not readily changeable. The problem is compounded when the input/output devices are communication lines, each having the capability of receiving and transmitting in different modes, synchronous or asychronous, and at different bit rates.

In a computing system operative with a plurality of input/output systems, the subsystem controlling the data flow may be operative by means of channel programs and may include a microprocessor, and a plurality of input/output devices including but not limited to Universal Synchronous Asychronous Receiver Transmitters (USART) for servicing communication lines. The microprocessor may control a USART that is operative by means of a channel program. If another communication line having higher priority requests service, the microprocessor must interrupt the channel program that is operative and switch the channel program to be operative with the requesting communication line. In the prior art the microprocessor interrupts the channel program by storing information in memory.This information stored in memory enables the channel program to continue service on this interrupted communication line. The information consists of the contents of various registers in the system which must be unloaded when a higher priority communication line interrupts and must be reloaded when the higher priority communication line has completed the data transfer and the system reverts back to the original communication line. This prior art system has various disadvantages.

Firstly, it has to load and unload a large amount of information, which slows up the operation. Secondly, it is difficult to prevent the interrupt if required by the system; and thirdly, there is no identification of the communication line that interrupted the system.

In running a computer program, there are in general two phases which normally alternate. First, instructions and/or operands are fetched to the central processor and then the instructions are executed. During the fetch phase, the processor fetches the next instruction to be executed from main memory, and transfers it to one or more control registers where such further modifications for indexing, indirect addressing and base addition as required may be performed. During the execution phase of an instruction, the processor decodes the instruction and the operation specified by the instruction is executed.

Most stored program digital computers have some means of interrupting the running program upon request either from an external or internal signal. There are a variety of reasons why it is necessary to interrupt a computer program, such as for input or output of information or for calling some routine for performing a standard routine such as maintenance, diagnostic, square-root, etc.

The simplest from of interrupt is to utilize an instruction which causes a halt or branch, such as a HALT or a GO TO, and RETURN subroutine which causes the CPU to go to another location in main memory to obtain the next instruction to be executed rather than continuing with the next sequential instruction of the program. However, before executing the new program or routine, the contents of any indirectly addressable registers such as program counters, accumulator registers or the like must be preserved so that control may be returned to the interrupted program at the point where it was interrupted. This entails additional time in unloading and reloading the program counter.

There are of course many variations to this basic interrupt function such as conditional interrupts, and nested interrupts.

Generally, both instructions and data operands are stored for execution in various addressable locations in the same main memory.

Moreover, the instructions may be further grouped in groups forming subroutines. This requires that address locations be assigned in advance when the program of a subroutine for a particular problem is computed. Moreover, if the subroutine is later modified, the programmer must keep track not only of the original allocations of memory but also of the later modifications. In order to make programming independent of the actual address locations in main memory, indirect addressing has been resorted to, By means of index registers, groups of data or programs may be used without assigning specific address locations to each word in the group at the time the program is compiled.Although the absolute address is later inserted in the memory location referred to by the command, it can be different each time the program is run, depending on where the group is placed by the executing program in main memory. Since the group may be indirectly addressable by a number of commands, the address of the commands remains unchanged and only the absolute address of group is changed if the location of the group is modified. This technique generally requires special words known as descriptors, in place of operand words or instruction words in memory.When an instruction causes an operand word to be read out of memory, it may find a data descriptor word which includes a base address of a group of words, and further includes information identifying it as a descriptor word instead of an operand word, information as to the length of the group of instructions or data, and information indicating whether or not indexing is required.

Whereas it is desirable in an interrupt operation to have operands or instructions grouped in groups which may be placed anywhere in main memory, it is just as desirable that the addresses of the descriptors or other indirect address words be fixed. This may be done by having a central location such as a segment or a table for storing such words.

Both of these techniques are comparatively slow, one requiring several accesses of main memory to access descriptors by indirection whereas the other requires comparison of the command or function code word with the words stored in the table. Moreover, these techniques require substantial amounts of memory space. Where a microprocessor is used, such storage space and speed are at a premium. Accordingly, a hardware technique of interrupt by indirection to any one of several predetermined locations is needed which is fast and is miserly in the utilization of processor and main memory storage.

One object of the invention is to provide an improved mechanism for resolving the order of priority of a number of devices or communication channels requesting access to a processor.

Another object is to provide an improved mechanism for intercepting a channel program operative with an input/output device to be operative with a higher priority input/output device.

A further object is to provide an improved mechanism for interrupting a computer program executing on a computer system.

According to the present invention there is provided a computer system having a memory, a paging apparatus for converting virtual memory addresses to real memory addresses, a central processing unit (CPU) coupled to the memory, and a microprocessor coupled to the memory and the CPU, the microprocessor including a PROM (Programmable Read Only Memory) and a Program Counter, said PROM for storing a plurality of read base addresses in the memory, each such base address locating a respective one of a plurality of interrupt routines, multiway vectored interrupt means comprising; (a) a first means for disabling the paging apparatus when a predetermined location in the real memory is addressed; (b) second means for addressing the PROM when said first means disables the paging apparatus; and, (c) third means responsive to the PROM and the PC for addressing the memory with the base address obtained from the PROM to obtain a selected one of the interrupt routines.

In the preferred embodiment, predetermined locations in main memory store the high order and low order bytes of interrupt vector respectively. When the location in main memory storing the high order byte of the interrupt vector is addressed by the microprocessor, the high order position of the program counter of the microprocessor is provided with the high order byte of the interrupt vector.

However, when the low order byte of the interrupt vector is addressed, the bits of the address are applied to hardware in the CPU which disables the normal addressing mechanism of the CPU and enables an indirect addressing mechanism. The indirect addressing mechanism provides a selected address to one of 64 locations in the ROM or PROM of the microprocessor. The contents of this selected address provides a second address which is placed in the low order byte position of the program counter of the microprocessor, thus giving an absolute address of a desired location in main memory where an interrupt subroutine is stored. Thus, any of 64 interrupt subroutines may be quickly called with a minimum of space requirements.

The preferred embodiment also includes improved means for timing interrupts and for resolving interrupt priorities.

A computer system according to the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1A is a schematic block diagram of the system.

Figure 1B is a schematic block diagram of typical addressing formats of the system.

Figure 1C is a map of the paging PROM.

Figure 2A is a schematic diagram of a typical organization of the real memory of the system.

Figure 2B is a schematic diagram of a typical organization of the virtual memory of the system.

Figures 3, 4, 4A to 4D, 5A, 5B and 7 are detailed diagrams of parts of the system.

Figure 6A is a flow chart of the system.

Figure 6B is a timing diagram of the system.

Fig. 1 A is a block diagram of the system showing information flow and modification of the information for improved addressing. A microprocessor 101 utilizes a 16 bit address bus 102 to address main memory 108. This provides an addressing capability of over 64,000 bytes of main memory 108. The formats of the instruction are shown in Fig.

1 B. There are two formats, one having an eight bit op code and an 8 bit (a) byte whereas the other one has an 8 bit op code, an 8 bit (a) byte, and an 8 bit (b) byte. In order to converse space and cycle time, it is more advantageous to use only the (b) byte.

Accordingly the register 103 utilizes the first 5 high order bits 8, 9, 19, 11 and 12 to address the paging signal generator 105, which is a standard integrated circuit memory chip. The paging signal generator 105 stores 32 eight-bit words which can be addressed by bits 8-12 of the (b) byte. Since 5 bits are utilized to address the paging signal generator they can be utilized to address any of the 32 words therein. The contents of the generator 105 are such so that when the first 8 words (up to address 07) are addressed, signal CPGLIN is activated (i.e. goes low). When the next four words of the signal generator 105 are addressed (i.e. addresses 8-11) then both signals CPGLIN and CPGDIR are activated.

When the next location, word 13 (i.e. address 12), is addressed then all of the following signals are activated: CPGLIN, CPGDIR, CPGCCB, and CPCAD4. The contents are discussed in more detail later.

The paging signal generator 105 is enabled when a low signal is present at its E input terminal from the output of NOR gate 104, which occurs when all the bits 1-8 of the (a) byte are made 0 when it is desired to modify the 16 bit address provided by the (a) and (b) byte. When the paging signal generator 105 is enabled, one of the control signal locations 105a is addressed by bits 9-13 of (b) byte and is enabled by going low. When one of these control signals 105a is active, the 16 bit virtual address 106 is modified to the real address 107 which then addresses main memory 108. If none of the control signals 1 05a are active, then the 16 bit address 106 is identical to the 16 bit address 107 and no modification occurs for addressing memory 108. (The mechanism for performing this modificaion will be discussed in detail in relation to Fig. 3).Assuming, therefore, that control signal CPGCCB is active then bit 11 of the virtual address is replaced by the bit in position a of CCB register 115 and bit 12 will be replaced by bit ss in CCB register 115 to form the real address. If control signal CPGDIR is active, then bit 10 of the virtual address is replaced by bit D of channel register 114. If control signal CPGLIN is active, then bit 9 of the virtual address is replaced by bit M of the CH register 114, and bit 8 of the virtual address is replaced by bit H of the CH register 114. If control signal CPGAD8 is active, then bit 7 of virtual address is replaced by a 1.

Finally, if control signal CPGAD4 is active, then bits 4, 5, 6 of the virtual address are replaced by 1 's.

A CBIU2U signal is utilized to address the line number of a selected Universal Synchronous Asynchronous Receiver Transmitter (US ART) 116, 117. (USART's are commercially available, and may be used to enable computers to communicate with each other over public telephone lines.) the CEI02U control signal enables the I-bus 113 via bidirectional bus driver 111. A CEI02U signal permits communication from the I-bus 113 to the U-bus 112, whereas a CEU210 signal permits communication from the U-bus 112 to the I-Bus 113. The I-bus may have various registers attached for storing communications information. Some typical registers are HI-Order Data Register 120, LO-Order Data Register 121, channel no. register 122, and status register 123.These registers communicate with the microprocessor via the I-bus 113 and the U-bus 112, and with main memory 108 via I-bus 113 and M-bus 109.

In order for the various attachments on the I-bus 113 to communicate with main memory 108 and microprossor 101 it is necessary to assign space in main memory for various lines and channels associated with any communication port. Referring therefore to Fig. 2A, it will be seen that real memory 200 has a portion of its area reserved for lines 0-3. Each line is comprised of 64 bytes and the total 4 lines 0-3 comprise the Logical Table (LCT) space. Each line 0-3 is furthermore subdivided into 2 channels of 32 bytes each. Accordingly, there are 8 channels of 32 bytes comprising 4 lines of 64 bytes each which comprise the LCT space. The next 256 bytes are reserved for Channel Command Programs (CCP) use. There are also 3 to 4K bytes which together with the unused space are reserved for Channel Command Programs (CCP).Below this space there is an additional 256 bytes reserved for the Channel Control Block (CCB). As with the LCT space each line 0-3 is associated with one CCB of 64 bytes each of which is subdivided into 2 channels of 32 bytes each. Below this is memory space reserved as firmware work space. Accordingly, it can be seen that each line 0-3 is associated with one LCT space and one CCB space each of which is subdivided into two channels.

Part of the addressing mechanism described above with Fig. 1A addresses all of these memory spaces. However, to do this it takes two address bytes a and b since one address byte to comprised of 8 bits dnd 8 bits can address only 256 locations. Yet as can be seen from Fig. 2A there are 768 locations (3 x 256) excluding the 3K/4K locations.

These 768 locations are the most commonly addressed since communication of lines 0-3 must constantly be had with its LCT's, its CCB's and the firmware. It is very inefficient to utilize the 16 bit address which can normally address over 64,000 locations merely to address 768 locations. Yet a single 8 bit address can address only 256 locations. The present system permits the 768 locations to be addressed by the first 5 bits 6-12 of the (b) byte 103 by permitting the modification of the virtual address as discussed above. Hence cycle time and storage space is saved by this short form of addressing.

Fig. 1 C is the map or contents of the Paging Signal Generator 105 (i.e. paging PROM 300). The address locations are shown in various numbering systems in the first 3 columns, and the last two columns contain the actual information stored at that address location, in hexadecimal and binary.

Fig. 2B shows 256 locations in memory 201 reserved for virtual memory. The first 64 locations or bytes are numbered in decimal notation 0 to 63 and in hexadecimal notation O O to 3F and comprise the LCT of the current line used by the CCP. The next 32 locations or bytes, decimal locations 64-95 (hexadecimal 40-5F) are reserved for the LCT of the current channel used by firmware. The next 8 locations or butes, decimal locations 96-102, (hexadecimal 60-67) are reserved for the active CCB of the current channel. There is then an unused space and there are 3 eightbyte locations reserved for the USART of the current line, the shadow USART of the current line respectively and the extension of LCT of the current channel.

A typical example will illustrate how the improved addressing scheme of the system works. Assume, therefore, that location 5 of line 0 of virtual memory 201 is to be addressed. Accordingly, all of the bits 0 to 7 of (a) byte of register 103 would be 0 which would enable NOR gate 104 and enable the paging signal generator 105. The next 5 bits 8 to 12 would also be 0, bit 13 would be a 1, bit 14 would be 0, and bit 15 would be a 1, thus giving the binary address 101 (decimal 5). The virtual address 106 would also have bits 0 to 12 equal to 0 with bit 13 being 1, bit 14 being 0, and bit 15 being 1.

Additionally, however, since bits 8-12 of the (b) byte in register 103 are 0, control signal CPGLIN would be active. (It was seen above that if bits 8-12 were utilized to address the first 8 words in the paging signal generator 105, signal CPGLIN would be active or low).

With signal CPGLIN active, bits 8 and 9 of the virtual address 106 would be replaced by bits H and M respectively of channel register 114. Under our assumption, which was that we are addressing location 5 of line 0, bits H and M of channel register 114 would be 0 and accordingly bits 8 and 9 of real address 107 would also be 0. Thus the final real address would have bits 0-12 equal to 0, bit 13 would be a 1, bit 14 would be a 0, and bit 15 would be a 1, thus addressing the fifth location of line 0 of real memory.

To take this one step further, assume now that the fifth location in line 1 is now to be addressed. The bit contents of register 103 and virtual 106 would be identical as in the prior example. However, since line 1 is now being addressed the channel register 114 would have a 0 in its high order bit H and a 1 in its next order bit M. Accordingly, when signal CPGLIN is activated once again (since bits 8-12 of the (b) byte of register 103 are all 0's) bit 8 of virtual address 106 would be replaced by bit H of channel register 114 which is a 0 and bit number 9 of virtual address 106 would be replaced by the mid bit M of channel register 114 which in this example is a 1, since line 1 is being addressed.Hence the real address 107 would have 0's in bit positions 0 to 8, bit 9 would be a 1, bits 10-12 would remain 0, and bit 13 would still be a 1, bit 14 would still be 0, and bit 15 would still be a 1. Accordingly, now hexadecimal location 45 is addressed in real memory which is the fifth location of line 1. It can readily be seen by this reasoning that location 5 of lines 2 or line 3 could be similarly addressed merely by substituting bits H and M of the channel register 114 for bits 8 and 9 of the virtual address 106 to obtain the real address 107.

Fig. 3 is a detailed diagram of the paging apparatus for improved mapping of virtual addresses to real addresses. A structural description, with the various structures of Fig. 3 indentified and tied into Fig. 1A where feasible, will be followed by the operation. It should be noted from Fig. 1A that the paging mechanism is designed to modify bits 4 to 12 of virtual address format 106 to provide the final real address 107 with bits 4 to 12 either modified or not in accordance with the signals presented. On Fig. 3 it should be noted that multiplexers (MUX) 302, 303 and 304 and driver 305 provide the output signals respectively on lines 302A, 304A, 305A and 305B which represent modified bits 8 to 12 of the real address 107. Multiplexer (MUX) 301 and driver 308 provide the output signals on lines 301A, 308A, 308B, and 308C which represent bits 4 to 7 of the modified real address 107. Register 309 corresponds to register 114 of Fig. 1A and stores bits H, M, and D and provides these bits as output signals on lines 309A, 309B, and 309C. Register 310 corresponds to CCB register 115 on Fig. 1A and stores and provides the L and B bits as signal outputs on lines 310A and 310B respectively. PROM 300 corresponds to paging signal generator 105. As described supra, it provides the various signals for mapping the virtual address 106 into the real address 107.

The contents of PROM 300 are given by Fig.

1 C. Drivers 305 and 306 are coupled with AND gate 311 to provide the real memory address bits 11 and 12. Register 311 is utilized to store various signals.

As has been discussed with respect to Fig.

1A, when addresses 0 to 7 of PROM chip 300 are addressed the communication paging line signal (CPGLIN) becomes active by going low. This is shown on the Paging PROM Map of Fig. 3, wherein the contents of the map in the first 8 positions is 01111111. Bit position 7 is 0, or low, which activates signal CPGLIN.

This signal is then applied to input terminals 2 of multiplexers (MUX) 302 and 303 respectively. The other input control signal to input terminals 1 of multiplexers 302 and 303 respectively is the logic 1 (LOGIC 1) signal which is wired to be always high. When signal CPGLIN is active (i.e. in the low state) it addresses input terminals lag and 1 ah of multiplexers 302 and 303 respectively, which means that the signals on input terminals 1 g and 1 h will pass through as outputs on lines 302A and 303A respectively. The signal (CPGCNH) on input terminal 1g of multiplexer 302 comes from the high order bit on line 309A of channel register 309. Similarly the input signal (CPGCNL) on input terminal 1h of MUX 303 comes from the middle order output line 309B. These correspond to bits H and M of channel register 114 of Fig. 1A.

Accordingly, when the line paging signal (CPGLIN) is activated the H and M bits of register 309 are substituted for virtual address bits 8 and 9 on output lines 302 and 303 respectively. Conversely when the line paging signal (CPGLIN) is not activated (i.e. high) then the address bits 8 and 9 virtual address are not modified and passed unchanged to the output lines 302A and 303A of MUX's 302 and 303 respectively. This is so because when CPGLIN is high and with LOGIC 1 always being high, addresses 3g and 3h decimal (11 binary) are addressed on MUX's 302 and 303 respectively. Input address 3g of MUX 302 is CADU08 which is interpreted as the communication address of the microprocessor bit 8. Input address 3h of MUX 303 is CADUO9 which is interpreted as the communication address microprocessor bit 9.When input terminals 3g and 3h are addressed this becomes active and permit the addresses on that terminal to pass through to the output lines of 302A and 303A of MUX's 302 and 303.

The next control bit for modifying the virtual address 106 from the PROM chip 300 is the directional bit (CPGDIR). The directional bit is the low order bit D in channel register 114 and on line 309C of channel register 309. The direction bit becomes activated when addresses 8, 9, 10, or 11 (decimal) of the PROM 300 are addressed (see Fig. 1C).

Additionally when these bits 8-11 are addressed output signal CPGLIN also becomes active. Accordingly, in addition to the application of the CPGLIN signal to MUX's 302 and 303, there is an application of signal CPGDIR on input terminals 1d and lai of MUX's 301 and 304 respectively. With signal CPGDIR on input terminal 1 of MUX 304 inactive or low it makes no difference whether input signal CPGAD8 on input terminal 2ai of MUX 304 is high or low since under either condition, either input terminal Ob or 2b (addresses O to 11 binary) are activated and the CPGCND signal is applied to both these addresses. The origin of the CPGCND signal is from the output line 309C of channel register 309 which is the D bit of channel register 114 and channel register 309.Accordingly, when the directional bit CPGDIR is activated the number 10 (decimal) bit of virtual address 106 is modified in accordance to the contents of the D bit of the channel register 114 or 309.

There is no effect of the CPGDIR signal on the 1d input terminal of MUX 301 unless CPGAD8 signal is also activated. This is so because with signal CPGAD8 inactivated or high, only addresses 2e or 3e (10 or 11 binary) or MUX 301 can be addressed and these are both the same and represent bit 7 of the communication address of the microprocessor. However, when the CPGAD8 signal from PROM 300 is also acrivated (i.e. low) then only address Oe or le (00 or 01 binary) of MUX 301 are addressed and become active; both these addresses have the logic signal 1 LOGIC 1 applied which are permitted to pass to output line 301A or MUX 301 when both signal CDGAD8 and CPGDIR are active or only when CPGAD8 is active. Hence with CPGAD8 active, bit 7 of virtual address is modified and forced to 1.

As described with respect to Fig. 1A, when the channel register bit (CPGCCB) is active or low then bits 11 and 12 of virtual address 106 are replaced by channel bits a and ss of register 115. Since register 310 on Fig. 3 corresponds to channel register 115 and bit CPGCCH on output line 310A correspond to the a bit of channel register 115 and bit CPGCCL on output line 310B corresponds to the ss bit of register 115, then these bits will replace bits 11 and 12 of the virtual address when the signal CPGCCB is active or low.

When the signal CPGCCB is activated, it is applied to the 11 input terminal of driver 306 and to one terminal of AND gate 31 1A.

Accordingly, driver 306 is enabled and the channel control bit signals CPGCCH and CPGCCL on output lines 310A and 3108 are applied to terminals 1 h and Oh respectively of driver 306 and pass through to output lines 306A and 306B of driver 306 and replace bits 11 and 12 of the virtual memory address. It should be noted that when the CPGCCB signal applied to input terminal 1 of driver 306 is low it enables driver 306, but this same signal applied to the input terminal 19 of driver 305 disables driver 305. Hence the CADU signals on input terminals 24 and 25 respectively of driver 305 are not passed through to the output terminal 305A and 3058 of driver 305, but rather are replaced by channel register 310 bits as previously described.Accordingly, it is seen that either driver 306 or 305 are enabled but not both, and either the channel register bits are passed through via driver 306, or the microprocessor address bits are passed through to the output via driver 305.

Finally, with respect to the virtual address modification the modification of bits 4, 5, and 6 will be discussed. As noted with respect to Fig. 1A this is accomplished via signal CPGAD4. When address 1 2 (decimal) of Paging Signal Generator is addressed all of the following signals become active; CPGLIN, CPGDIR, CPGCCB, and CPGAD4. This is seen from Fig. 1C, where address 12 (decimal) contains 00001111. The way the first three signals modify the virtual address when they are active has already been discussed. The signal CPGAD4 modifies the virtual address and forces 1's into bits 4, 5, and 6 of the virtual address.The CPGAD4 signal is applied to the enabling terminal 19 of driver 308 When driver 308 is enabled (i.e. low) then 1 's are forced for bits 4, 5, and 6; if it is not enabled and is high then the microprocessor address CADU on bit numbers 4, 5 and 6 will pass through. The reason for this is that driver 308 is a commercially available tri-state circuit which has pull up resistors for the signal applied. Accordingly, if a low signal such as CPGAD4 is applied it does not enable driver 308 and the output signals are pulled up to + 5 volts making it a logic 1. On the other hand, when CPGAD4 is not active it is high, then it enables driver 308 and permits the address signal on input terminal 1 k, 2k, and 3k respectively of driver 308.

Not only does the paging signal generator 105 on Fig. 1A (PROM 300, Fig. 3) generate signals that can more efficiently address memory 109, but it further generates signals which provide more efficient addressing and communication between main memory 108, the microprocessor 101, and various registers and peripherals attached to the I-bus and U-bus. This communication between various devices such as registers utilizing the U-bus and the I-bus Is initiated by activating signal CEU210 (i.e. signal CEU210 is low and represented on Fig. 1C by a 0). It should be noted that signal CEU210 is bit position number 1 on paging signal generator 105.Now referring to Fig. 1C which is the map of paging signal generator 105 (PROM 300) it should be noted that there is a 0 stored at bit position number 1: decimal locations 18, 21, and 22 or virtual address hexadecimal locations 90, A8, and BO.

Accordingly, when any of these locations of paging signal generator 105 (PROM 300) are addressed by the microprocessor 101, signal CUE210 will become active or low. Signal CEU210 initiates the communication process and controls the enabling of the bus driver 111 on Fig. 1A (311A, Fig. 3). It is also applied as one input to AND gate 354 of Fig. 4 and guarantees a pulse out after the data becomes valid on the bus.

Referring to Figs. 3 and 4, a signal CUE210 is generated at bit position 1 of PROM 300 when it is desired to enable the I-bus driver 311A to cause data to be driven from the U-bus to the I-bus and written into either the channel register 114, the CCB register 11 5, or the S register 1 23A. Referring to Fig. 4 it will be noted that the signal CEU210 is applied to one input terminal of AND gate 354 and is ANDed with a strobe signal CTPHZD to generate the CEU210-10 signal at the output and AND gate 354. This signal is then applied to the enabling input of decoder 355. Also applied to input terminals 20A and 10A respectively of decoder 355 are bits 10 and 11 of the address 103 of the communication address unit.These bits are then decoded so as to activate one of four signals on the output terminals of decoder 355. When bits 10 and 11 on the input terminals 20 and 10 of decoder 355 are both 1, then the output signal CEU2 IO-A2 is enabled and is applied to the enable terminal of decoder 357. Additionally, bits 1 3 and 14 of the communication address unit (i.e.

signals CADUI3 and CAD14) are applied to input terminals 2PA and 1 PA respectively of decoder 357. When both these bits 1 3 and 14 are 0, the zero output terminal of decoder 357 is enabled and signal CEI2CN is activated and utilized to write into channel register 114 on Fig. 1A, (309, Fig. 3). On the other hand, if bits 13 and 14 are 0 and 1 respectively and are applied as signals CADU13 and CADU14 to input terminals 2PA and 1 PA respectively of decoder 357 then the 01 output terminal of decoder 357 is enabled and signal CEI2CB becomes active and is utilized to address CCB register 11 5 on Fig. 1A (310, Fig. 3).Finally, if bits 13 and 14 applied as signals CADU13 and CADU 14 on input terminals 2PA and 1 PA respectively of decoder 357 are 1 and 0 then the 02 output terminal of decoder 357 becomes enabled and signal CEi2SR becomes active and is utilized to address the S register 1 23A.

Thus signal CEU210 is utilized to enable the bus driver 111 and address registers 114, 11 5 and 1 23A. Accordingly, when the microprocessor 101 executes a write instruction directing it to write the microprocessor's accumulator into location A8 hexadecimal, the microprocessor places the contents of the microprocessor's accumulator on the U-bus and enables bus driver 111 in a write direction, the U-bus signals then being strobed into the appropriate register address.

When a write instruction is being executed and information is being written into any of the registers on the l-bus, bus driver 110 (Fig.

1A) also enables the M-Bus 109 and the same information written into the address register is also written into a section of memory 108 which is addressed. (See also Figs. 2A and 2B). Bus driver 110 is enabled by the lack of signal CEMB2U and enables the M-bus in the direction of the memory 108. Hence the information written into the registers is also written into a "shadow memory" which preserves the information for diagnostic purposes or for debugging and provides a place to preserve data when remote maintenance is performed.

In reading data from the I-bus to the U-bus it is necessary to inhibit transfers of data from the M-bus to the U-bus. This allows the I-bus to control the data onto the U-bus. This function is performed by generating the signal CEI02U in paging signal generator 105. This signal is then applied to the enable terminal of decoder 351 on Fig. 4, and at the same time bits 9 and 10 of the address 103 are applied to input terminals 2K and 1 K respectively as signals CADUOS and CADU10. These signals undergo a first level of decode to provide an output signal CEIO2U-A1 on output terminal 01 of decoder 351 when the input bits 9 and 10 are 0 and 1 respectively.The CEl02U-A1 signal is then applied to the enabled input terminal of decoder 352 along with bits 14 and 15 on input terminals 2LA and 1 LA respectively. Depending on the binary value of bits 14 and 15, 1 of 4 subcommand signals will be generated at the output terminals of encoder 352. When bits 14 and 15 have 0 values (which is equivalent to addressing location hexadecimal A8 in virtual memory space) a subcommand CEDH2100 is generated at the 00 output terminal of decoder 352. That signal is then applied to the enable terminal of register 360. Register 360 corresponds to the HI-order data register 120 of Fig. 1A. Accordingly, signal CEI02U provides a means for reading data from the high order register 120 into the I-bus and onto the U-bus.However, since bus driver 110 has been inhibited by the presence of signal CEM2B the memory space addressed by the address 103 is not read, and only the high order register 120 is read. In a similar manner low order data register 121 is read when bits 14 and 15 are 01 respectively thus addressing output terminal 01 of decoder 352. Hence the signal CEDL21-00 is generated which is applied to the enable terminal of register 361 on Fig. 4A. Thus register 360 and 361 of Fig. 4A correspond to registers 120 and 121 respectively of Fig. 1A.

Bus driver 110 of Fig. 1A corresponds to driver 370 of Fig. 4B. This is a bidirectional driver and can drive data either from the memory bus 109 to the U-bus 112 or vice versa. The direction of data transfer is controlled by the signal CEMB2U. When the signal is 1, data is permitted to flow from the memory bus 109 to the microprocessor bus 11 2 and when it is O it permits data transfers in the other direction. The CEMB2U signal is generated via AND gates 371 and 372 of Fig. 4.

These AND gates represent a simple AND'ing operation of various signals such as the microprocessor read CUREAD, the strobe signal CIPHZ2 and the communication enable signals CSR2U and CEIN2U. They generate the CEMB2U signal which is then applied to one input terminal of AND gate 371. It should be noted when a transfer operation from the I-bus to the U-bus is being made, in other words a read operation from a register on the I-bus to the U-bus, then that signal would be high on the input of AND gate 371 and if the remaining signals are also high the CEMB2U signal is high. When this high signal is applied to the input terminal of driver 370 of Fig. 4B it would inhibit information passing through via bus driver 110 from the I-bus to the M-bus.

Referring now to Figs. 1 A, 1 C and 4, the addressing of USART's 116 and 117 will be described. The signal that initiates this addressing procedure CE$U2U which appears as bit 3 from the paging signal generator 105 of Fig. 1A. It should be noted from Fig. 1C that the only address containing a O at bit number 3 is decimal 17. Accordingly, when this location is addressed, bits 0, 3, 4 and 7 will become active. As noted previously, bit 3 provides the signal CE$U2U which is applied to the enable terminal of decoder 350A of Fig.

4, and participates in the decoding of the middle bit of channel number CPGCNL. Depending on the value of that bit one of two output signals CEOU2U and CEl U2U on output terminals 0 and 1 respectively of decoder 35A will become active. When CEOU2U is active, USART 116 is enabled whereas when CE1 U2U is active, USART 117 is enabled.

When information is written in the enabled USART it is also written into that portion of memory addressed by address 103. This type of dual addressing utilizes two virtual addresses which are converted into the same physical address to provide a duplicate address or shadow of the physical device actually being addressed. For example, we have shown how address 88 hexadecimal addresses the physical USART by providing an enable signal for the appropriate USART. Referring to Fig. 1C again, it will be noted that address C8 hexadecimal has the same binary map or contents as address 88 hexadecimal with one exception, which is that bit number 3 of address 88 is O or active whereas bit 3 of address C8 is 1 or inactive.Accordingly, it is seen that with the exception of the third bit, address 88 provides the same signals as address C8 and accordingly C8 can be regarded as the shadow of the particular USART being addressed when the signal CESU2U is provided at address 88. Hence it can be ssen that address 88 (decimal 17) addresses the actual USART data whereas address C8 (decimal 25) addresses its shadow. Accordingly, when we write into address 88 it is written in the USART and the appropriate memory space addressed by memory space C8 in accordance with the principles discussed above.

Let's see how this happens by a typical example. First we shall address decimal location 17 in paging signal generator 105. Utilizing address format 103 the address will be as follows: 0000000010001000. It should be not that bits 8 to 12 which do the actual addressing contain the decimal number 17 in binary format. Referring to Fig. 1C it will be noted that decimal location 17 will have bits 0, 3, 4 and 7 active. Bit O is signal CPGAD8 from paging signal generator 105 and this signal when active forces bit 7 to a 1. Bit 3 is the signal that addresses the USART and does not participate in changing the virtual address to a real address. Bit 4 of paging signal generator is CPGAD4 and when this is active forces bits 4, 5 and 6 to a 1.Finally, bit 7 of paging signal generator 105 when active provides the signal CPGLIN and forces the high order bit and the middle order bit of the channel register into bit positions 8 and 9 of the real address.

Assuming for the purposes of this example that those bit positions are 0, then bits 8 and 9 would be 0 and the final real address would be 000011110000000. Now when decimal addret 25 is addressed, the address format 103 would take the form 0000000011001000. Again it w be noted from Fig. 1C that the following signals would be active: CPGAD8, CPGAD4, and CPGLIN. Since the signal CE$U2U which was also present in the previous example did not participate in changing the address, the final real address which would result is the same as the previous address given as follows: 000011110000000. Hence it is seen that the same address is addressed in memory. Accordingly, when remote maintenance or diagnostic operations are required only the shadow memory can be addressed and not the actual USART.This same principle is applied to other peripheral devices or registers attached to the I-bus also.

This shadow technique of addressing a piece of hardware such as the USART, the channel register or the channel control block register, etc., is particularly useful and saves cycle time when an interrupt occurs which requires a register such as the CCB register to have its contents replaced. In the conventional implementation, the contents of the register are read and stored in a temporary storage and the new information is written into the register. When it is required to repace the original contents of the register, the register is first read once again and the contents stored in a temporary storage and then the original contents are written back in.With the shadow concept, since there is a shadow of the original information of the register stored in a predetermined location in main memory, all that is required in an interrupt mode is for the new information to be written into the register. The old information will still be retained in the shadow location and when it is necessary to replace it back into the register it can be read directly from the shadow location. Since it takes approximately 3 microseconds for a read and 4 microseconds for a write, a total of 4 microseconds is saved during each complete cycle.

Referring now to Figs. 5A and B and 6A and B, the preferred embodiment of the vectored interrupt system will be disclosed. Fig.

6B shows the timing diagrams of the interrupt sequence. The T3 signal is a ground active TTL signal generated each 500 nanoseconds by the CPU 600 and has a nominal width of 100 nanoseconds. This signal is widely used by peripheral controllers of the system 600A to demark and set/reset conditions on the busses 620, 621 and 622 and to act as a data strobe.

The interrupt request signal is an open collector driven line on the busses and is switched to ground by any peripheral controller of the system which is attempting to interrupt. The PIOCT signal is also a ground active TTL signal utilized by the CPU 600 to indicate to a selected controller that there are encoded states on the bus which convey bus dialog control information to the controller.

The microprocessor interrupt mechanism herein described is activated by the CPU 600 initiating an I/O instruction addressed by channel number to one of the I/O devices (620 or 601) via the I/O bus. Should the order be directed to the microprocessor, a decoder within the bus interface 601a recognizes the channel number and sets the interrupt request.

The 16 bits of information on the system bus during command initiation (PIOCT, see Fig.

6B) comprise the 10 bit channel number CN and a 6-bit function code. The CN is checked, and if it is the CN of this microprocessor this information is stored in registers 362 (channel number) and 311 (FCN), and an interrupt request to the microprocessor is stored in a flip-flop in the bus interface 601. Since the microprocessor treats this as a "masked interrupt" its action may be deferred. Timing of these actions is shown in Fig. 6B.

Typically when the microprocessor 601 receives an interrupt order it sequentially addresses locations hexadecimal FFF8 and FFF9 in main memory 108 where the high order byte and low order byte respectively of the interrupt vector are stored. It will be seen that the hexadecimal address FFF8 is, in the format denoted in Fig. 1A at 103, 1111111111111000. The hexadecimal address FFF9 is, in the same format, 1111111111111001. Accordingly, when ad- dress FFF9 is addressed after the high order byte of the interrupt register is fetched, the 1 bits of the FFF9 address become active. These bit signals are applied in various combinations or individually to various hardware circuit elements shown on Fig. 3; in other words these address bits, instead of addressing hexadecimal address FFF9 in main memory 608A and 608 B, are used to (a) disable the paging ad dress mechanism described above and (b) to enable decoder 380 in the CPU, which in turn (c) enables register 311 to provide a predetermined base address in PROM/RAN 601 B (d) which in turn contains the address of a selected one of 64 function codes. This is accomplished when bits 0, 1, 2, 13, 14 and 15 ortho above address are applied to input terminals of decoder 380 of Fig. 4C.As noted above, when address FFF9 is being addressed bits 13 and 14 will be 0 and bit 15 will be 1, and these will be applied to the enable terminals of decoder 380. Moreover, bits 0, 1 and 2 of the address which will all be 1 's are applied to terminals 1, 2 and 4 of decoder 380 of Fig. 4C.

Since the terminals on which bits 13 and 14 (i.e. signals CADUI1 and CADUIS) are applied have an inversion circuit, decoder 380 will be enabled and the information on terminals 1, 2 and 4 of decoder 380 (which will all be 1 's) will be decoded and provide an active signal CADUH7 on output terminal 7 of decoder 380 (because binary 111 decodes into decimal 7). The signal CADUH7 is then applied to the enable terminal F of register 311, Fig. 3, and is further applied simultaneously to the enable/disable terminal of MUX's 301, 302 and 303 and AND gate 31 1A thus disabling the paging address mechanism described above.Accordingly, instead of accessing location FFF9, register 311 is enabled and provides the low order bits 10, 11, 12, 13, 14 anc 15 at its output terminals. These bits form an address for addressing the microprocessor memory RAM or PROM 601 B. The contents of the address of memory 601 are placed in the low order byte position of the microprocessor program counter (PC) 601d. The information in register 311 is the function code information shown in Fig. 5B which was delivered by the CPU when an interrupt has been initiated (see Fig. 6B PBYTE signal).Since the paging address mechanism has been inhibited, and since signal CADUH7 redirects the address FFF9 to register 311, and since signal CADUH7 additionally enables register 311, the low order bits 11,12,13, 14, and 15 register 311 are used to access information in memory 601 b which is placed in the low order byte position of program counter (PC) 601d.

Since there are 6 bits in the low order byte of the function code, it can address up to 64 locations in memory such as the RAM or PROM 601 b. Each of these locations contain the low order byte of the interrupt vector associated with its function code which when appended comprises the interrupt address.

Accordingly, depending on the information content of the function code, there is provided an interrupt which can start at any of 64 different locations in the PROM 601b and accordingly can provide up to 64 different interrupt operations. Moreover, as seen above, the program computer counter 601d or other registers obtain their information from a shadow location and accordingly it is not necessary to first unload and then save the old information and then load the new information and repeat the same process over again when going out of the interrupt loop. It should also be noted that the normal interrupt procedure of the microprocessor which directs the microprocessor to address FFF9 on interrupts is bypassed, and one address of 64 unique addresses is automatically provided by the function code, thus providing in effect a shortcut to 64 different vectors or routines.

Referring now to Figs. 4 and 6B it should be noted that when signal CADUH7 is activated, it is applied along with a phase D signal CTPHZD to AND gate 358A enabling signal CEl2CN. Moreover, signal CADUH7 is OR'ed with signal CECNZI in OR gate 358B to activate signal CECNZI. Signal CEI2CN is applied to the C terminal of channel register 309 on Fig. 3, which is the channel register 115A of Fig. 1A. Similarly, signal CECN21 is used for strobing the contents of channel number register 122 on Fig. 1A onto the I-bus or vice versa.

Accordingly, the vector interrupt does two things: (a) it automatically addresses any one of 64 locations in accordance to a unique function code; and (b) it loads the hardware channel number register to the channel number that is being asked to service on the interrupt. The channel control block register (CCB) 115 may also be changed subsequently by firmware on an interrupt depending on what the function code is.

There is also another type of interrupt which involves the establishment of priorities among a number of competing input/output devices 620. This is accomplished by means of a PROM 384 which has a number of predetermined locations storing information for determining priorities. For example, either the USARTO 116 or the USARTI 117 in Fig. 1A is operative with the microprocessor 101 under control of a channel program. The priorities are established in a PROM 384 in Fig. 4D and the CPBACK + 00 input to PROM 384 is activated when the microprocessor 101 is running a background program. The USARTO 11 6 request signals CORRQT (receive) and COTRQT (transmit) are applied to PROM 384 address terminals 1 a and 2a respectively.

Similarly the USART1 117 request signals Cl RRQT and CITRQT are applied to PROM 384 address terminals 3a and 4a. Signals CPGCNH, CPGCNL and CPGCND identify the channel number of the currently active channel program and are applied to address terminals 5a, 6a, and 7a rqspectively. The PROM 384 is internally coded to give 1 of 256 outputs, The PROM output signals include the chan nel number of the intercepting input/output device and a signal to indicate that a higher priority input/output device requests to access the program. At any particular time, there may be a number of devices requesting the channel program and a particular device operative with the channel program. Each of these conditions at that time is reflected in a PROM address signal which selects a particular PROM location.Permanently fixed in that location is a bit configuration which indicates the device having higher priority and whether that device will intercept the channel program when the present device has completed its channel program subroutine. The codes are established by following a number of rules.

If a channel is executing, its mate cannot intercept. That is, if UARTO 116 is receiving and the receive request CORRQT + 00 signal input to PROM 384 is high, then if the USARTO 11 6 transmit request COTRQT + 00 signal is forced high as well as the USART 11 7 transmit signal CITRQT + 00 the USART 116 continues in the receive mode until the channel program has completed the receive operation, then the channel program will start a USARTO 11 6 transmit operation.

If both USARTO 116 and USART1 117 operate synchronously, then the receive operation takes priority over the transmit operation.

If USARTO 116 was transmitting and USART1 117 requested the channel program for a receive operation, the channel program would switch to service USART1 117 after USARTO 11 6 completed its transmit operation.

If both lines are not synchronous, USARTO 116 has priority over USART1 11 7. The background program running on microprocessor 101 has priority over both USARTO 11 6 and USARTI 117. The configuration burned into the PROM 384 define the priorities.

The apparatus provides a means for intercepting the channel program to execute for a different communication line at a time in the channel program when there is very little information to store. The termination of a microprocessor microprogram subroutine is just such a time. The microprocessor subroutine terminates with a jump to adress BD40,6 (7E BD40). Address signals Bud4016 contain an instruction interpreted by the microprocessor as a "reset interrupt mask" microword which enables the microprocessor interrupt line. If no interrupt request is outstanding, the program then steps to address Bud41,,. The BD41 signals on the address bus enables an instruction register and disables the normal memory read data path 110.When another communication line requests to intercept the channel program, then the no operation microword NO OP 01,6 which is stored in the instruction register appears on the U-bus resulting in the microprocessor sending out address BD42 which is the start of the service routine for starting the intercept operation. If no intercept exists, the "Return from Subroutine" microword 3916 is stored on the U-bus resulting in the microprocessor normal return to execution of the current channel program.

In more detail, if the channel program is to be intercepted, then the PROM 384 output selects the channel number of the device that is operative with the intercepted channel program, through PROM 384 output signals CICHNH + 00, CICHNL + 00, and CICHND + 00. In addition, the CITCTR signal output of PROM 384 is applied to the inputs of a register 382. When the channel program reaches the end of a subroutine, a jump microinstruction coded as hexadecimal 7E BD40 is outputted from the microprocessor 101. The bits coded as hexadecimal 7E desig- nate a jump microinstruction and the bits coded as hexadecimal BD40 designate the address to which the channel program jumps.

The address Bud40,6 signals are sensed by the microprocessor 101 as a "set interrupt mask" microword which disables the microprocessor 101 interrupt line.

The next address BD4116 (1011 1101 0100 0001) is applied to address bus 102its and input decoder 380 of Fig. 4C. The 0, 1, 2, 13, 14, and 15 bit positions are applied to the input of decoder 380 of Fig. 4C (or, as designated in Fig. 1A, decoder 128) ad address bus signals CADUOO + 00, CADU01 + 00, CADU02 + 00, CADU13+O0, CADU 14 + 00, and CADU 15 + 00. The CADUHT-OO output of decoder 380 is forced low thereby enabling the I register 382 of Fig. 4D, or as designated in Fig. 1 A, I register 130.

If a request is not made to intercept the channel program, then the signal CITCTR-OO is 1 and the output of register 382 appears on the U-bus 112 of Fig. 1A as hexadecimal 39 by means of signals CDBUOO-07 + 00, which is the return to start microinstruction. If there is a request for intercept, then signal CITCTR-OO is 0 and the output of register 382 appears on U-bus 112, Fig. 1A as hexadecimal 01 which is the no operation microinstruction, which is sensed by microprocessor 101 to start a service routine starting in the next address location, hexadecimal BD42, to intercept the channel program.

In Fig. 4 the CADUH5-OO input to AND gate 372 when high inhibits information from flowing from U-bus 112 to U-bus 109 in Fig.

1A through driver 110 by forcing the signal CEMB2U + 00 output of AND 371 in Fig. 4 high.

As seen in Fig. 3, the signal CPBACK + 00 output of the CCB register 310 is operative when the I-bus 113 in Fig. 1 signal CDBl02 + 00 is 1, indicating to the PROM 384 of Fig. 4D that the microprocessor 101 is operating in a background mode.

Claims (11)

1. In a computer system having a memory, a paging apparatus for converting virtual memory addresses to real memory addresses, a central processing unit (CPU) coupled to the memory, and a microprocessor coupled to the memory and the CPU, the microprocessor including a PROM (Programmable Read Only Memory) and a Program Counter, said PROM for storing a plurality of real base addresses in the memory, each such base address locating a respective one of a plurality of interrupt routines, multiway vectored interrupt means comprising: (a) first means for disabling the paging apparatus when a predetermined location in the real memory is addressed; (b) second means for addressing the PROM when said first means disables the paging apparatus; and, (c) third means responsive to the PROM and the PC for addressing the memory with the base address obtained from the PROM to obtain a selected one of the interrupt routines.

2. A system according to Claim 1, wherein the Program Counter has a high order address area and a low order address area, and including fourth means coupled to the third means for storing in the high order address area the contents of the memory location addressed by the selected base address.

3. The apparatus as recited in Claim 2, including fifth means for storing into the low order address area of the PC the contents of a selected one of the plurality of locations of the PROM.

4. A system according to any previous claim including means responsive to an interrupt order for interruption of the CPU to address said predetermined location in the real memory.

5. In a computer system having an I/O bus with a plurality of I/O devices coupled to it, a system bus with a central processing unit (CPU) and a microprocessor coupled to it and coupled to the I/O bus, a memory coupled via a M-bus to the CPU, and a plurality of communication lines coupled to the microprocessor, a priority resolving mechanism com prising a storage device coupled to the microprocessor and having a plurality of locations storing priority information, the priority device being addressed by a combination of signals indicative of the states of the memory, CPU, microprocessor, I/O devices, and communication lines in response to requests and produc ing in response thereto signals indicative of the relative priorities of devices requesting interrupt.

6. The computer system according to Claim 6, wherein the storage means stores in each location an indication of the device having highest priority when that location is addressed.

7. A computer system according to either of Claims 5 and 6, wherein when the commu nication lines are vying for control of the microprocessor, and at least one of the communication lines is operating in a synchronous mode and the remainder of the communication lines are operating in and asynchronous mode, the priority resolving mechanism provides signals indicative of that combination of conditions including a warning priority to the communication line operating synchronously.

8. A computer system according to Claim 7, wherein when both communication lines are operating in an asynchronous mode, the priority resolving mechanism provides signals indicative of that combination of conditions including a warning priority to a predetermined one of the communication lines.

9. In a computer system according to any one of Claim 5 to 8, wherein the M-bus and the system bus are coupled by means of a bus driver, and the system bus has an instruction register coupled to if for storing information for initiating an intercept operation, an intercept mechanism comprising: interrupt means for interrupting the microprocessor; addressing means for addressing a first predetermined location in the memory storing signals for enabling the interrupt means; means for causing the addressing means to address the next sequential location to the first predetermined location when no interrupt request is being made, that next location storing signals for enabling the I register and for disabling the bus driver, whereby the normal memory read data path is disabled; and, means coupled to the I register and responsive to an intercept request from one of the communication devices for initiating an intercept operation.

1 0. A computer system according to Claim 9, wherein the addressing means comprise a PROM which converts virtual addresses to real addresses.

11. A computer system substantially as herein described with reference to the drawings.