GB2038520A - Variable mark/space generator - Google Patents

Abstract

A system for producing a variable mark/space output signal which has particular application in the driving of a motor for propelling an invalid carriage employs a decoding comparator 5 and a counter 6. The comparator compares a digitally coded input signal 1, 2, 3, 4 with the state of the counter 6 which counts clock pulses 7 continuously. The overflow pulse from the counter sets a bistable 8 while the comparator 5 resets it after the number of clock pulses specified by the input signal. Digital-to-analogue conversion is thus avoided, together with the problems of wear inherent in conventional analogue control systems. The control system which is described derives an output signal of variable mark/space ratio directly from digital signals coded in accordance with a Gray code with a minimum of logic circuitry, and provides the ability to multiplex. <IMAGE>

Description

SPECIFICATION A control system This invention relates to a control system for producing a variable mark/space output signal. Such an output signal may be used for a variety of purposes, two examples being the dimming of lights and the driving of a motor.

Conventionally variable mark/space output signals are generated from analogue inputs using a linear transducer, which is generally a potentiometer, in comparison with a reference potential and the difference signal is used to control an integrator or a ramp generator.

After a period of use wear occurs in the potentiometer introducing inaccuracy into the system and in consequence there have been continued attempts to produce higher grade potentiometers in order to reduce this and other disadvantages which inevitably result from potentiometer wear. The use of higher grade potentiometers means that the cost of these control systems for producing variable mark/space output signals is inevitably increased. Also difficulties arise due to backlash in these conventional systems, particularly in the drive means, operated for example by a joy stick, which is used to set the potentiometer.

When a conventional analogue control system is used to drive a motor for propelling an invalid carriage, the incidence of wear in the potentiometer used in the conventional analogue control system is inevitably greater in the direction for forward movement of the carriage than in the direction for backward movement of the carriage, because reverse is used so much less frequently than forward drive.

This uneven wear of the potentiometer affects its zero setting which leads to problems in operating the motor drive for the invalid carriage.

According, there has been a need to replace the known analogue control systems by control systems which do not require the use of potentiometers, but no solution for this problem has been found up to the present time when analogue systems incorporating potentiometers are used universally for producing variable mark/space output signals in a variety of applications.

In accordance with the present invention there is provided a control system for producing an output signal of variable mark/space ratio from digitally coded input signals each of which is preselected to correspond to a desired mark/space ratio, in which digitally coded input signal is applied to a decoding comparator which is connected to a counter having a plurality of count states each of which corresponds to a desired mark/space ratio, and the instantaneous mark/space ratio of the output signal is directly determined by a signal given by the decoding comparator when the decoding comparator detects a coincidence between the digitally coded input signal and the state of the counter corresponding to the mark/space ratio represented by the digitally coded input signal.

Further in accordance with the present invention there is provided a control system for producing an output signal of variable mark/space ratio from digitally coded input signals each of which is preselected to correspond to a desired mark/space ratio, the system comprising a pulse generator for generating a series of pulses, a counter arranged to be driven by the pulses in said series, a decoding comparator which produces a signal in recognition of the application of a selected digitally coded input signal simultaneously with the presence in the counter of a count corresponding to that digitally coded input signal, and means for determining the mark/space ratio of the output signal in accordance with the time at which the decoding comparator signal occurs.

The digitally coded input signals may be derived from any one of various sources, for example from the output of a microprocessor, but where direct manual control is required, the digitally coded input signals may be obtained from a keyboard or by reading with a suitable device from a digitally encoded tape, tablet, disc or like means, the position of which is manipulated in accordance with the output signal required. The reading device for reading the digitally coded signals from the tape, tablet or disc may be an optical-type device for cooperating with translucent parts of the tape, tablet or disc, or it may alternatively be a magnetic device for reading signals recorded magnetically on the tape, tablet or disc. In the embodiment of the invention which will be described the reading device comprises a series of opto-coupled pairs of photo-transistors and infra-red emitting diodes.

As already indicated a control system in accordance with the present invention has particular application in the production of a variable mark/space output signal for controlling the speed of a motor, conveniently a D.C.

motor. More particularly in accordance with this aspect of the present invention there is provided a control system for controlling the speed of a motor which is driven by an output signal of variable mark/space ratio derived from digitally coded input signals each of which is preselected to correspond to a desired mark/space ratio, the system comprising a pulse generator for generating a series of pulses, a counter arranged to be driven by the pulses in said series, the counter having a plurality of count states, each of which corresponds to a desired mark/space ratio, and a further count state, a decoding comparator to which each of the said plurality of count states in the counter is connected, the decod ing comparator providing a signal when the decoding comparator detects a coincidence between a digitally coded input signal and the state of the counter corresponding to the mark/space ratio represented by the digitally coded input signal, and means responsive to the further count state of the counter and to the occurrence of the decoding comparator signal for respectively initiating and terminating a mark or a space condition of the output signal whereby the mark/space ratio of the motor drive current is determined.

in a manually operated system in which the digitally coded signals are read from a tape, tablet or disc the position of which is manipulated, accuracy in the control of the output signal is achieved by using digital signals encoded in accordance with a Gray code. In a Gray code the sequence of digitally coded signals is so chosen that there is a change of only one bit between successive coded signals. In the embodiment of the invention which will be described a four-bit inverse Gray code is employed with opto-transducers for reading the code from the tape of tablet.

The present invention will be further understood from the following detailed description of embodiments thereof which is made, by way of example, with reference to the accompanying drawing in which: Figure 1 is a schematic block diagram of a control system in accordance with the present invention.

Figure 2 is a circuit diagram of a preferred embodiment of a control system in accordance with the present invention for providing a variable mark/space output signal for driving a D.C. motor using signals coded in accordance with an inverse Gray code illustrated in Fig. 3, Figure 3 shows a four-bit inverse Gray code applied to give coded information designating an OFF position of a motor and ten operating speeds represented by count states from 0 to 9 inclusive, and Figure 4 is a schematic block diagram of a control system in accordance with the present invention for controlling two motors simultaneously at different speeds.

In the drawings the same or similar parts are designated by like reference numerals.

Referring to Fig. 1 it is assumed that the desired mark/space ratios of the output signal have been encoded in a four-bit code, each of the bits being presented at the devices 1, 2, 3 and 4, which may be supplied directly from a microprocessor or which may be reading heads for reading the code from a medium upon which it has been recorded. The output from each of the devices 1 to 4 is fed to a decoding comparator which also receives output signals from count states in a counter 6 which is stepped by clock pulses fed from a clock pulse generator 7.

The mark/space ratios representing the desired levels of output signals in ascending order of the output signal levels correspond to successive count states of the counter 6 from the first count state upwards. Using a four-bit code there may be sixteen output levels, including zero output signal and the maximum desired output signal. There are thus fourteen possible mark/space ratios representing output signal levels between zero and the maximum. If all these fourteen possible mark to space ratios are used the outputs from the corresponding fourteen count states of the counter 6 are taken to the decoding comparator 5. However, in the embodiment illustrated in Fig. 1 only nine intermediate output signal levels are chosen, and outputs from the nine count states of the counter 6 corresponding to these mark/space ratios are taken to the decoding comparator 5.The counter 6 is conveniently a decade counter and an output from the tenth count state is used to initiate a pulse of the output signal, for example by application of the tenth count state output to a set condition of a two-condition device 8, which may conveniently be a flip-flop.

As already stated the decoding comparator 5 receives the four bits of the four-bit code from devices 1 to 4 and it also receives a sequence of signals from the count states of the counter 6 which correspond to the mark/space ratios represented by the digitally coded signals. The function of the decoding comparator is to recognise a coincidence between the digitally coded input signal received from the devices 1 to 4 and the state of the counter 6 corresponding to the mark/space ratio represented by the digitally coded input signal, and to produce a decoding comparator signal which is applied to reset the two-condition device 8 to terminate the pulse of the output signal.

The function of the decoding comparator 5 can be best understood from an example.

Suppose that the output signal is desired to have the mark/space ratio which is the third of the nine output levels intermediate zero and maximum. A digitally coded signal representative of this third level is received at the devices 1 to 4 and fed to the decoding comparator which will hold the signal while the counter 6 is stepped through its cycle by the clock pulse generator 7. As the counter 6 is stepped to its first count state an output from that first count state is supplied to the decoding comparator. However, this is not the count state corresponding to the mark/space ratio represented by the digitally coded input signal present in the decoding comparator 5, and there is no output from the decoding comparator 5. Similarly, when the counter 6 is stepped to its second count state there is no output signal from the decoding comparator 5. However, when the counter 6 reaches its third count state this state does correspond to the mark/space ratio represented by the digi tally coded input signal in the decoding comparator 5, and the decoding comparator 5 will produce its own output signal which is used to reset the two-condition device 8 and terminate the pulse of the output signal.

The output signal from the two-condition device 8 is thus caused to subsist for a time equal to the duration of three clock pulses, corresponding to the time taken to step the counter 6 through three count states. A sequence of pulses of the same duration will be generated as the output signal from device 8 for as long as the same digitally coded signal is applied to the decoding comparator 5. A change in the applied digitally coded signal will produce a corresponding change in the width of the pulses making up the output signal (i.e. a change in the mark/space ratio of the output signal).

It will be readily appreciated that each clock pulse from the clock pulse generator 7 represents the minimum pulse width obtainable in the output signal of variable mark/space ratio.

Also the clock pulse width, in conjunction with the number of count states used in the counter 5, sets the repetition rate of the output signal.

When the output signal from the control system of Fig. 1 is desired to be at its maximum the digitally coded input signal applied through the devices 1 to 4 is different from any of the signals which correspond to the first nine count states of the counter, and the decoding comparator 5 will not give any output signal to reset the two-condition device 8. There will thus be a continuous signal provided by the two-condition device 8, and this is the maximum output signal provided by the control system, corresponding to an "allmark" signal.

Conveniently, the outputs from the devices 1 to 4 are also connected to suitable means (not shown in Fig.1) for recognising an all low input signal which corresponds to zero output signal and applying a clamping signal to the counter 6 to prevent this from stepping while the all low condition remains.

In Fig. 2 there is illustrated a suitable circuit for carrying out the invention essentially as already described with reference to Fig. 1 It is assumed that the coded signals consist of series of apertures in a tape or tablet which is arranged to slide past an optical-type reading head consisting of four infra-red emitting diodes 11,12, 13 and 14 and four phototransistors 15, 16, 1 7 and 1 8. Each infra-red emitting diode is arranged as a pair with one of the phototransistors, the infra-red emitting diode being on one side of the tape or tablet and the photo-transistor on the other side of the tape or tablet. The four infra-red emitting diodes 11 to 1 4 are supplied in series with current from a D.C. supply via resistor 19.

The forward voltage drops across the four diodes 11 to 14 combine to act like a zener diode and form the D.C. supply for the logic circuits of the decoding comparator 5. Resistors 20 to 23 supply current from the D.C.

supply to photo-transistors 1 5 to 1 8.

The tape of tablet has holes punched therein in accordance with a four-bit inverse Gray code as illustrated in Fig. 3, the holes in the tape or tablet being represented by the white squares in Fig. 3. The tape or tablet may be moved directly or via levers and pivots according to the application required but in any event, when zero output signal is required, the tape or tablet will have its zero or OFF position (where there are no apertures in the tape) located between the four diodes 11 to 14 and the four phototransistors 1 5 to 1 8 so that all the radiation paths are interrupted. In this position there will be a low output from all the four phototransistors 1 5 to 18, which condition is recognised by NOR gate 41 which applies a clamping signal to inhibit the counter 6 and reset it to zero.

When the tape of tablet is moved to position one (corresponding to the first count state (O) in the counter), the inhibit signal is removed from the counter 6 which is then stepped by the clock pulse generator 7. The arrangement of Fig. 2 in which the four diodes are in series also has the effect that, if any one of the infra-red emitting diodes 11 to 1 4 should fail, this D.C. supply to the logic circuits also fails and the counter 6 is automatically inhibited by NOR gate 41. The control system of Fig. 2 is thus inherently failsafe.

The decoding comparator 5 essentially comprises an array of NAND gates to which the outputs of the four photo-transistors 1 5 to 1 8 (corresponding to the four bits of a code pattern) are wired so that one signal or output is provided by the decoding comparator 5 corresponding to each unique code pattern, but only when one of the count states of the counter 6 corresponds to that code pattern.

The decoding comparator 5 may therefore comprise one NAND gate for each of the nine coded signals. However, in the embodiment described only eight NAND gates 24 to 31 are used and additional decoding, comprising diodes 37 and 38 and AND gates 39 and 40, permit the full nine coded signals to be decoded using only eight NAND gates. The first nine count states of counter 6 are also wired to NAND gates 24 to 31, NAND gate 24 being used for both the eighth and ninth count states of the counter 6.

The normal condition of each NAND gate 1 4 to 21 is to produce a high output signal which is supplied to one of eight inputs of NAND gate 36. Consequently, the output of NAND gate 36 is normally low. However, when the digitally coded signal corresponds to the inputs wired to one of the NAND gates 24 to 31 and the counter reaches the count state corresponding to that digitally coded input signal, the output from that particular NAND gate will go low thereby producing a high output from NAND gate 36 to reset the flipflop which in Fig. 2 constitutes the twocondition device 8.

Referring to the modified inverse Gray code shown in Fig. 3, the first bit is used as an ON/OFF signal and thereafter up to count state 7 (level 8 of the mark/space ratio) each digitally coded signal is defined uniquely by the last three bits of the four-bit code signal.

However, count states 8 and 9 (corresponding to the ninth level of the mark/space ratio and to the maximum of continuous mark output respectively) duplicate the last three bits of count states 7 and 6 but are distinguished from them by the reintroduction of the first bit. AND gates 39 and 40 are therefore provided to act as inhibits so that NAND gates 24 and 25 are not permitted to actuate NAND gate 36 when the counter is in count state 7 or 6 and the code selected is intended to represent count state 8 or 9. Thus a decoder -the eight NAND gates 24 to 31 -for a three bit code is effectively used to decode a four-bit code by the addition of the AND gates 39 and 40 to which the other bit of the fourbit code is fed.

The control system described with reference to Figs. 2 and 3 has a particular application in driving the motor of a vehicle such as an invalid carriage. When used in such an application the output from the two-condition device 8 is taken to a conventional power switching output stage to control the supply of current to the motor.

It will be noted that the control system of Fig. 2 includes inverters 32, 33, 34 and 35 to change the sense of certain of the phototransistor outputs in order to facilitate the decoding. These inverters particularly facilitate the provision of the inhibit signal which prevents the counter counting, so that the output signal from the control system is zero.

Certain applications require a motor driven by a control system to be reversed. The control system described herein is readily adapted for such applications by adding an extra opto-coupled pair comprising a fifth infra-red emitting diode and a fifth photo-transistor and incorporating, on the code tape or tablet, a mirror image of the code together with an output from the additional pair. Motor reversing can then be directly commanded.

The actual motor reversing circuit may then use a relay to reverse the polarity of the motor in the conventional way, or to switch the inputs to a semiconductor reversing switch.

In other applications two or more motors may be required to be controlled simultaneously at different speeds. This may be accomplished as indicated diagrammatically in Fig.

4 by using two coded tapes of tablets, one for each motor, and by gating the coded outputs from each tape or tablet synchronously with an equal number of gated flip-flops, one for each motor drive semiconductor circuit. By changing over the gated flip-flops in synchronism with the clock pulse generator, each counter step may be examined twice, once by each gated flip-flop. By multiplexing in this way only one counter 6 and one decoding comparator 5 are needed to control more than one motor.

However, in the multiplexed case, zero motor speed must be obtained by inhibiting the output pulses to each motor drive circuit independently, instead of by inhibiting the counter 6.

Referring to Fig. 4 two strobing signals "strobe 1" and "strobe 2", out of phase with one another, are derived from the clock pulse generator 7 by effectively selecting alternate pulses for each strobing signal. The first strobing signal, strobe 1, is applied to a set of four three-state latches 50 which control the application of a first set of code signals to the decoding comparator 5 and also to a set of gates 52 which control the application of the output signals from the counter 6 and the decoding comparator 5 to the two-condition device or flip-flop 8 providing the signal to the first motor.Similarly, the other strobing signal, strobe 2, is applied to a set of latches 51, which control the application of the second coded signal to the decoding comparator 5, and also to gates 53 which control the application of the output signals from the counter 6 and the decoding comparator 5 to the second two-condition device or flip-flop 8'.

The circuit of Fig. 4 also includes a divider 54 which divides the output from the clock pulse generator 7 by two before this output is applied to the counter 6.

The use of a counter and a decoding comparator in accordance with the present invention enables a variable mark/space output signal to be derived directly from digitally coded input signals, that is to say without the use of any digital-to-analogue conversion.

Furthermore use of the present invention enables an output signal of variable mark/space ratio to be derived from digital signals coded in accordance with a Gray code without any necessity for conversion of the Gray coded signals to an ordinary binary code or to a binary coded decimal form.

The particular embodiment of the present invention which has been described enables a motor to be driven in 10% steps with the minimum of logic circuitry, whilst providing the ability to multiplex.

Also the particular embodiment of the invention which has been described provides a simple circuit, with fail-safe features, suitable for driving the motor or motors of an invalid carriage.

Claims (11)

1. A control system for producing an out put signal of variable mark/space ratio from digitally coded input signals each of which is preselected to correspond to a desired mark/ space ratio, in which a digitally coded input signal is applied to a decoding comparator which is connected to a counter having a plurality of count states each if which corresponds to a desired mark/space ratio, and the instantaneous mark/space ratio of the output signal is directly determined by a signal given by the decoding comparator when the decoding comparator detects a co-incidence between the digitally coded input signal and the state of the counter corresponding to the mark/space ratio represented by the digitally coded input signal.

2. A control system for producing an output signal of variable mark/space ratio from digitally coded input signals each of which is preselected to correspond to a desired mark/space ratio, the system comprising a pulse generator for generating a series of pulses, a counter arranged to be driven by the pulses in said series, a decoding comparator which produces a signal in recognition of the application of a selected digitally coded input signal simultaneously with the presence in the counter of a count corresponding to that digitally coded input signal, and means for determining the mark/space ratio of the output signal in accordance with the time at which the decoding comparator signal occurs.

3. A control system for controlling the speed of a motor which is driven by an output signal of variable mark/space ratio derived from digitally coded input signals each of which is preselected to correspond to a desired mark/space ratio, the system comprising a pulse generator for generating a series of pulses, a counter arranged to be driven by the pulses in said series, the counter having a plurality of count states, each of which corresponds to a desired mark/space ratio, and a further count state, a decoding comparator to which each of the said plurality of count states in the counter is connected, the decoding comparator providing a signal when the decoding comparator detects a coincidence between a digitally coded input signal and the state of the counter corresponding to the mark/space ratio represented by the digitally coded input signal, and means responsive to the further count state of the counter and the occurrence of the decoding comparator signal for respectively initiating and terminating a mark or a space condition of the output signal whereby the mark/space ratio of the motor drive current is determined.

4. A control system according to Claim 3 wherein the said responsive means comprises a two-condition device which initiates a mark condition of the output signal when the counter reaches said further count state and terminates the mark condition of the output signal in response to the receipt of the decoding comparator signal.

5. A control system in accordance with any one of the preceding claims wherein the decoding comparator comprises a plurality of devices each arranged to change its output condition in recognition of the application of a selected digitally coded input signal simultaneously with the presence in the counter of a count corresponding to that digitally coded input signal, and logic means for producing the decoding comparator signal in consequence of a change of output condition of one of the said plurality of devices.

6. A control system according to any one of the preceding claims wherein the digitally coded input signals are coded in accordance with a Gray code.

7. A control system according to any one of the preceding claims in which the digitally coded input signals are read from a digitally encoded member using an optical type reading head comprising a plurality of radiation emitting devices electrically connected in series with one another and a corresponding plurality of radiation responsive devices, the outputs from which are connected to the decoding comparator, and in which the all low signal is utilised as the OFF signal of the code, the system including means for inhibiting the counter upon receipt of the OFF signal.

8. A control system according to Claim 7 wherein a punched tape or tablet has the digitally encoded signals recorded thereon in a series of positions and each discrete position of the punched tape or tablet relative to the reading head corresponds to a level of supply current to a motor.

9. A control system in accordance with any one of the preceding claims wherein multiplexing of the coded signals to the decoding comparator permits a plurality of motors to be independently controlled by independently derived digitally encoded signals using a single decoding comparator and associated counter.

10. A control system according to any one of Claims 1 to 8 in which a motor is controlled from a member bearing a digital code and in which the motor is reversed by using a mirror image of the said code on the member together with an additional code bit.

11. A control system for producing an output signal of variable mark/space ratio from digitally coded input signals substantially as hereinbefore described with reference to the accompanying drawings.