GB2038054A - Multiple channel control systems - Google Patents

Abstract

A control system by which locomotives and accessories in a model railway can be separately and independently controlled by modulating a common power supply for the locomotives and accessories, comprises a transmitter unit for modulating the output voltage of the power supply and a separate receiver associated with each locomotive and accessory. Each transmission is preceded by a pulse-width modulation of the carrier which will produce in each receiver an electrical signal which is immediately compared with stored pre-programmed information so only one receiver will respond to any one particular pulse width to open the channel for the subsequent reception by that receiver of subsequent modulations of the transmission in the form of a plurality of pulses the number of which is decoded to provide information for controlling the speed, direction of a locomotive or operation of an accessory. Security can be added by requiring identity between two pulses of equal duration separated by a given dwell time and by rejecting pulses of incorrect pulse width before an information modulation is counted. <IMAGE>

Description

SPECIFICATION Improvements in and relating to multiple channel control system Field of the invention This invention concerns multiple channel control systems and is particularly but not exclusively adapted for use with model railway systems and the like.

The idea of multiple channel control for model railways thereby allowing more than two engines to be controlled independently whilst operating on a single length of track has been under consideration for some years.

As early as 1 963 a system was available known as the ASTRAC system and this was described in the magazine "Model Railroader" December 1 963 issue in an article by the Editor Linn Westcott.

The ASTRAC system employs alternating current for the power supply to the track and controls the locomotives by switching the motor on and off for a fraction of each pulse of the appropriate half wave of the alternating current supply. The direction is governed by whether a positive or negative pulse is employed and the speed by the duration of the pulse. Transistor switch gear was employed to effect the high speed switching required but the system had disadvantages and limitations on the number of separate locos which could be operated on one track at once.

Latterly two further systems for multiple operation of model locomotives have been developed but at least one of these operates with alternating current power to the track with the attendant problems of alternating current track supply.

It is an object of the present invention to provide an alternative multi channel control system particularly for model railways to allow the independent control of a number of locomotives on a single length of track.

Definition As used herein the expression "single length of track" is intended to mean a loop or complete layout in which all the track is joined together electrically without isolating rails so that a locomotive can be positioned at any point along the length of the layout and can obtain power from the rails for traction and additionally is independently controllable so as to draw either more or less power from the rails and proceed either in a forward or reverse direction as determined by the user.The expression is not intended to eliminate the possibility of isolated sections of rail within a layout for the purpose of providing isolated regions of track for the purpose of allowing a series of controllers to separately control the power supply to isolated sections of track to thereby allow control of power to the locomotives as they pass over the different sections of track, which has been the basis of multiple locomotive operation in certain previous arrangements.

The invention According to the broadest aspect of the present invention a multiple channel control system for independently controlling a plurality of devices comprises a transmitter unit which includes means for modulating the output voltage of a power supply for the devices so as to provide a constant frequency carrier waveform in the output voltage, means for controlling the modulator to interrupt the carrier and produce sequences of bursts of carrier according to predetermined codes or patterns, receiver means associated with each of the devices, each said receiver being adapted to receive and demodulate the carrier and decode the demodulated carrier to produce an electrical signal having a value indicative of each code or pattern of bursts of carrier received by the receiver, means for comparing the said electrical signal with pre-programmed information to produce an identity signal when the said electrical signal corresponds to the pre-programmed information, further means within the receiver for producing a control signal to establish a channel of communication between the transmitter and the receiver upon the successful generation of an identity signal to allow the receiver to receive a subsequent transmission of electrical signal information relating to the operation of the associated device, and means associated with the receiver and the device, responsive to the said subsequent transmission to vary the operation of the device.

The invention is particularly suitable for controlling a number of separate locomotives and accessories of a model railway.

Typically the information relating to operation of a device is in the form of a further sequence of bursts of carrier each burst being of predetermined duration and separated from immediately adjoining bursts of carrier by predetermined time intervals, the number of such bursts determining the actual information which is conveyed to the receiver.In this event a receiver will incorporate decoding circuits for decoding the sequence of bursts of carrier in the said subsequent transmission to produce pulses therefrom, a counter for count ing the pulses, and further decoding means for decoding the final total in the counter according to pre-programmed logic to provide an output signal which will indicate in the case of a model railway loco the direction of travel and the precise speed at which it is to travel as determined by the polarity and cur rent available for driving the locomotive motor.

Where accessories are to be controlled on the locomotive or in the train associated with the locomotive, these may be switched on or off as the case may be by certain other decoded outputs from the receiver.

The bursts of carrier which are demodulated and decoded by comparison with pre-programmed information in the receiver are of accurately defined duration and are related to the number of carrier frequency pulses which are occurring during the burst. It will be seen therefore that by providing a possible carrier burst of up to 99 carrier frequency pulses, up to 99 different channels can be selected by transmitting accurately either one, two or any number up to 99 consecutive carrier frequency pulses as an identity signal.

By providing an appropriate number of receivers each having pre-programmed information which will allow the identification of any one of the numbers between 1 and 99 inclusive so any one of the receivers can be addressed by its appropriate identifying signal made up of a burst of carrier containing the appropriate number of carrier frequency pulses.

In a development of the basic system, the accuracy of identifaction is improved by proving two bursts of carrier and requiring that each receiver is identified by two numbers each in the range 1 to 99 and by arranging that only if the two numbers are received correctly and in the correct order will the channel for further information from receiver to transmitter be opened.

By appropriate selection of digits from those available so up to 99 unique number sequences can be selected so that there is virtually no possibility of noise or lost pulses causing an incorrect address of a locomotive to occur.

The modulation of the direct current supply output voltage can be 100% or may to advantage be a reduced percentage (such as 50%) so that instead of reducing the output to zero, it is only reduced to 50% of its normal value by the modulating signal so that a D.C. carrier always exists. By providing a D.C. carrier detector circuit in each receiver, a further safeguard can be built into the system to ensure that in the event of an interruption of carrier the receiver is immediately reset and will await the next address signal or reopening of the information channel before acting on any information received.It will be appreciated that with 100% modulation, there is a break in carrier for each pulse of the carrier so that an interruption of the carrier due to a fault may in fact result in a mistake occurring in the decoding of the address information by a receiver and the incorrect locomotive being addressed.

Other provisions may be made to reduce the risk of decoding mistakes occurring due to noise spikes and temporary interruptions of the supply and/or the carrier.

Typically the incoming signal to the receiver is demodulated so as to produce a chain of pulses the first of which is of a width which can be decoded to determine which of the receivers is to respond to the remainder of the signal and the latter constitutes a series of equal duration pulses separated by equal periods of time the sum of which defines the action to be taken. In the demodulator stage the modulated carrier is converted into the sequence of pulses and the duration of the first of these pulses is determined by an indentification pulse detector circuit which looks for a pulse of precise duration and only produces an output signal if such a pulse is received.The output pulse is used to reset the binary counter and to set a timing device which determines the period during which the incoming demodulated pulses are to be counted the sum of which is to define the action to be taken. The period is referred to as the data period and at the beginning of this period a signal is generated to enable the clock input of a binary counter to which the demodulator output signals are also supplied.

The counter is therefore reset at the beginning of the data period and is then caused to count the pulses which are subsequently received from the demodulator stage until such time as the data period ends as determined by the timing device.

In order to build in additional security a data pulse detector is inserted between the output of the demodulator circuit and the clock input to the binary counter so as to respond only to pulses having a fixed pulse width and all the pulses which are to be counted during the data period are controlled to within a close tolerance of single pulse width of for example 25 microseconds. By ensuring that the data pulse detector will not pass any pulses other than pulses having the set data pulse width so the clock input of the binary counter is prevented from receiving anything except data pulses as transmitted by the transmitter. Spurious noise spikes and any other demodulated signals which previously would have been counted by the counter are therefore prevented from being included in the total.

A second level of security is provided by requiring the identification pulse to be made up of two separate pulses of predetermined duration spaced apart by a given quiescent period or dwell time. To this end the identification pulse detector circuit is arranged to respond only to the presence of two identification pulses of appropriate width and spaced apart by a given dwell time so as to again render the circuit insensitive to spurious pulses which might be detected by the identification pulse detector. The chance of two such pulses being received with a given dwell time therebetween is so small that the possibility can be virtually ruled out.

A third level of security can be provided by altering the decoding of the output of the counting circuit so that the lowest two bits of information are unused so as to increase noise immunity. Where the first two bits of information are employed, one or two noise spikes demodulated and seen by the receiver as data pulses can produce undesirable changes of direction or speed and by eliminating the bottom two bits of information the presence of one or two noise spikes in the data pulse period will not produce any undesirable results.

Typically the data period is of an extent sufficient to transmit 255 pulses each of 25 ,uses. duration and for simplicity the output of the counter to which the data pulses are supplied as a clock input is arranged to be in the so-called binary form. It will be seen that eight on/off outputs can be used to express any number up to and including 255 and in a simple decoding arrangement the first five output lines corresponding to 20 through to 24 denote the speed required from the loco, the next output level corresponding to 25 provides the on/off output, the next output level corresponding to 26 provides the forward or reverse direction signal and the seventh output signal level corresponding to 27 allows an accessory on the locomotive to be switched on or off.

If security is required the lowest two output levels may be ignored corresponding to 20 and 2' and the speed range governed by the next four output levels corresponding to 22 through to 25. In this event the output level corresponding to 26 provides the on/off information and the seventh level corresponding to 27 provides the forward and reverse direction signals.

By arranging that the one output of the 26 level switches the locomotive off and the one output of the 27 level corresponds to the forward control signal for the locomotive a chance pulse at full speed will simply stop the locomotive rather than change its direction.

A single transmitter may be used with suitable controls for setting up appropriate sequences of pulses from the transmitter so as to address one or other of a plurality of receivers located in locomotives or other movable devices which are electrically connected to the transmitter via the conductive rails or like connections. If the mode of operation of one locomotive is to be changed (for example the locomotive is to be started from rest) the appropriate code number for that locomotive may be dialled into the transmitter or an appropriate switch corresponding to that locomotive may be operated, so that the identification pulse having a width corresponding to the pulse width detector circuit within the receiver of that locomotive will be generated by the modulator within the transmitter.The desired change of state of the locomotive is then selected by adjusting the controller associated with the transmitted so as to indicate forward direction and speed of for example one-quarter speed and thereafter a send or transmit button may be pressed to transmit first of all the identification pulse and then at the specified interval thereafter data pulses corresponding to a forward speed at onequarter full speed to the locomotive which has been addressed.

By providing electrical latches within the receiver so as to hold the last binary output from the counter until such time as the counter is re-addressed, the locomotive which has been addressed in this way will continue to move in a forward direction gathering speed until it has reached the desired speed of for example one-quarter full speed until such time as the locomotive is subsequently addressed and fresh information in the form of a new series of data pulses supplied to the counter of the receiver in the locomotive.

If immediately after the first locomotive has been addressed and has responded to its data pulses information is required to be sent to a second locomotive the procedure can be repeated but this time the code number or the appropriate switch for the second locomotive is selected so as to determine the appropriate identification pulse width so that the receiver in the second locomotive is addressed and data pulses corresponding to the change of state required of the second locomotive will be transmitted after the identification pulse when the transmit or send button on the transmitter is depressed.

Whilst this arrangement will suffice on smaller layouts and is adequate for two-train operation, multiple train operation requires a more sophisticated arrangement and here whilst a single transmitter is employed, separate memory devices in the form of independent controllers are provided one for each of the locomotives which have to be controlled and separate receivers are mounted on each of the locomotives as before.The transmitter includes a control circuit which causes each of the controllers to be addressed in turn and the information stored in the controller corresponding to the mode of operation required of the engine to which the controller relates is transmitted in the form of an indentification pulse (which will be recognised by the receiver of that locomotive) followed by the data pulses corresponding to the mode of operation required each time the transmitter addresses the controller for that locomotive.In this way information will be transmitted to each of the receivers on each of the locomotives in a continual sequence and by employing a high switching rate and a high carrier frequency of typically 1 mHz, a virtually instantaneous response can be obtained as between changing the desired mode of operation of any particular locomotive and the actual bringing about of the desired change in the locomotive's performance.

As applied to a model railway, the transmitter is preferably incorporated into a master or base Unit which also contains a power supply and provides electrical connections to the track and separate channel controllers are provided which conveniently are adapted to be plugged into one another on an add-on basis side by side so as to allow any number of controllers within the capacity of the sys tem to be added on.

Each of the channel controllers typically includes an on/off switch, a forward reverse switch and a speed control. Where the decoding circuits provide for an accessory to be switched on the loco, a further switch may be provided for controlling the on/off condition of the accessory on the loco. In addition to those basic controls each channel controller preferably incorporates an adjustable switch or thumb-wheel operated switches or the like for selecting which of the channels the controller is to relate to and therefore which of the locomotives in the layout is to respond to the settings of the switches and speed controller etc. thereon.

According to a preferred feature an indicator lamp or other device for indicating an on/off mode of operation may be provided on each channel controller and provision within the system is made to cause the lamp or other device to be switched into an on mode when the controller is "on line" and to cause the lamp to be extinguished when the controller is no longer "on line". The "on line" condition is determined by the addressing circuits associated with the master or base unit which are arranged to address the channel controllers in turn in strict sequence.

Where the channel controllers are used with a simple non-scanning master or base unit a further switch is provided for switching the channel controller "on line" and means is provided within the system for ensuring that if one controller has been switched "on line" none of the others can gain access to the transmitter unit until after the identification pulse and data pulses from the last channel unit to select "on line" condition have been transmitted.

Where a channel is provided solely for an accessory the channel controller unit may be of similar design to the channel controller units for the locomotive and may be adapted to be plugged in in an add-on manner to the locomotive controllers and since only on/off conditions are required of the accessory or accessories under control of the accessory controller the controls thereon are typically on/off switches each designated with an appropriate designation indicating the particular accessory or accessory function which it relates to. As before the controller preferably includes a switch or thumb-wheel operated switches or the like to allow the appropriate channel to be selected and a status lamp may be provided to indicate when the channel controller is "on line".

The invention will now be described by way of example with reference to the accompanying drawings.

In the drawings Figure 1 is a block circuit diagram of a basic receiver unit for use in a multiple channel control system embodying the invention, Figure la is a graphical representation of part of a modulated carriet to which the receiver of Fig. 1 responds, Figure lb is a tabulation of a typical binary code which may be used in a system incorporating the receiver of Fig. 1, Figure 2 is a circuit diagram of the signal power supply separator stage of Fig. 1, Figure 3 is a circuit diagram of the demodulator and pulse shaper stage of Fig. 1, Figure 4 is a circuit diagram of the identification pulse detector stage of Fig. 1, Figure 4b is a graphical illustration of the mode of operation of the circuit of Fig. 4 in response to a given input signal, Figure 5 is a circuit diagram of the data period selector employed in Fig. 1, Figure 6 is a circuit diagram of the binary counter with latched outputs as employed in Fig. 1, Figure 6a is a graphical representation of the mode of operation of the circuit of Fig. 6, Figure 7 includes the circuit diagram of the digital to analogue converter of Fig. 1 and additionally includes a constant current source for supplying the converter circuit, Figure 7a is a graphical representation of the output voltage relative to the binary input signal value for the circuit of Fig. 7, Figure 8 is a circuit diagram of the forward/reverse selector stage of Fig. 1, Figure 9a is a circuit diagram of a first accessory circuit for controlling lamps on a model locomotive or in the coaches hauled by a model locomotive, Figure 9b is an electrical circuit diagram of an accessory which may be fitted to a locomotive or any rolling stock in a model railway which will automatically cause the rolling stock or locomotive to become uncoupled from an adjoining piece of rolling stock and Figures 9c, 9d and 9e illustrate the uncoupling device actuated by the solenoid contained in the circuit of Fig. 9b, Figure 9f is a circuit diagram of a whistle simulating module which may be incorporated into rolling stock in a model railway as an accessory, Figure 10 is a block circuit diagram of a receiver based on the design of receiver shown in Fig. 1 but incorporating an additional data pulse detector and a second identification pulse detector for security, Figure ii is a circuit diagram of the second identification pulse detector, Figure 1 1a illustrates the form of the two identification pulses in the modified transmission required to operate the modified receiver of Fig. 10 and Figure 1 ib illustrates graphically the mode of operation of the circuit shown in Fig. 11, Figure 12 is an alternative digital to analogue converter circuit based on the circuit of Fig. 7 but modified so as to ensure that stray pulses do not produce undesirable changes of operation of the model locomotive, Figure 12a is a tabulation of the binary decoding effected by the converter and illustrates how the lowest two levels of binary number are not used, Figure 13 is a block circuit diagram of a transmitter unit for use with a receiver unit of the type shown in Fig. 10, Figure 14 is a circuit diagram of part of the serial sequence generator of Fig. 1 3 and comprises the identification pulse selector part thereof, Figure 15 is a circuit diagram of a further part of the serial sequence generator of Fig.

1 3 and comprises the second identification pulse selector required in the serial sequence generator, Figure 16 is a circuit diagram of a third and last section of the serial sequence generator unit of Fig. 1 3 and comprises the data selector section thereof, Figure 17 is a circuit diagram of the modulator of Fig. 13, Figure 18 is a circuit diagram of the control logic section of the transmitter of Fig. 13, Figure 19 is a circuit diagram of the interface unit contained in the transmitter of Fig.

13, Figure 20 is a circuit diagram of the crystal oscillator and dividers for producing the carrier signal used in the transmitter of Fig. 13, Figure 21 is a circuit diagram of the power supply associated with the transmitter of Fig.

13, Figure 22 is a circuit diagram of a channel controller for controlling up to eight separate accessories each having a simple on/off mode of operation, Figure 23 is a circuit diagram of a channel controller suitable for controlling the on/off, forward/reverse and speed of operation of a model locomotive, Figure 24 is a perspective view of different modules which can be plugged together to form a console from which a model train can be controlled, each of the modules comprising part of the transmitter and/or channel controller units of which the circuits have been shown in preceding Figures, Figure 25a illustrates one embodiment of channel controller fascia for controlling a locomotive, Figure 25b is a similar view to that of Fig.

25a of the fascia of a channel controller of a different design for controlling a locomotive, Figure 26a illustrates the fascia of a channel controller for accessories and Figure 26b illustrates an alternative fascia for an accessory channel controller.

Detailed description of the drawings A receiver is shown in Fig. 1 having input terminals 10 and 1 2 which, when the receiver is mounted in a locomotive or rolling stock of a model railway are electrically connected to two conductive rails.

The signal appearing at the input of the receiver comprises a D.C. signal and a 1 mgH carrier superimposed thereon which itself is modulated as will hereinafter be described. A separator stage 14 separates the 1 mgH carrier from the direct current component and supplies a modulated carrier signal as an input to a demodulator and pulse shaper stage 1 6.

This provides an output for a detector 1 8 and also a signal to the clock input of a binary counter 20.

The detector 1 8 looks for a particular pulse width in the demodulated signal and produces an output signal at junction 22 only after a pulse of predetermined width has been received. This signal serves as a reset signal for the counter 20 and also an input to a data period selector stage 24.

Circuit 24 defines a precise period of time during which the signals from the demodulator and pulse shaper stage 1 6 can clock the binary counter 20 and to this end the output of circuit 24 is shown as a clock enable input to the binary counter 20.

Counter 20 is not a simple counter but includes latches through which the binary signal data is transferred and which serve to hold the particular binary number in the output of the counter until the next message is transmitted. The counter and latches will be described in more detail with reference to Fig.

6.

Part of the latched output of the counter 20 serves as an input to a digital to analogue converter 26.

One of the binary levels (level 2 to the power of 6) serves an input to a forward/reverse selector 28, the 1 condition in the 26 output denoting forward and 0 condition in the 26 output denoting reverse. The selector circuit is shown in more detail in Fig. 8 and will be described in relation thereto.

The highest binary level (27) constitutes a control signal for a locomotive accessory denoted by reference numeral 30. The 1 condition may be arranged to switch the accessory on and the 0 condition to switch the accessory off.

The modulation of the input signal to the terminals 10, 12 is shown in Fig. 1a. The 1 mgHz carrier is shown at 32 and a particular controlled duration burst of 1 mgHz carrier denoted by reference numeral 34 constitutes an identifying pulse the duration of which is typically the whole number multiple of a fixed time period such as 1.00 jusecs. The invention is intended to be used in systems where a number of different receivers are connected to the common track and by arranging that each of the receivers will only respond to an identification pulse of a unique pulse width, information can be supplied selectively to one or another of the receivers by first of all transmitting a burst of carrier frequency having the precise duration corresponding to the programmed pulse width of the identification pulse detector 18 in the receiver to which the information is to be sent.

Immediately after the identification pulse the carrier signal is modulated so as to present a sequence of short fixed duration bursts of carrier typically 25 psecs wide and in the system to be described it is determined in advance that there will be no more than 255 such pulses in the information or data period which is denoted by reference numeral 36.

Each of the data pulses is similar to the others and the first of these is denoted by reference numeral 38.

A simple code is employed to convey different pieces of information to the receiver and to allow this information to then be processed and produce the appropriate response in the locomotive or rolling stock or accessory as required. In the system under consideration the code is a simple numerical one so that different levels of operation, speed, direction, etc. correspond to different numbers in the range 1 to 255.

in the receiver shown in Fig. 1 the binary counter 20 has a maximum capacity of 255 so that the full 255 pulses available during the data period may be used.

Fig. 1 b illustrates the coding of the information which is transmitted during the data period 36. By allocating the higher binary levels to the more crucial decisions such as on/off and forward/reverse (and in the case of an accessory associated with the locomotive the level 27) any inaccuracy in the number of pulses received due to noise or faults such that one or two pulses are missed or accidentally added into the sequence, will only result in an incorrect speed setting for the loco.

It will be seen therefore that if full speed forward is required 1 27 pulses will have to be transmitted producing in the output of the binary counter 20 the binary number indicated below:01111111 Clearly the binary code itself could be transmitted so limiting the number of pulses which would have to be transmitted but it will be appreciated that the loss or gain of one pulse would then be very crucial and it is felt that the transmission of a number of discrete pulses which are then counted and a binary number recreated therefrom is less prone to interference and inaccuracy from noise etc.

than the alternative arrangement. However it is to be understood that the invention is not intended to be limited to the transmission of the pulses such as 38 which then have to be decoded into a binary form and the alternative arrangement is envisaged within the scope of the invention.

Fig. 2 illustrates the circuit of section 1 4 of Fig. 1. Where appropriate the same reference numerals have been used.

The invention is most applicable to a layout employing a D.C. energisation of the track.

This provides safety since the supply is easier to regulate and to incorporate short circuit cutouts and thermal overload protection as is well known. In addition expansion of the layout can be accommodated very easily since floating direct current supplies may be parallelled to increase the total current output of the power supply to the layout.

In the circuit of Fig. 2 the diode bridge formed from diodes D1 to D4 inclusive ensures that no damage occurs to the later receiver circuits if the locomotive is reverse positioned on the track and the effect of the bridge is that the later circuits are still fully operational irrespective of the directional positioning of the locomotive on the track.

A signal for the demodulator and pulse shaper circuit 1 6 is provided from the secondary winding of a transformer T1 and is denoted by V2. The primary of the transformer T1 is connected across the track through a series capacitor C1 typically of 0.1 mF capacity.

Two chokes L1 and L2 typically of 10 mH inductance are connected in series between the track and the two inputs to the diode bridge D1 to D4 and the input to the bridge is itself bridged by a smoothing capacitor C2 of typically 0.1 mF capacity.

The output of the bridge is also bridged by a capacitor C3 of typically 47 mF capacity and a stabilised voltage. VB is obtained using a zener diode D5 typically having a cutoff voltage of 1 5 volts connected in series with a resistor R 1 the value of which is selected according to the current requirements of the later circuits to be connnected to VB. An unstabilised supply VA is available between terminals 40, 42. Simply for convenience the terminals at which the stabilised voltage VB is obtained is denoted by reference numeral 44.

The circuit of the demodulator and pulse shaper stage 1 6 is shown in Fig. 3. The input voltage V2 is applied to the base of transistor TR1 (typically type BC147) via diode detector circuit formed from diode D6 (type 1 N9 14) and resistors R2 and R3 and capacitor C4 the values of which together with the values of the other components employed can be obtained from the table at the end of the de scription.

TR1 forms one-half of a Schmidt trigger circuit of which transistor TR2 forms the other part and the output signal across R5 serves as the input signal to an identification pulse detector circuit shown in Fig. 4. The common input/output junction is denoted by reference numeral 46 in Figs. 3 and 4.

The detector circuit comprises two monostable dual devices IC1 and IC2 which are connected in the positive triggered, retriggerable mode. By setting R6 and R7 so the reset times of the two mono-stable devices IC1 and IC2 can be set to fine limits so as to define a very short duration period just before and just after the trailing end of an input pulse of correct duration which will cause an output signal to appear at junction 48. This junction is the output of a logic circuit made up from two logic NAND gates IC4 and IC5 the inputs of which are supplied from the Q and Q bar outputs of the devices IC1 and IC2 and from the output of an inverting amplifier IC3 as shown.

IC5 has three inputs and only when all are high will a 0 signal be generated at junction 48. At all other times junction 48 will be high.

Referring to Fig. 4b it will be seen that the input condition for IC5 is only satisfied in the event that an input pulse is received (pulse 50) which is slightly longer in duration than the relaxation period of mono-stable circuit ICS denoted by pulse 52 and is just shorter in time than the relaxation period of device IC2 denoted by pulse 54. In this situation, IC1 resets before the trailing edge of pulse 50 so that there is a short period of time denoted by the output pulse 56 after the trailing edge of the pulse 50 and before the trailing edge of the pulse 54 (denoting the reset of IC2) during which all three inputs to the NAND gate IC5 are high.This produces a short duration low denoted by pulse 56 in the output of the NAND gate IC5 and this signal indicates that an identification pulse has been received by the circuit of Fig. 4 having a duration which is within the tolerances set by the two monostable relaxation periods set by R6 and R7 and denoted by 52 and 54 and the pulse 56 will be referred to as an ident pulse.

Until an ident pulse appears at junction 48 none of the remainder of the circuit of the receiver can respond to any incoming pulses at junctions 10 and 1 2. However once an ident pulse has appeared at junction 48 (which corresponds to junction 22 in Fig. 1) the data period selector circuit which will now be described with reference to Fig. 5 is triggered and the ident pulse also serves as a reset signal for a binary counter to be described with reference to Fig. 6.

Referring now to Fig. 5, the data period selector comprises a monostable device IC6 connected in the negative triggered non-retriggerable mode. A variable resistor R8 sets the relaxation period to an exact interval typically 12.7 milliseconds which is sufficient to allow 250 data pulses each of 25 microseconds duration and spread apart by 25 microsecond gaps to be received. The beginning of the data period coincides with the end of the ident pulse and accordingly the latter is made of predictable duration by careful selection of the relaxation periods of the mono-stable devices IC1 and IC2 and the duration of the identification pulse 34 which produces the demodulated pulse 50.

The device IC6 produces a high output at output terminal 58 when the device is triggered and a low output when the device resets as it does at the end of its 1 2.5 millisecond relaxation period.

As shown in Fig. 1, the terminal 58 is connected to the clock enable input of a binary counter circuit to be described in relation to Fig. 6.

Turning now to the binary counter, junction 48 in Fig. 4 is connected through an inverting amplifier IC7 to the reset A and reset B inputs of a dual 4-bit binary counter 20.

The clock enable input for section A of the counter is connected to junction 58 in Fig. 5 and the clock input to section A of the counter is connected to terminal 46 in Fig. 3.

An ident pulse at junction 48 therefore resets the counter 20 and subsequent data pulses such as 38 occurring during the data period 36 (see Fig. la) will register in the binary counter 20. At the end of the data period determined by 24, the clock enable input from junction 58 is removed.

The clock enable input for section B of the dual binary counter is connected to the 04A output of the A section of the counter and the eight binary outputs Q1 B to 04B are connected to the inputs D of a dual 4-bit latch formed by devices IC9 and IC10. The two clock inputs of these two devices are supplied from the junction 58 so that when the clock enable signal is removed the two 4-bit latches transfer data from the outputs of the counter to the outputs of the latches to preserve the binary coded information in the output of the counter until such time as a further ident pulse and fresh data has been received by the receiver.

The eight lines are denoted by 20 through to 27.

Fig. 6a illustrates the relationship between the ident pulse received from circuit 4 and denoted by reference numeral 62 and the pulse which is referred to as data select and which appears in the output of the data code selector 24 and is denoted by reference numeral 64.

Before the binary information can be converted into speed control etc. a digital to analogue conversion is required and the cir cuit for the digital to analogue conversion of the outputs from the latches IC9 and IC10 is shown in Fig. 7. The inputs from latch outputs 20 through to 25 control the base current of six transistors TR4 to TR9 and except for TR4 each includes a load resistor which limits the output current of the transistor when switched on. The relationship of R12 through to R16 is such that if R13 is denoted by a resistance R, R12 has a resistance of R . 2, R14 a resistance of 2 X R, R 1 5 a resistance of 4 x R and R16 a resistance of 8 x R.

The values of the resistors R 1 2 to R 1 6 depend on the value of the output resistor R11 for transistor TR3 the base current of which is very closely controlled using a zenor diode D7 and resistor R9. Typically R11 is 1000 ohms.

Transistor TR3 provides a constant current feed for the line 66 which in turn supplies the current to the base of transistor TR 10 which in turn controls the base current for TR 11 the emitter of which is connected to junction 40 in Fig. 2 and the collector of which is connected to a junction 68 (see Fig. 7) from a voltage Vc is obtainable.

TR11 is a power transistor in the sense that the full load current for the motor must pass across the junction of TR 11 and the transistor is selected accordingly.

A smoothing capacitor C8 and diode D9 remove unwanted spikes and a diode D8 and resistor R 1 7 provide the return path for the current through transistor TR 10.

The digital to analogue conversion law followed by the circuit of Fig. 7 will be determined by the values of the resistors R 1 2 to R 1 6 amongst other factors and by using the values indicated a particularly non-linear digital to analogue conversion is obtained the characteristic of which is illustrated graphically in Fig. 7a. This shows the value of V out (the voltage of line 66) relative to the value of the number of the binary input to the circuit. It will be seen that this provides fine control at slow speeds to allow for more realistic shunting and acceleration etc.

It will be appreciated that the digital to analogue conversion law could be linear by providing appropriate values for resistors R 1 2 to R 1 6 and the invention is not limited to the use of the particular nonlinear digital to analogue conversion characteristic denoted by Fig.

7a nor to the particular values of resistors R12 to R16 that includes any digital to analogue converter which will provide a fixed relationship between the binary input to the value of Vc.

It is also to be noted that only levels 20 through to 24 provide speed control and the binary level 25 provides the on/off control via transistor TR4.

The other two binary levels 26 and 27 provide switching as described in relation to Fig. 1.

To this end the 26 binary level is supplied to junction 70 in Fig. 8 which represents the circuit of the forward/reverse selector stage of Fig. 1. This comprises a complementary bridge circuit made up from transistors TR 1 2 through to TR1 7 one input of which is supplied directly from junction 70 via R 1 9 and the other through R23 and an inverting amplifier Icy 1. The outputs of transistors TR 12 and TR15 supply the line current for a motor (not shown) connected to terminals 72 and 74 through to 10 mH inductors L3 and L4.

Changing the level of the binary input at junction 70 causes the polarity of the terminals 72 and 74 to be reversed.

In view of the large amount of data which the system embodying the invention can transmit, the final binary level can be used to switch an accessory mounted on the locomotive or on rolling stock connected to the locomotive and various examples of such accessories are illustrated in Figs. 9a through to 9f.

Fig. 9a shows how lighting either on the locomotive or in following coaches can be controlled by connecting the 27 output from IC10 to terminal 76 in Fig. 9a for controlling the base current of the transistor TRA connected in series with the lamp or lamps generally designated 78.

Fig. 9b and Figs. 9c, 9d and 9e illustrate an uncoupling module which can be fitted to a locomotive. As shown in Fig. 9d the coupling hook 80 is pivoted at point 82 to a bracket 84 which is secured to the underside of the locomotive. A solenoid shown in Figs.

9c and 9e is mounted underneath the bracket 84 and the solenoid is a so-called push action solenoid which is mounted so as to produce a thrust in the direction of the arrow 86 in Fig.

9d so as to move the hook 80 in a generally upward anticlockwise direction. The solenoid is generally designated 88 and the winding of the solenoid is connected in series with a transistor TRA shown in Fig. 9b the base current of which is controlled -from the 27 output of latch IC 10.

A further alternative accessory is shown in Fig. 9f which comprises a circuit for generating sound from a loud speaker which simulates a steam whistle. The circuit is intended only to be illustrative and will not be described in detail. Suffice to say that the pitch of the sound produced by the loud speaker LSA must be varied and noise must be introduced into the signal supplied to the loud speaker so as to produce a realistic steam whistle sound. To this end TRB is connected as a phase shift oscillator having a basic pitch of 100 Hz. Diode DA is a noise diode giving 50 mV of white noise and transistor TRC serves as a summing transistor for combining the pitch and the noise. Feedback to the base of transistor TRB via CL DB and RV causes the pitch to vary and transistor TRD serves as a driver for the loud speaker LSA.

Operation of the circuit in inhibited until base current is available for transistor TRA which is only the case when the appropriate binary condition appears in the output of binary level 27 of IC10.

Fig. 10 illustrates an alternative and improved receiver circuit based on Fig. 1. The additional features incorporated into Fig. 10 are not essential to the invention but provide a degree of security against incorrect data being supplied to the control circuits which are controlled by the output from the receiver.

The improved circuit of Fig. 10 is of particular application in a large model railway layout where the possibility of stray pulses appearing is greater than on a small layout.

The first modification involves a data pulse detector denoted by reference numeral 90.

This circuit is essentially the same as Fig. 4 but with the two mono-stables set to select a 25 microsecond data pulse width and to reject any other pulse. It will be appreciated that the clock input of the counter 20 in Fig. 1 will count all pulses subsequent to an ident pulse at junction 22 which arise during a data period as determined by the selector 24. By incorporating the data pulse detector 90 pulses which are not exactly 25 microseconds in duration will be rejected so that any stray pulses occurring during the data period determined by selector 24 will not be counted by the counter 20.

The second modification (which requires modification of the received signal) requires that two identification pulses must be transmitted with a particular dwell time between them and both must be received before any action is taken. Typically the two identification pulses are of the same width (although it will be appreciated that this need not necessarily be the case) and the second identification pulse detector which is denoted by reference numeral 92 in Fig. 10 is shown in detail in Fig. 11.

The input to the circuit of Fig. 11 is the output from junction 48 of Fig. 4 and is denoted by reference numeral 22'. The output of circuit 11 is denoted by reference numeral 22 which therefore corresponds to junction 22 in Fig. 1 and Fig. 10.

The circuit comprises a mono-stable device IC13 set to relax after a fixed period of time.

The input from terminal 22' is inverted by inverting amplifier IC12 which constitutes a negative trigger for IC13 and this inverted input is supplied as one of the inputs to a NAND gate IC14 the other input of which is the Q output of the device IC13.

By making the relaxation period of the mono-stable device IC13 equal to the width of the ident pulse 96 plus the dwell time typically 50 ysecs, the circuit will produce an output signal corresponding to the second identification pulse produced by the identification pulse detector 1 8 (since both the pulses are of the same duration) and Fig. 11 b illustrates the relationship between the inputs and outputs signals. The output from the identification pulse detector 1 8 is shown at 98 and the trailing edge of the first ident pulse from 18 triggers the device IC13 to produce the Q output pulse denoted by reference numeral 100.

At the end of the second identification pulse the detector 1 8 produces a second ident pulse at 98 and because the Q output is already high, the NAND gate IC14 is satisfied for the duration of the second ident pulse which is transmitted to junction 22.

The third refinement lies in the digital to analogue converter circuit and subsequent switching circuits. This modification is shown in more detail in Fig. 12 and Fig. 1 2a which illustrate the binary codes used.

The basic improvement lies in not using the lowest two binary levels so that noise spikes ripping through the system will no longer cause a change of direction which could occur using the basic system of Figs. 1 to 9.

To this end speed control is obtained using the four levels 22 through to 25 (see Fig. 1 2a) and off/on operation is obtained using the high and low outputs of level 26 and the forward and reverse control is obtained using the high and low outputs of level 27.

The converter circuit includes a constant current source formed by TR18 and diode D10 in the same way as transistor TR3 and diode D7 provides it in Fig. 7. The line 102 in Fig. 12 is similar to the line 66 in Fig. 7 and transistors TR24 and TR25 and diodes D11, D12, R31 and C 1 0 serve the same purpose as the corresponding components in Fig. 7.

Connected to the line 102 are five transistors TR19 through to TR23, transistors TR20 to TR23 inclusive being connected thereto through resistors R27 through to R30 respectively. The values of resistors R27 to R30 are selected so as to give an appropriate digital to analogue conversion characteristic and reference is here made to the description of Fig. 7 to indicate how the relationship of resistors R27 to R30 and resistor R27 will vary the relationship.

Base current for transistor TR 1 9 is obtained from a NAND gate IC15 which is only satisfied if the 26 level is high and at least one of the speed control lines (levels 22 through to 25) is high. This is achieved using an OR gate IC16 and an inverting amplifier IC17 between the 26 output and the input to IC15 to which it is supplied.

Depending on the number of pulses received so none or some of the transistors TR20 to TR23 will be rendered conductive and when the unit is switched on by the level 26 output going high the appropriate base current flows for TR24 and TR25 to produce the appropriate level of Vc for supplying to the motor.

In this connection it will be noted that the controlled voltage Vc is supplied to junction 104 in Fig. 8 and referring back to Fig. 7 the output voltage Vc obtained from junction 68 in the previously described digital to analogue converter circuit shown in Fig. 7 is of course available for supply to junction 104 in Fig. 8 in the event that the basic digital to analogue converter circuit shown in Fig. 7 is employed.

Whereas with the D to A converter- circuit of Fig. 7 full speed in the forward direction is denoted by the binary number 01111111 the corresponding binary number for full speed in the forward direction using the D to A converter of Fig. 1 2 is denoted by binary number 001111X-X It will be seen that if an additional one pulse appears in the Fig. 7 circuit, the locomotive will in fact be reversed in direction and since the appearance of a single stray pulse during a data period could occur the arrangement of Fig. 12 will be seen to represent a significant advantage since in the event that additional pulses arise when travelling at full speed in one direction or the other, the additional pulses will simply cause the locomotive to be turned off without reversing direction.

Whilst neither effect is desirable, the latter effect is less devastating than a sudden reversal of direction at full speed.

Figs. 1 to 1 2 have illustrated the basic receiver and modifications that can be made to the basic receiver. Figs. 1 3 et seq illustrate the transmitter which is used to produce the trains of pulses required for controlling the receiver circuits previously described.

Fig. 13 is a block circuit diagram of a transmitter unit formed from a single base unit denoted by the dotted line 106 and a number of separate channel controllers of which three are shown at 108, 110 and 112.

The base unit essentially comprises a power supply 114 the output of which is modulated by a modulator 11 6 for supply to the track and for consistency the terminals to which the output of modulator 11 6 are shown as connected are denoted by the reference numerals 10 and 1 2 which correspond to the input terminals of the receiver. 10 and 1 2 can therefore be thought of as the track.

The modulator 11 6 is itself supplied with a carrier signal from a crystal controlled master oscillator and divider network denoted by reference numeral 118 and also by control pulses from a serial sequence generator 1 20.

This circuit is itself controlled by control logic 122 which produces a sequence start signal on line 1 24. A signal indicating that a sequence of pulses has ended is supplied back to the control logic 1 22 along line 1 26.

In addition the serial sequence generator 1 20 receives information relating to the address of the receiver to which information is to be sent in the form of an 8-bit word on an 8bit address bus 1 28 and in addition an 8-bit data bus 1 30 supplies the data to be transmitted as information to a receiver after it has been addressed and is ready to receive the data.

An interface unit 1 32 serves to relay the data information on the data bus 130' which connects the channel controllers 108, 110, 11 2 to the interface unit 1 32 and also receives the address information on the 8-bit address bus 1 28 from the control logic 1 22 and relays this to the channel controllers 108, 110, 112 on the address bus 128'. A status bus 1 34 serves to indicate to the control logic 1 22 when any particular channel controller 108, 110 or 11 2 has been addressed correctly.

The channel controllers 108, 110 or 11 2 are connected in parallel to the three bus bars 128', 130', 1 34 and it will be seen that any number of channel controllers can be so connected provided they do not exceed the number of channels which the control logic 1 22 can address.

Each of the channel controllers is given an unique address and the control logic 1 22 is arranged to produce each of the addresses in sequence so that one after another of the channel controllers is addressed in turn and information therefrom is conveyed via the interface unit 1 32 and serial sequence unit 1 20 to the modulator 11 6.

The serial sequence generator 120 is made up of three units (1) an identification pulse selector (2) a second identification pulse selector and (3) a data selector.

These three parts are illustrated in detail in Figs. 14, 1 5 and 1 6 respectively and these will now be described in more detail.

The identification pulse selector comprises a mono-stable device IC18 which is connected so as to be negative triggerable and nonretriggerable. The relaxation period is set by adjusting R31 to a multiple of the number of channels theoretically available and the basic identification pulse width which as previously mentioned is typically 100 psecs. Where two digits are used to denote the different channels up to 99 channels can be employed and in this case R31 is set to give a relaxation period of 9.9 milliseconds (i.e. 99 x 100 ,uses.) to ensure full capability of 1 to 99 without repeat.

A 10 kHz clock input derived from a divider in the oscillator and divider stage 11 8 serves as an input to clock A input of a dual 4-bit B.C.D. counter IC19.

The Q output of IC18 serves as the enable input to part A of the dual counter IC19 and also serves as the A reset and B reset inputs.

Consequently the counter IC19 is reset and enabled simultaneously by the appearance of an output at Q and the counter begins to count and produce a binary number on the lines BO through to B7.

A digital control of pulse width is provided by two 4-bit comparators IC20 and IC21 to which the outputs from the dual 4-bit counter are supplied as inputs.

Inputs to the comparators are provided from the address information from the control logic as will hereinafter be described and this is denoted by information on the 8 input lines denoted by AO through to A7.

Digital control of the pulse width gives an extremely accurate 2-digit B.C.D. channel setting in multiples of 100 lisecs. but the counter nevertheless continues the set marked space ratio. Thus for channel 5 denoted by appropriate information on the address inputs AO to A7, the output from the two comparators IC20 and IC21 connected as shown will constitute a pulse of duration 500 ysecs. at the beginning of the 9.9 millisecond period.

The mono-stable device IC18 therefore restricts clock pulse entry and resets the counter to give only one ident pulse out of the counter at junction 1 36 for each input trigger.

The transmitter of Fig. 1 3 is assumed to be incorporated in a system which employs two ident pulses such as 94 and 96 in Fig. 1 1a which are separated by a fixed period or dwell time. Fig. 1 5 illustrates the second identification pulse selector which forms the second stage of the serial sequence generator 1 20 in Fig. 13.

The selector comprises a first mono-stable integrated circuit IC22 the negative trigger input of which receives the first ident pulse from junction 1 36 of Fig. 14. The relaxation time of the mono-stable is set to the dwell time between the two ident pulses and is typically 50 ysecs.

The Q bar output of IC22 forms the positive trigger input for a second mono-stable device IC23 whose relaxation time is set to the same period as is IC18 which is for a 2-digit 0 to 99 channel system 9.9 milliseconds.

The Q output of IC23 serves as the enable input to a dual 4-bit B.C.D. counter IC24 and as with the counter IC19 the 1 0kHz clock signal is applied to the clock input of the A section of the dual counter.

The 0 output of IC23 also provides a reset signal for sections A and B of the counter and the Q4A output of the A part of the counter forms the enable signal for the B part of the counter.

The various Q outputs of the two counters constitute a binary coded decimal number on lines BO to B7 and these provide the inputs to two comparators IC25 and IC26 which are connected so as to operate in the same way as comparators IC20 and 1C21 described with reference to Fig. 14.

IC25 and IC26 are supplied with the same input signals AO to A7 as are IC20 and IC21 and the A = B output of IC26 provides the second identification pulse provided two suitable ident pulses separated by the appropriate dwell time have been received.

Fig. 1 6 illustrates the remaining part of the sequence generator 1 20 in Fig. 1 3 and comprises a data selector stage.

The ident signal from junction 1 38 of Fig.

1 5 provides the negative trigger input for a further mono-stable device IC27 which is adjusted to have a relaxation period of 12.75 milliseconds which will allow up to 255 jusec.

pulses spaced at 25 !Lsecs. intervals to be transmitted.

The Q output of IC27 serves as a control signal for the control logic stage 1 22 which will be described in more detail with reference to Fig. 1 8 and the trailing edge of the Q output provides the positive trigger for resetting the device IC27. The Q output also serves as the enable signal for the A section of a further dual bit binary counter IC28. The same signal also serves as a reset for both sections A and B of the counter so that when the counter is enabled it is simultaneously reset to 0.

The Q outputs of the two parts of the counter A and B provide inputs to a comparator formed from two devices IC29 and IC30 and the counter IC28 is clocked by a 20 kHz signal from the divider stage 11 8.

The A = B and A is less than B outputs from IC30 provide two inputs to an OR gate IC31 and the output of the OR gate together with the 20kHz clock signal provide the two inputs for an AND gate IC32 the output of which is supplied to the modulator 11 6 (see Fig. 13).

The inputs to the comparator formed by IC29 and 1C30 comprise the data from the 8bit data bus 1 30 (see Fig. 13) and the action of the circuit is to transmit via the AND gate IC32 a number of 20 kHz pulses during the data period which is determined by the particular number on the 8-bit data bus supplied to the comparator IC29/lC30.

The modulator 11 6 of Fig. 1 3 is shown in more detail in Fig. 17, the quiescent base current of which is controlled by the resistor chain R35, R36 and R37.

A 1 meg Hz carrier signal from the crystal oscillator 11 8 provides one input to an AND gate IC34 the other input of which is provided from an OR gate IC23 having three inputs one from terminal 1 36 from Fig. 14, one from terminal 1 38 of Fig. 1 5 and one from terminal 140 of Fig. 16. The action of the AND gate IC34 is to gate the 1 megHz carrier and to supply the carrier in bursts of duration equal to the ident pulses 1 and 2 and then as a series of 25 use data pulses during the data period defined by IC27, through capacitor C15 to the base of TR26.

The output of TR26 comprises a tuned circuit formed by the primary winding of transformer T1 and capacitor Cl 6 and the secondary of T1 is connected at one end to one of the conductive rails 10 and at the other end through capacitor C17 to the other conductive rail 1 2 of the track.

The control logic stage 1 22 of Fig. 1 3 is shown in detail in Fig. 1 8.

The function of the control logic is to provide the numbers corresponding to the addresses of the various channels as outputs AO to A3 and A10 to Al 3 on the address bus 128' and to receive via the status bus 1 34 the status signal from each receiver in turn as it receives its correct address.

The status bus signal on line 1 34 is gated in a NAND gate IC36 with the output from an inverting amplifier IC35 the input of which is normally low. Consequently as soon as a signal appears on the status bus 1 34 the NAND gate is satisfied and a signal is transmitted to the serial generator to indicate that the start of sequence is required. This is received by the negative trigger input of IC18 of Fig. 14 and initiates the generation of identity pulses depending on the particular number on the address bus at that instant.

The appearance of a signal on the status bus 1 34 also serves to trigger device IC37 and the Q bar output serves as the reset signal for IC38 the Q output of which constitutes the enabling signal for a dual 4-bit B.C.D. counter IC40. This signal is supplied to the enable input of IC40 via an OR gate IC39 the other input of which can receive a positive voltage from resistor R40 via S2.

A further switch S1 which is a push button switch removes the positive voltage delivered via R39 normally to the negative trigger of IC38 and the negative going voltage transition produced by the closing of switch S1 also serves as a reset signal for sections A and B of the dual counter IC40.

By depressing S1, S2 can be used to manually step through the counter sequence checking the serial sequence generation and observing the operation of a status lamp on each channel controller (to be described later) to check for correct addressing.

The transmission sequence is initiated by first of all depressing S1 with S2 in the position shown. This causes the counter IC40 to be reset and triggers a clock pulse enable signal from a mono-stable device IC38.

Counter IC40 begins to count from 0 having been reset and the outputs on lines AO to A3 and A10 to A13 constitute the channel address numbers which are supplied to the address bus 128.

As soon as a channel controller 108, 110 or 112 acknowledges receipt of signals corresponding to its programmed number which constitutes its address, the status bus changes state stopping the counter via lC37 and IC38.

As mentioned before an ident pulse width is automatically established as a result of the frozen numerical value in the output of counter IC40 since this is supplied to the first and second identification pulse selector circuits shown in Figs. 14 and 1 5 via the 8-bit address bus with the simultaneous transmission of the sequence start signal to the negative trigger input of IC18 (Fig. 14) thereby beginning the generation of the sequence of ident pulses 1 and 2 and data pulses as previously described with reference to Figs.

14, 15 and 16.

IC35 receives as an input signal the Q output from 1C27 of Fig. 1 6 and by virtue of the connection labelled 142 in Fig. 18 between the output of the inverting amplifier IC35 and the positive trigger input of monostable device IC38, a new enabling signal is provided for the counter IC40 as soon as the two ident pulses and the data pulses for any particular channel have been transmitted. This allows the counter IC40 to continue counting until the next change of state of the status bus 1 34 whereupon the procedure is repeated.

It will be seen therefore that each of the channel controllers connected to the bus lines will be addressed in sequence and in turn and the control logic will ignore numbers generated by the counter IC40 for which there is no channel controller connected to the bus lines.

The interface unit 1 32 is shown in Fig. 1 9.

The address bus which is made of two B.C.D. digits is fed through the interface unit to the channel controllers from the outputs of IC40 in the control logic stage 1 22. The interface unit therefore incorporates 8 buffer amplifiers (devices IC41 through to IC48) for decoupling the counter IC40 from the input circuits of the receivers.

The status bus may be a direct connection depending on the polarity of the signal required by the control logic circuit 122. However in the circuits shown the status signal delivered by the channel controllers is of incorrect phase and an inverting amplifier IC50 is provided in the interface unit.

Where the data can be delivered as a digital signal on the lines DO to D7 then the data transfer through the interface unit 1 32 can be direct and it is merely necessary to switch in pull-up resistors R43 through to R50 from the positive 1 5 volt rail to accommodate open collector outputs from the channel controllers 108 etc. (see later description).

However where it is more likely that at least some of the data information from a channel controller will be in analogue form (for example from a variable resistor indicating the speed required) an analogue to digital conversion stage is provided in the form of IC49 and this is conveniently located in the interface unit since only one analogue signal has to be converted to a digital signal at any instant in time and this saves duplication of analogue to digital converters on all the separate channel controllers.

The A to D converter IC49 receives the status bus signal which initiates conversion and the analogue signal from the channel controller which has been addressed correctly is made available to the analogue bus (not shown in Fig. 13) which is designated by reference numeral 146 in Fig. 19.

The digital output from the converter IC49 is provided on five lines into five OR gates IC51 through to IC55 connected in the DO to D4 data bus lines, the other inputs of the OR gates being connected to the DO to D4 lines.

In this way if data is available on all of the data bus lines DO to D7 in the form of digital information this is transmitted directly but in the event that analogue information is available and has to be converted this likewise will be converted and supplied onto the first five data bus lines DO to D4.

Having been converted entirely into digital information the data bus output from the interface unit can be described in binary terms and the eight lines are designated in Fig. 1 9 as 20 through to 27 respectively. It is this information which is supplied via the 8-bit data bus 1 30 to the data selector circuit of Fig. 1 6 as the inputs to the comparator formed by devices IC29 and IC30.

Fig. 20 shows one circuit suitable for the crystal oscillator and divider circuits. The oscillator stage is controlled by a transistor TR27 and a 1 meg Hz crystal Ol is connected to the base circuit via capacitor C21 and trimmer capacitor C20. The feedback path is provided from the upper end of resistor R53 to the junction of capacitors C22 and C23 also connected in the base circuit of the transistor TR27.

Output from the circuit is provided via C24 to the base of transistor TR28 which is connected as a Schmidt trigger circuit with TR29 the output of which constitutes a square wave having a frequency of 1 mHz.

This 1 mHz signal is available as the 1 mHz clock referred to elsewhere in the description and also serves as an input signal to a first divider stage IC56 connected as a divide by 5 network. The 200 kHz output signal is supplied as the input to a second divide by 5 stage IC58 the 40 kHz output signal from which serves as the input signal to a divide by 2 stage IC60. The 20 kHz square wave output from IC60 serves as an input signal to a further divider stage connected as a divide by 2 stage IC61 which provides the 10 kHz clock referred to in the description.

The devices IC56 and IC58 may be presettable decade counters having four P inputs onto which the binary signal 5 is loaded.

Counters count to 10 and at that stage give a pulse as a carry out which repeats therefore dividing the incoming clock by 5.

Fig. 21 illustrates the circuit of the power supply 11 4 which takes the alternating current mains at L and N and transforms this via transformers T2 and T3 into lower voltage centre tapped alternating current supplies from the secondaries of the two transformers.

Full wave rectifying circuits involving diodes D13 and D14 for transformer T2 and Dl 5 and D16 for transformer D3 feed smoothing and controlling circuits to provide 24 volts at up to 4 amps as the main direct current track supply for driving the locomotives and + 15, 0, - 1 5 volts for the operation of the transmitter unit.

The 24 volt direct current supply is short circuit protected so that the maximum current which can be drawn therefrom is limited to the design maximum i.e. 4 amps and at currents above that the voltage collapses to O thereby protecting the transformer and rectifying elements etc.

The receivers described with reference to Figs. 1 through to 1 2 have assumed that the receiver will always involve the controller of a locomotive. However one of the receivers may be used to control up to eight switched accessories in which event the outputs from the binary counter 20 of Fig. 1 allow each supply to switching circuits which can be changed from the state to the other depending on the outputs on the lines 20 through to 27 of counter 20.

A channel controller suitable for controlling the eight accessories which are then controlled by the switching circuits of the accessory receiver is illustrated in Fig. 22.

The controller includes thumb wheel digital switches S4 and S5 which can be set to give an electrical version of the two-digit number allocated to the channel and to the receiver and the digital signal set up by the switches S4 and S5 is compared in comparators IC65 and IC66 with the information on the address bus 128'.

When the comparators IC65 and IC66 indicate equivalence between the incoming address information and the thumb wheel digital switches S4 and S5 an output signal is provided via inverting amplifier IC67 which provides a status signal on the status bus 1 34 via buffer transistor TR32.

The signal is also provided as one of the inputs to eight separate gates IC68 to IC75.

When so enabled, the gates IC68 to IC75 allow information from the switches S6 through to S13 to be transferred via buffer transistors TR33 through to TR40 onto the data bus DO to D7 and it will be seen that the collectors of the transistors TR33 to TR40 in the buffer amplifiers are open and it is for this purpose that the interface unit of Fig. 1 9 includes the resistors R43 to R50.

The switches S6 to S13 can be used to control the eight accessories connected to the receiver and the appropriate accessory will be operated on or off by the operation of the appropriate switch out of S6 to S13.

Fig. 23 shows a channel controller which is adapted to be used as a control for a locomotive on a model railway.

The first part of the circuit is similar to the channel controller of Fig. 22 in that two thumb wheel switches S14 and S15 provide the channel address number and comparators IC76 and IC77 compare the channel address numbers from switches S14 and S15 with the address information from the address bus 128'.

As in Fig. 22, in inverting amplifier IC78 provides a status signal via buffer amplifier transistor TR42 onto line 1 34 when identity is achieved between the incoming address and the numerical value set up on the thumb wheel digital switches S14 and S15. Also an enabling signal is provided for the gates IC78 through to IC85 and input information to the gates can then be transferred via buffer amplifier transistors TR43 through to TR50 onto the data bus lines DO through to D7.

Since speed control is required to save analogue to digital conversion at each of the channel controllers for each of the locomotives, an analogue output corresponding to the setting of a variable resistor R86 across a constant voltage diode D17 is supplied via an F.E.T. transistor TR41 to the analogue bus 146 previously referred to with reference to Fig. 19.

Since the analogue bus will be converted into five lines of digital data which will appear on lines 20 through to 24 on the data bus the amplifiers TR43 through to TR47 of the channel controller of Fig. 23 are inhibited by strapping the data inputs of the gates IC78 through to IC82 to 0 volts. This means that no information will arrive at the gates IC51 through to IC55 other than from the data output of the analogue to digital converter IC49.

On the other hand the on/off, forward/reverse and accessory on/off switching is in a binary form from switches S16, S17 and S18 and this information (either a 0 voltage or a positive voltage depending on the setting of the switches) is transferred to the data inputs of the gates IC83 through to IC85 and from thence through the transistors TR48 through to TR50 and onto the D5 to D7 data bus lines.

Fig. 24 illustrates how a transmitter can be built up from a base unit 1 48 containing the circuits contained in the dotted outline 106 in Fig. 13, and a plurality of separate channel controllers of similar shape and configuration which can be plugged one to the other and to the base unit and which are denoted by reference numerals 150, 1 52 in the Fig. 24.

Two output terminals 1 54 are provided to receive power supply from a booster console should it be required and plugs and sockets such as 1 56 and 1 58 are provided between adjoining units to allow for interconnection.

The fascia layout of the channel controllers used to control locomotives may be as shown in Fig. 25a or 25b. Here the speed control is a slider 1 60 in the case of 25a or a rotary handle 1 62 in the case of 25b. Either is attached to the variable resistor contained within the speed control circuit and denoted by reference numeral R86 in Fig. 23.

Illuminated rocker switches 164, 1 66 and 1 68 control the operation of switches S16, S17 and S18 of Fig. 23 in the case of 25a and in Fig. 25b the switches are replaced by lever switches 170, 172, 1 74 respectively.

In both cases channel selection is obtained by thumb wheel switches 1 76 and a status lamp 1 80 is shown adjacent the thumb wheel switches 1 76 in each case.

Where a controller is to be allocated to one particular locomotive a description or name of the locomotives may be entered by entered in an appropriate plate 1 82 in either embodiment.

Figs. 26a and 26b illustrate two alternative channel controller fascias for controlling eight accessories.

In the case of 26a the switches S6 to S13 are controlled by illuminated push-button switches of which one is designated 1 84.

Tablets or plates such as designated by reference numeral 1 86 are provided adjacent each of the illuminated push-button switches 1 84 on which the description of the particular accessory to be controlled by that switch can be entered.

In the case of Fig. 26b switches S6 to S13 are controlled by lever switches one of which is denoted by reference numeral 1 88 and as before panels or plates such as 1 90 are mounted adjacent each of the lever switches 1 88 on which the details of the particular accessory to be controlled by that switch can be designated.

As with the channel controllers shown in Figs. 25a and 25b, thumb wheel channel selection switches 1 76 and status lamps 1 80 are provided along the upper edge of the fascia.

Claims (24)

1. A multiple channel control system for independently controlling a plurality of devices comprising: a transmitter unit which includes means for modulating the output voltage of a power supply for the devices so as to provide a constant frequency carrier waveform in the output voltage, means for controlling the modulator to interrupt the carrier and produce sequences of bursts of carrier according to predetermined codes or patterns, receiver means associated with each of the devices, each said receiver being adapted to receive and demodulate the carrier and decode the modulated carrier to produce an electrical signal having a value indicative of each code or pattern of bursts of carrier received by the receiver, means for comparing the said electrical signal with pre-programmed information to produce an identity signal when the said electrical signal corresponds to the pre-pro gramme information, further means within the receiver for producing a control signal to establish a channel of communication between the transmitter and the receiver upon the generation of an identity signal to allow the receiver to receive a subsequent transmission of electrical signal information relating to the operation of its associated device and means associated with the receiver and the device responsive to the said subsequent transmission to vary the operation of the device.

2. A multiple channel control system as claimed in claim 1 wherein the independently controllable devices are model railway locomotive and accessories of a model railway and the receivers are mounted in the locomotives and in or adjacent the acessories to be controlled, each of the receivers having different pre-programmed information so that any one of the receivers can be addressed independently of the others by transmitting an appropriate code or pattern of bursts of carrier.

3. A multiple channel control system as claimed in claim 2 in which the information relating to operation of a device (locomotive or accessory) is in the form of a further sequence of bursts of carrier each burst being of predetermined duration and separated from immediately adjoining bursts of carrier by predetermined time intervals, the number of such bursts determining the actual information which is conveyed to the receiver and each receiver further comprises decoding circuits for decoding the sequence of bursts of carrier in the said subsequent transmission to produce pulses therefrom, a counter for counting the pulses and further decoding means for decoding the final total in the counter accord ing to pre-programmed logic to provide an output signal for controlling the device.

4. A multiple channel control system as claimed in claim 3 in which the output signal controls the speed and direction of operation of an electric motor drive unit in a model railway locomotive.

5. A multiple channel control system as claimed in claim 4 wherein the output signal additionally controls the on/off operation of an accessory located on the locomotive or in rolling stock associated therewith.

6. A multiple channel control system as claimed in any of the preceding claims in which the bursts of carrier which are demodulated and decoded in the receiver are of accurately defined duration.

7. A multiple channel control system as claimed in claim 6 in which the duration of the burst of carrier is related to the number of carrier frequency pulses occurring during the burst.

8. A multiple channel control system as claimed in any one of the preceding claims in which two bursts of carrier are required each of specific duration and separated by a specific interval of time before an identity signal will be generated by a receiver having appropriate pre-programmed information.

9. A multiple channel control system as claimed in any one of the preceding claims wherein the modulation of the power supply output voltage is 100%.

10. A multiple channel control system as claimed in any one of the claims 1 to 8 wherein the modulation of the power supply output voltage is less than 100% typically 50%.

11. A multiple channel control system as claimed in claim 10 in which the power supply is a direct current power supply and each receiver includes means for detecting an interruption in the direct current component of the incoming signal to the receiver to reset the receiver to a quiescent condition in the event of an interruption of carrier thereto.

1 2. A multiple channel control system as claimed in claim 1 in which each information transmission is preceded by a burst of carrier of a unique duration and each receiver includes a decoding means for producing an identity signal after a burst of carrier of appropriate duration has been received.

1 3. A multiple channel control system as claimed in claim 1 2 in which each receiver includes a timing device which is reset by an identity pulse to define a period during which the receiver is sensitive to a subsequent transmission of electrical signal information.

1 4. A multiple channel control system as claimed in claim 1 3 further comprising a counter which is reset by an identity pulse and which counts pulses demodulated from an incoming subsequent transmission, the sum of the pulses constituting an output signal for determining the mode of operation of the device associated with the receiver.

1 5. A multiple channel control system as claimed in claim 1 4 further comprising pulse identifying circuit means responsive to the demodulated subsequent transmission to reject pulses which do not conform to a predetermined pulse width and thereby eliminate from the counter input spurious signals and noise signals.

1 6. A multiple channel control system as claimed in claim 6 or 7 wherein two bursts of carrier constitute the signal which must be received by a receiver to produce an identity signal, the two bursts of carrier being of predetermined duration and spaced apart by a given quiescent period or dwell time.

1 7. A multiple channel control system as claimed in claim 1 3 in which the counter which counts the pulses corresponding to the demodulation of the said subsequent transmission produces a binary coded output signal and one or more of the least significant bits of binary information remain unused so as to increase noise immunity of the system.

18. A multiple channel control system as claimed in claim 1 wherein a single transmitter is used to address a plurality of different receivers associated with the devices to be controlled, the transmitter including controls for setting up appropriate sequences of pulses from the transmitter so as to address one or other of the plurality of receivers and including further controls for producing an appropriate subsequent transmission containing an appropriate number of bursts of carrier which when decoded by the addressed receiver will produce an appropriate control signal for the device associated therewith.

19. A multiple channel control system as claimed in any one of the preceding claims wherein each receiver includes electrical latches which serve to hold the last control signal until such time as the receiver is readdressed so that a device associated with the receiver will continue to operate in accordance with the last transmitted instruction.

20. A multiple channel control system as claimed in claim 1 comprising a single transmitter having associated therewith a plurality of independent controllers each one incorporating a memory device and one controller being provided for each of the devices which are to be controlled by the system and each controller is addressed in turn in sequence in rapid succession and information stored in the controller memory corresponding to the mode of operation required of the device to which that controller relates is transmitted as a subsequent transmission by the transmitter following the sequence of carrier bursts identifying the receiver to which the information is to be sent.

21. A multiple channel control system as claimed in claim 20 wherein each of the separate controllers includes an on/off switch, a forward/reverse switch and a speed control for controlling a locomotive of a model railway.

22. A multiple channel control system as claimed in claim 21 wherein each channel controller incorporates an accessory switch for controlling an accessory associated with the locomotive to which the controller relates.

23. A multiple-channel controller as claimed in any of claims 20 to 22 in which each controller incorporates an indicator for indicating an on-off mode of operation and means is provided within the system to cause the indicator to be switched into an "on" mode when the controller is "on line" and to cause the indicator to be extinguished when the controller is no longer "on line".

24. Multiple channel control systems for controlling locomotives on a model railway constructed arranged and adapted to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.