GB2037117A - Digital scan converter - Google Patents

Digital scan converter Download PDF

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Publication number
GB2037117A
GB2037117A GB7938389A GB7938389A GB2037117A GB 2037117 A GB2037117 A GB 2037117A GB 7938389 A GB7938389 A GB 7938389A GB 7938389 A GB7938389 A GB 7938389A GB 2037117 A GB2037117 A GB 2037117A
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sep
tb
memory
data
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GB7938389A
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Baymar Inc
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Baymar Inc
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/523Details of pulse systems
    • G01S7/526Receivers
    • G01S7/53Means for transforming coordinates or for evaluating data, e.g. using computers
    • G01S7/531Scan converters
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28Details of pulse systems
    • G01S7/285Receivers
    • G01S7/295Means for transforming co-ordinates or for evaluating data, e.g. using computers
    • G01S7/298Scan converters
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/56Display arrangements
    • G01S7/62Cathode-ray tube displays or other two-dimensional or three-dimensional displays
    • G01S7/6218Cathode-ray tube displays or other two-dimensional or three-dimensional displays providing two-dimensional coordinated display of distance and direction
    • G01S7/6227Plan-position indicators, i.e. P.P.I.

Abstract

In a digital scan converter a PPI radar or sonar scan is processed to generate a standard television video raster scan format compatible with standard television receivers and recorders by storing the data from a radar or sonar transponder 7 in a scratch pad memory 9, performing a coordinate conversion in a microprocessor 19 using angle data from measuring means 11 and storing the converted data in a refresh memory 13 for supply to a display 17. Signal to noise ratio is improved by correlation of successive PPI scans. <IMAGE>

Description

SPECIFICATION Target display system and method This invention is concerned with a target display system and method.

A radar scanner unit is typically mounted high on a mast to allow unobstructed rotation of the antenna on top. This unit is commonly connected via one or more cable to a control and display console which contains the manual controls and CRT display and power source. The scanner unit serves to rotate the antenna and generate the radar pulses. In addition, it also contains a resolver which sends information to the display console concerning direction of the scan. The display console contains circuitry to read the angle from the resolver and drive the CRT display.

It also contains controls to adjust the range markers, partial sweep limits, and the like.

A sonar scanner unit of conventional design is typically mounted below the water line at a location on the bottom, outboard portion of a ship from which unobstucted sonar scans may be made. This sonar scanner unit operates to send out a wave of acoustic energy in response to electrical pulsing of a piezoelectric transducer. The acoustic energy emanating from the face of the transducer propagates through water in a selected direction and then returns as an echo reflection from a remote reflective object. The transducer, then converted to operation as an echo receiver, receives the echo reflection and converts the acoustic energy thereof to an electrical echo signal for subsequent processing in a control module. By altering the direction of propagation progressively, such conventional systems can provide a sonar scan of the surrounding water.

In accordance with the present invention, a radar-scanning unit or a sonar-scanning unit may be mounted as previously described and a display module may be connected by interconnecting cables to the scanner unit and its control module. The control module generates a video signal that can be carried by a single coaxial cable to video monitors located throughout the vessel.

Alternatively, the control module may be incorporated into, or closely associated with, the scanner unit so that only a standard video cable and remote control conductors need be connected to the scanner unit and control module at its remote mounting.

The control module according to the present invention is capable of processing radar or sonar signals to overcome the effects of sea scatter and anomalous targets which often obscure an object due to reflections therefrom. These reflections cause the entire CRT display to appear illuminated with the result that any small real objects, such as boats etc., in the range of the radar, or such as bottom protrusions, wrecks, and the like, will be obscured. In one embodiment, the received radar reflections or sonar reflections from two or more successive scans are compared. Only reflections which occur substantially identically in the successive scans will be retained and processed for video display. Reflections in successive scans which do not repeat identically will be discarded.

In addition, the control module of the present invention may also include an alarm that can be sounded, audibly or visually, when an object is detected within a certain range from the scanning unit. This may be done through selective signal processing to initiate alarm only for objects, for example, that lie in a collision course or at less than a selected depth and using various color displays, for example, for different types of objects which may or may not present a hazard. In addition, precision variable range markers (PVRM) are provided which enable easy determination of distances to be made from the display. The range markers include one or more circle displays at known variable radii which may be aligned with a particular object to produce a corresponding digital read-out of the distance to the object.

Television or video signals thus provided according to the present invention may be broadcast under local or regional control for reception on standard television receivers aboard vessels operating in the region to provide an indication of the objects about the region. This also facilitates the use of standard video recorders to produce video records of events involving collision, or other dispute situations where a radar record would be useful for determining the party at fault.

Figure 1 is a simplified block schematic diagram of the radar or sonar television apparatus of the present invention; Figure 2 is a detailed schematic diagram of the scratch pad memory of the apparatus of Fig.

1; Figure 3 is a schematic diagram of one embodiment of the angle-measuring and coordinate conversion apparatus of Fig. 1; Figure 4 is a schematic diagram of one embodiment of the refresh memory and controls therefor in the apparatus of Fig. 1; Figure 5 is a schematic diagram of one em'-lac' ent of the control and video generators for the apparatus of Fig. 1; and Figures 6 and 7 are flow charts showing the operations of the present invention.

In the present invention, three pieces of information are used to produce a video display. One is a radar or sonar signal indicative of received reflections, another is a signal indicative of the start of radar-pulse transmission or sonar-pulse transmission, and third is a signal representative of the scan angle of the radar antenna or sonar transducer. The reflected signal can be obtained either before or after range rings or precision variable range markers are added to the scan signal, depending upon whether the range rings are wanted to appear on the television display.

The start of the radar-pulse or the sonar-pulse transmission and the angle information which determine the movement of an electron beam on a conventional display CRT are resolved into X-Y direction vectors which are then converted to rectangular coordinates to control the addressing of a refresh memory address that stores the reflection information over a given scan.

Fig. 1 shows the simplified block schematic diagram of the present invention for operation with a radar transponder 7, or sonar transducer 7a, including the scratch pad memory 9, angle measurement 11 with rectangular-coordinate conversion means, refresh memory 1 3 including video generator 15, a CRT television display 17, a microprocessor 19, and the front-panel controls 21.

The radar transponder 7 operates conventionally by emitting a high frequency, high energy pulse that is radiated electromagnetically in a particular direction. A sonar transducer 7a also operates conventionally by emitting a high energy, acoustic pulse that radiates in a particular direction. When the radiated energy strikes discontinuities in the path of propagation, echoes are generated and returned back to the radar transponder or sonar transducer, now operating as a receiver. The distance to the object encountered from the radar transponder or sonar transducer is directly proportional to the time delay between the emitted pulse and the received echo propagating in air (for radar) or water (for sonar). When the echo is received at the transponder or sonar transducer, it is converted into an electronic echo video signal.In accordance with the present invention, one hundred twenty-eight (128) discrete points along the echo video signal are quantized and stored in the scratch pad memory 9, regardless of the range at which the radar or sonar is set. Echo signals which are above a predetermined amplitude are recorded as ones (1's) and the echo signals below the threshold amplitude are recorded as zeroes (O's) in the scratch pad memory 9. This quantization and recordation in the scratch pad memory 9 must be done at high speed in order to record the echo signal in real time. For example, with a radar range of one mile, in order to record 128 discrete points along the onemile range, the memory 9 must operate at 10 MHz. Similarly, with a sonar range of 100 meters, in order to record 128 discrete points along the 100-meter range the memory need only operate at low, sonic frequencies.The scratch pad memory 9 may be equipped with an autonomous control system in order to achieve the required operating speeds, indpendently of control by the microprocessor 1 9 which would be too slow for recording a radar scan in real time (except for very long ranges). Of course, sonar scans can be operated much slower due to the propagation velocity of sound in water (1500 meters/sec.). In either case, -A high-energy pulse is emitted. As it propagates away from the transponder of transducer, echoes are returned from objects in the propagation path.

-The echoes are converted to electronic video signals.

-The amplitudes of video signals above a predetermined threshold are recorded as ones (1 's) in the scratch pad memory 9, and the amplitudes of such signals below that threshold are recorded as zeroes (O's).

Numerous such pulses and sequences occur as the radar antenna or sonar transducer completes a scan through a given sweep angle. Since the radar antenna or sonar transducer rotates slowly, the scans are repeated over and over until the complete sweep angle (360 , or less), surrounding the transponder or transducer is scanned, and then are repeated all over again in the next sweep angle.

Operation of the scratch pad memory 9 (when sea scatter elimination for radar is utilized or echo-inhibit for sonar is utilized) begins with the first scan, as described later herein. Instead of using the data recorded in one section of scratch pad memory 9 immediately, it is saved until one or more subsequent scans are taken through the sweep angle. The quantized echo signal information in one scan is stored as a succession of ones and zeroes in a section of scratch pad memory, and the quantized echo signal information in a subsequent scan is AND-logically compared with the stored information from the first scan. Only ones (1 's) occurring in identical address locations (i.e., antenna or transducer angle) are considered as correlated data (1 's) and are processed as a real object. All other combinations of data in corresponding address locations are considered as noncorrelated data (e.g., waves, fish, etc.) or as non-reflecting objects and are processed as zeroes. The resulting data from such a comparison is stored in another section(s) of the scratch pad memory. More than one successive scan for sea-scatter or echo-inhibit processing can be selected from the control panel 21. In each such scan, the quantized echo signals stored in successive address locations of the scratch pad memory 9 are AND-logically compared for parity with quantized echo signals received at each corresponding address location, as described above. Thus, in any successive scan in which an object does not persist, a zero is processed as indicative of no object at that location.

Subsequently, the contents of the scratch pad memory 9 that are indicative of echo signals at each point are transferred to the refresh. memory 1 3 in form that is converted from the polar coordinates of the echo signals to rectangular coordinates. Thus, each one (1) stored in the scratch pad memory 9 will be processed to appear as a bright spot on the television CRT display, and each zero (0) thus stored will be processed to appear as a dark spot, as later described in detail.

In order for the information to be processed from the scratch pad memory 9, the angle at which the radar antenna or sonar transducer was set while the pulse was transmitted and echo pulses received must be known. The angle-measuring means 11 also contains its own control system in order to function rapidly. Thus, an angle resolver coupled to a radar antenna or a sonar transducer can typically generate a three-vector direction signal. The angle-measuring means 11, as shown in Fig. 3, converts these vector signals into sine and cosine functions of the angle. The sine and cosine functions may then be applied to a sample and hold circuit for further processing to convert each point in the scratch pad memory to rectangular coordinates.

Of course, where a radar-antenna or sonar transducer angle resolver generates the sine and cosine functions directly, it is not necessary to perform the aforementioned conversion. However obtained, the sine and cosine functions of the antenna or transducer angle are stored in separate sample and hold circuits of the means 11. A conventional hardward adder may be provided in means 11 in order to calculate both the X and Y coordinate of each of the 1 28 points in the scratch pad memory 9 at the high speeds required to transfer the information to the refresh memory. These conversions and transfers may be done under control in a conventional manner by the microprocessor 1 9.

The refresh memory 1 3 stores the data thus converted for one complete sweep angle of the surroundings which the radar or sonar is scanning. The refresh memory 1 3 is then essentially a map of the entire area with each bit corresponding to an exact location of a reflective object with X-Y coordinates. The addresses in refresh memory 1 3 can then be accessed sequentially with the proper timing to display on a standard television raster-type video monitor. The refresh memory 1 3 is actually accessed at twice the frequency required for fetching the data for the video display.The memory addresses are alternately read and written so that each "read" fetches data for the television monitor display and each "write" may be used to load new data into the refresh memory 1 3. In this way, a steady television display is achieved, even when new updating data is being loaded into the refresh memory 1 3 for subsequent display. The refresh memory 13 is configured into 4K by 16-bits to make up a total capacity of 65K bits which correspond with 65K discrete points on the television CRT 1 7. The refresh memory module 1 3 includes the requisite timing and control for refreshing dynamic memory cells as well as a video output shift register for developing the television video signal.This module 1 3 is coupled to a video generator 1 5 for generating composite video output including horizonal and vertical synchronizing signals and the television video signal. The module 1 3 also contains an address multiplexer which allows read and write addresses to be multiplexed into the refresh memory.

Read addresses are supplied to select sequential read-location addresses in order to maintain the video display and make it appear as a steady display. The write addresses are supplied when data is to be updated in the refresh memory. An optional RF generator 1 6 may be used to convert the composite video just described into an RF signal in a conventional manner for transmission and reception by a television CRT monitor without fixed wiring at all.

The television CRT unit 1 7 may be a standard video display monitor or television set that can accept composite video or RF signal and display it in standard television raster-scan format. The refresh rate is sufficiently rapid to make the picture appear steady to the viewer with sufficient intensity and contrast to be daylight viewable.

The microprocessor 1 9 (e.g., MOS Technology Model 6502) acts as a controller for each of the modules to assure proper operation. As described herein, the scratch pad memory 9 may be first configured for sea-scatter repeat or echo-inhibit repeat operation one or more scan cycles under control of the microprocessor 1 9 which enables the memory 9 at the proper times to record the subsequent echo information. The microprocessor 1 9 then disables the writing of data into memory and controls the processing of the data, as described above, until the memory 9 is again enabled by the microprocessor for the next scan.The microprocessor 1 9 thus coordinates the transfer of data from the scratch pad memory 9 to the refresh memory 13, and in doing so controls the conversion of the polar coordinates of each point of data in the scratch pad memory 9 to rectangular coordinates before transferring to the refresh memory 1 3. The microprocessor 1 9 initiates the point-by-point conversion from polar coordinates to rectangular coordinates sequentially for each bit in the scratch pad memory 9, which conversion and data transfer from scratch pad to refresh then proceeds autonomously until all 1 28 data bits have been transferred.

The control module may include a range selector switch which selects the range that is viewed on the CRT 1 7 as a series of fixed markers representative of ranges from a minimum of one mile through successive doublings to a range of, say, sixty-four miles for radar, or for a minimum of 100 meters through successive doublings to a range of, say, 1 600 meters for sonar. One or more variable range rings may also be provided via controls in unit 21 to find the distance to an object by determining the distance out to some point on the display. Digital readout of the distance to the point thus determined may be provided in the corner of the CRT as part of the display.A control for an alarm may also be provided to signal that an object is detected within a certain predetermined set radius from the transponder or transducer. The alarm simply samples the data from the scratch pad memory 9 as it is transferred to the refresh memory 1 3. Any ones (1 's) encountered within the selected radius (i.e., set of coordinates) will produce the alarm signal.

Referring now to Fig. 2, there is shown a more detailed schematic diagram of the scratch pad memory 9 of Fig. 1. As described with respect to Fig. 1, the scratch pad memory 9 is capable of autonomously making a recording of a single scan or sweep. The memory 9 is then disabled from scanning by the microprocessor 1 9 until the data from the scratch pad memory 9 is converted and unloaded into the refresh memory 1 3. The integrated circuits 24 and 25 are both 256 x 1 random access memories (e.g., type AM27LS0O) that operate for one mile range at 10 MHz in a radar embodiment of the present invention. The operating frequency is divided down successively for each range of 2, 4, 8, 16, 32 and 64 miles in a radar configuration.Thus, by slowing down the sequencing of the scratch pad memory 9, samples of returning echoes are taken less frequently and, since the velocity of the electromagnetic waves for radar (or the acoustic waves for sonar) is essentially constant, it can be seen that the slower sampling results in echo data over greater distances being recorded in the scratch pad 9. Conversely, by increasing the sequencing speed of the scratch pad memory 9, a shorter range of received echoes is recorded.

Echo signals at input 27 are applied directly to a comparator 29 for threshold detection against a signal level that is set by adjusting the potentiometer 31 connected to the other terminal of comparator 29. Thus, received echo signals which are above the threshold level are considered signals from significant objects and will be so processed, while received echo signals that are smaller than the threshold level are considered noise and will not be entered into the scratch pad 9. Thus, every time a received echo signal at input 27 exceeds the threshold set on the potentiometer 31, the signal is considered as a logic "1" level that appears at the output 33 of the comparator 29. This signal is then applied to one input of an AND gate 35.If seascatter elimination in radar (or the echo-inhibit in sonar) is not used, the other input of AND gate 35 be held high, and the digitized signal will therefore pass through the AND gate 35 and the NOR gate 37 to appear inverted at the output thereof. This signal is applied to the set input of flip-flop which thus remains set until the next "write" is executed in the scratch pad memory 9.

Thus, a signal appearing anywhere between successive addresses of the scratch pad memory 9 is stored in flip-flop 39 until it is written into the corresponding address of the memory itself.

After it is written into the memory, a clock pulse appears at input 41 to clear the flip-flop and wait for the next input 27.

The output from the flip-flop 39 is applied directly to the inverted data inputs of the memories 24 and 25 which are identical so that either one can be used when sea-scatter elimination (or echo-inhibit) is not utilized. When sea-scatter elimination (or echo-inhibit) is utilized, one scan must be taken and recorded in one of the memories, say, 24. Then a second scan is taken, but instead of writing directly into memory 24, the scan results are logically ANDed in circuit 44 with the result stored in memory 24 from the previous scan. Thus, only when a logic "1" from the previous scan corresponds with the logic "1" from the present scan, as applied to inputs 33 and 43 of gate 35, will a signal be recorded in memory 25.Thus, for sea-scatter elimination (or echo-inhibit) enabled by signal at input 45, the memory 25 will contain the correlated or "AND" logically combined data from the two successive scans. Thus, echoes from waves, fish, etc., or any temporary reflector received in one scan but not in a second scan are eliminated from the displayed picture. Of course, third, fourth, etc., sea-scatter eliminating scans (or echoinhibited scans) can be taken using the same process and then comparing the data bits in memory 25 with data bits from the next scan and storing the results in another memory, or even back in memory 24, as shown. Stored information with sea-scatter elimination (or echoinhibiting) is merely logically "AND"ed with the control signal to supply the composite to the next memory.If the control signal is in the READ position, then the data output 48 is essentially applied directly to an input of gate 35. The memory which is in the WRITE position (i.e., either memory 24 or 25) does not get "AND" logically combined with new scan data bits but rather is used to store the following results.

When loading of the scratch pad is completed in this manner, the information from the last scan is loaded into the last memory being used for loading, either memory 24 or 25, depending on how many scans were done. The data is then ready to be removed from the scratch pad and read into the refresh memory 1 3 for controlling the television CRT display. This is accomplished by applying control signals to terminals 45, 51, 53, 55, 57, 59 and 61 for reading the data out and for all operations of the scratch pad memory. The memory READ/WRITE control signals are applied to terminals 61 and 63. When either of these signals is low, the respective memory 24 or 25 is in the READ mode. If either of these signals is high, the respective memory 24 or 25 is in the WRITE mode.Thus, by placing one of the signals at 61 and 63 in READ mode and the other in the WRITE mode, the data output from the desired memory is applied through the logic gates 44 to output terminals 48, as previously described, for connection to the data inputs of refresh memory 1 3.

The scratch pad memories 24 and 25 are controlled by binary counters 65 and 67 which are four-bit binary counters, used as address selectors for the memories. Since these memories are 356-bits, an 8-bit address would be required to access the entire memory. However, by using only 1 28 points on each scan regardless of the range, only 1 28 memory bits are required for each memory, and this requires only a 7-bit address. The eighth bit is used as an interrupt signal when the scan is completed. The seven outputs from the cascaded binary counters 65 and 67 are connected to the address inputs of the memories 24 and 25. The eighth address bit from counters 67, when it goes high, indicates 1 28 counts have been taken and is used as an end signal to indicate the end of a scan or the end of a data unloading operation.The addresses of the refresh memories 1 3 are always sequenced in order from zero to 127. When a scan is going to be recorded, the address registers 65 and 67 are reset to the zero state and counted up sequentially using the clock input to count up to 1 27. At count 128, counter 67 output 69 goes high to signal the end of the scan operation. This output 69 is also inverted and is connected to the counter enable terminal 71 which stops the clocking when count 1 28 is reached. The same procedure is followed to read data from the memories 24 or 25 to store it in the refresh memory 1 3. The counters 65 and 67 are first cleared by a signal from the microprocessor 19 applied to input terminal 59.The single-step input 55 is connected to the same clock as the refresh memory 1 3 and the read and write cycles of the scratch pad memory 24, 25 and refresh memory 1 3 are synchronized such that when a data bit is available coming out of the scratch pad memory 24 or 25, the refresh memory 1 3 is ready to read and store it so that the process of transferring 1 28 bits from scratch pad memory 24 or 25 to refresh memory 1 3 can proceed continuously. At the end of this 128count sequence, output 67 goes high to signal the end of the operation.

The beginning of each scan is initiated by a start or synchronizing pulse from the radar (or sonar) which is applied at terminal 73. The positive edge of this sync pulse coincides with the emitting of the radar (or sonar) pulse at the start of the scan. This is considered time t,, and from this time on, the received signals represent echoes returning from objects at greater and greater distances. The sync pulse at input 73 is applied to the input of a one-shot circuit 75 which triggers the positive edge, and subsequently, produces a very narrow pulse 77 starting at the positive edge of the sync pulse. This pulse 77 is applied to gate logic 79 to reset the address counters 65 and 67.If the scan enable input 57 from the microprocessor 1 9 is in the enabled position, then the sync pulse 77 is applied at the reset terminal of counters 65 and 67 to reset the counters to their zero states. The counters thus immediately begin counting upward on the clock signal which is derived from gating logic 81 and the signal applied to terminal 83 from the crystal-controlled oscillator 82 (10 MHz for radar, or a low frequency of, say, 1000 hertz for sonar). This oscillator signal is applied to a divide-by-N counter 85 which serves as a range selector and which, for radar, divides by 2, 4, 8, 16, 32 or 64, depending on the setting of the range selector. Similarly, for sonar, the oscillator may be divided down successively to provide the desired ranges.The divided oscillator signal sequences the address counters 65, 67 at the proper speed, loading the memory at precise time intervals necessary for the required range. Write-pulses to the memory are also produced by gating this clock with the input readwrite selector inputs 61 and 63 using two NAND gates 87. The precision variable range marker (PVRM) 89 is also connected to receive the sync pulse at input 73. The PVRM 89 is essentially a one-shot multivibrator which produces a pulse that is delayed by a variable time from the start of scan indicated by the sync pulse. The output is a high level ''1'' logic signal and is indirectly applied to the memories through gating 37 and 39. This is used to provide a variable diameter range ring on the display.The time delay in the PVRM corresponds to a given radius of range ring, which radius may be read-out digitally on the CRT 1 7 so that the exact distance to target as viewed on the display can be determined by adjusting the variable range rings.

The sea-scatter (or echo inhibit) input 45 is used to disable sea scatter (or echo inhibit) at least for the first scan, where there is no previous history or previous scan and thus nothing to compare the first scan with. Thus, the first scan must be read directly into the memory 24 or 25 with the input at 45 disabled under control from the microprocessor 1 9. Thereafter, sea scatter (or echo-inhibit) may be enabled during any number of subsequent scans when desired. The clear input 59 is controlled from the microprocessor 1 9 and is used to initialize the memory address counters 65 and 67 to zero sor beginninsr either a read-scan cycle or the cycle of data transfer to the refresh display memory 13.

In one embodiment of the present invention, an anaiug-to-digital (A/D) converter receives an analog input proportional to the cosine of the angle of scanning, that is, the direction the radar antenna or sonar transducer is pointing relative to straight ahead at any moment in a scan. The A/D converter continuously tracks the analog value of the cosine of the angle and supplies a digital value representative of the cosine of the angle. Each radius is broken up into 1 28 discrete points of range, and a logic 1 or 0 may be recorded for each of the 1 28 points. The first discrete point at 1/128 of the radius out from the center is at some particular scan angle.

The cosine of that angle times a proper scale factor will give the X orthogonal component of the distance that the first point is out from the center of the circle. Since the distance (say, X1) between the first point and the second point is the same as the distance between the first point and the center of the circle for 1 28 equal increments of range, then the X component of the distance between the first point and the second point is the same as the X component of the distance between the first point and the center of the circle. Thus, to determine the X coordinate of the second point, it is merely necessary to add X1 plus X, since there are two equal X, components making up the X coordinate of the second point.Similarly, the X coordinate of the third point is X1 plus X1 plus X1 away from the center, and the fiftieth point X coordinate will be X1 added 50 times. This repetitive addition is performed very quickly for calculating the X coordinate of each point as it is transferred from the scratch pad memory 24 or 25 to the refresh memory 1 3. Similarly, for computing the Y coordinate, the sine of the angle of scanning is fed to a separate similar A/D converter and adder (not shown). These two calculations of X coordinate and Y coordinate proceed simultaneously using separate, similar circuits. For simplicity, therefore, only the X component calculating circuitry is shown on the schematic.

Referring now to Fig. 3, there is shown an integrated circuit switch module 91 which receives the sine and cosine of the scan angle at inputs 93 and 95. The values of the sine and cosine of the scan angle at the moment the switches are opened are retained at the output of the switches by the capacitors 97 and 99 which act as sample-and-hold circuits for the tracking digital-toanalog converter that follows. The cosine of the angle is applied directly to the X tracking A/D converter and the sine of the angle is shown at point A, which goes to a similar tracking A/D converter (not shown) for Y component. -The switches in integrated circuit 91 are controlled by inputs 96 which are connected to one-shot circuit 98 that is fired from the synch signal previously described and that remains on for a predetermined time depending on the range selector switch.The on time is an optimum time for reading the cosine or the sine of the scan angle. The one-shot circuit 98 then goes off at the end of that time and opens the switches 91 to complete a sample and hold cycle.

The tracking A/D converter for X components comprises integrated circuits 101-107 and associated circuits which are enabled by an input at line 1 09. Thus, as soon as the switches 91 are opened by one-shot circuit 98, the same control signal enables the tracking A/D converter which operates as follows: Integrated circuit 105 is a digital-to-analog converter for digital inputs applied to its terminals 1 2 through 5 which produces a proportional analog output current at output 11 3 that is converted to voltage level by the first stage integrated circuit amplifier 107. The integrated circuits 101 and 103 are up-down counters that are driven by an external clock input and the outputs of the counters are connected to the inputs of the digital-toanalog converter 105.The value to be measured is applied to one terminal of the comparator stage 107 and the analog value generated by the digital-to-analog converter is connected to the other input of the comparator. If the value of the cosine of the scan angle to be measured is larger than the analog value generated by the converter 105, then the comparator output 110 will be high, causing the counters 101 and 103 to count up until a balance of the voltages at the inputs of the comparator stage 107 is established. At that point, a digital equivalent value to the analog voltage of the cosine of the scan angle is available at the output of counters 101 and 103. To prevent the tracking A/D converter from searching outside its possible range, gating of the clock is provided by circuits 11 5 and 11 7.If the analog value of the cosine of the scan angle is higher than the converter 105 can reach (i.e., is beyond the maximum digital value of all ones), then the gating 115, 11 7 disables the clock and the tracking A to D value will remain all ones until the value of the cosine is reduced. Similarly, the gating 115, 11 7 prevents the tracking A/D converter from searching below the digital input value of all zeroes. The gate 11 7 also serves as a clock disable to stop the tracking A/D converter during the time the digital value is being utilized by the adder.

The digital value of the cosine of the scan angle is subsequently applied to the input terminals of the four-bit, full binary adders 119, 121. The integrated circuits 123 and 122 serve as accumulator registers for the adder. Note that the X coordinate can range from zero to plus or minus 128, and that each value of X is one unit (e.g., zero to one, one to two, two to three).

Note also that the seven-bit input to the adder is a fraction of a unit which can range from zero to one full unit. The fractions are thus repetitively added until one unit is exceeded. At this time a carry is generated at output 1 24. One unit having been exceeded means that the X coordinate should be incremented from its previous position to the next higher positive or negative value.

Adder operation is initiated by setting counters 1 25 and 1 27 to a value of 128, representing the center value on the television CRT display. Then, depending upon whether the cosine of the angle is positive or negative, the value will be incremented or decremented repetitively until the coordinates of all 1 28 points on the display have been calculated and transferred to the refresh memory 13. The positive or negative information is generated from the highest order bit within the tracking A/D converter and is connected via line 1 29 directly to the up-down control inputs of counters 125 and 127. Of course, similar circuitry (not shown) is provided for calculating the Y components, as previously discussed.In operation, then, the radar 7 (or sonar 7a) emits a pulse at some particular scan angle. The reflections are stored in the scratch pad memory 9 and the cosine of the angle and the sine of the angle are stored in the sample and hold circuits 91, 97, 99. The tracking A/D converter generates a digital value for the cosine of the angle. The digital value of the cosine is applied to the input of the adder 119, 121, and the X coordinates for the first 1 28 points in the scan are calculated. The exact digital value for the X coordinate is applied to the adder. This value is added to the value in the accumulators 122, 1 23 which are initially zero and the sum is stored in the accumulators.If no carry is generated (meaning the value is less than 1), then the address counters 125, 127 remain at the initialized value (i.e., 128) for starting at the center of the display. After the first point has been completed and X coordinate values has been calculated, the second point is calculated in identical manner and so on. The input to the adder is added to the values in the accumulators and if the carry is generated, the outputs of the address counters 125, 1 27 are incremented or decremented, depending on whether the cosine of the angle is positive or negative. This repetitive accumulative add continues until X coordinates for all 1 28 bits to be displayed for the single scan in one angular direction have been completed.Of course, simultaneously with the time that the X coordinates are being calculated from the cosine of the angle, the Y coordinates are also being calculated from the sine of the angle. This generates complete X and Y addresses for the refresh memory 13, and the particular point in the scratch pad memory 9 is then written into that address in the refresh memory 1 3. That address is subsequently displayed as the spot on the television CRT display 17. The data from the next scan which is to be read and converted to rectangular coordinates is controlled by the microprocessor 1 9 via scan enable signal at terminal 131.Also, signal at input terminal 133 initializes the adder and loads the initial X address (i.e., the center of the displacement) into counters 1 25 and 1 27. Similarly, signal at terminal 10 performs the same function on the Y adder (not shown). The address counters 1 25 and 1 27 are initialized using signals entered through terminals 1 35.

Numerical values such as for range, etc., may be displayed on the television CRT 1 7. This is accomplished under control of microprocessor 1 9 which has direct access to the refresh memory 1 3 for loading the proper data to represent the range value in numbers. Signals on terminals 1 33 and 1 35 are used to load the X address in the refresh memory and, of course, the same operation may be performed in the Y address (not shown) in the refresh memory. Thus, for range values or PVRM values to be displayed on the CRT along with the radar picture, the microprocessor 1 9 generates the proper dot pattern and then computes the X, Y addresses for locating the legend on the CRT.Also, a range ring appearing on the CRT has a known radius which is displayed numerically in the center of the screen.

The transfer of data from scratch pad memory 9 to refresh memory 1 3 in converted form is also controlled by the micrprocessor 1 9 which interfaces with ROM 20 programs which it executes and RAM 22 which provides temporary storage registers for the programs. The ROM 20 holds the programs, listed in Appendix A hereof, including the basic operating programs and the programs for such features as generating display characters as dot matrices on the CRT range or PVRM, or the like. The basic operation of the microprocessor includes initialization at power out/up, initializing the peripheral interface adapters, doing a first scratch pad load from video data without sea scatter (or echo inhibit) checking for the number of scan repeats, if any, required by the front panel control settings.The microprocessor 1 9 then controls the transfer of data from the scratch pad memory 9, which contains data from one scan, over to the refresh memory. It also checks for alarm conditions to sound an alarm if an alarm condition exists, and then repeats the procedure.

The refresh memory 1 3 of Fig. 1 stores 65,000 bits of video information for a full 360 display with one level of contrast, namely, a picture element is either on or off in the display.

The other feature of the refresh memory is that it facilitates aenerating the picture in television raster scan format, rather than in a form such as polar display (as in conventional radar CRT displays). In the raster scan format, the scanned beam traces a raster of about 256 or 512 horizontal lines, depending on how one wants to use them. The information on each line is a function of the video information and may be, for example, 256 dots long per line to form a matrix display of up to 256 x 256 spots. Since the raster scan is locally generated and controlled at each monitor, the only information that need be transported along with the video information is sync information conventionally used to correlate the displayed scan lines with the incoming video information.

Referring now to the schematic diagrams of Figures 4 and 5, there are shown sixteen dynamic random access memories (RAM) 151 connected in parallel and labeled RAM 1, RAM 2, etc., to RAM 1 6. The configuration of each RAM is 4K-by-one bit. They are connected to provide a memory system having an array of 4K-by-i 6 bits wide for a total of 65,000 bits.

These memory units operate through successive, timed read cycles and write cycles where the read cycle is used to refresh the CRT regularly and the write cycle is used when data from the scratch pad memory 9 is to be loaded into the refresh memory 1 3. Thus, the two cycles repeat at high frequency and a read cycle is executed each time data is to be sent to the CRT. The write cycles, however, are only utilized when there is data in the scratch pad memory 9 which must be transferred over to the refresh memory 13. Operation of the refresh memories 151 is determined by the timing and control functions including Write Enable, Chip Select, and the like. These signals are generated by decoding the four-bit binary counter 1 52 into sixteen steps.

The first eight of the sixteen steps establish the timing for a write cycle and the second eight steps establish the timing for a read cycle. The steps are decoded by circuits 160a, 160b, 160c, 1 60d and 1 68 to produce the required signals. The refresh memory RAM's 1 51 also must be addressed properly for the read cycle and write cycle. This is accomplished for the read cycle using six-bit counters in circuits 1 54 and 1 56 which together spake up a twelve-bit counter. Under external control, these counters are advanced by an applied clock signal derived from circuit 1 70 and the clock oscillator, later described.Thus, each read cycle accesses sequential addresses in the memory 151 by incrementing the six-bit internal counters in circuits 1 54 and 1 56 and by multiplexing the count outputs onto the address bus for the refresh memory circuit 170. The write addresses are also supplied to the refresh memory 151 via the counters 154, 1 56 which are capable of multiplexing with externally-supplied addresses from the microprocessor. Thus, every second memory cycle can be used as a write cycle, when required, and every read cycle can run uninterruptedly to access data for the display.

The data read out of the refresh memory 1 51 during a read cycle is entered into video shift registers 153, 1 55 sixteen-bits parallel at a time and are then shifted out and mixed with the video sync pulses for transmission to the television CRT display, as later described. Each memory access loads the video shift registers 153, 1 55 and sixteen shift pulses are required before another memory access is necessary. During this time, the write cycle occurs for loading the refresh memory 151. The shift frequency on the video shift registers 153, 1 55 is synchronized with the raster scan data for the television CRT display.The video sync generator 163 is driven from crystal oscillator 167 which operates at a frequency of 6.3 MHz that is divided down in divider 1 69 to 1.26 MHz. This clock is level-shifted and is applied to the clock input of the video sync generator 163. This sync generator 163 is connected to the buffer circuit 1 65 which generates the requisite control signals for a television raster which are then mixed in network 159, 1 61 to produce the composite video signal for transmission to the television CRT display. The data output from the memory 1 51 is thus synchronized with the video sync pulses. Addresses are synchronized at the zero count when counters 154, 1 56 attain zero count.This resets the flip-flop 1 62 which, in turn, resets the four-bit binary counter 1 66 to the zero state. This state remains until a vertical drive pulse is received by the flip-flop 1 62 which causes it to be set and to generate an output which resets circuits 1 66 and 1 74 to allow the sequencing of addresses to resume. In this way, the zero address, which coincides with the upper left-hand corner of the CRT display, is always in sync with the vertical drive pulse.

The horizontal line must also be synchronized with the horizontal line of data, consisting of 256 bits derived from sixteen memory accesses of sixteen bits apiece. The video shift registers 153, 155 are shifted at the 6.3 MHz clock rate derived from the main clock that is also applied to the divider 1 64 which divides the clock by sixteen and applies such divided clocking signal to the address counters 154, 1 56. This assures clock pulses for each time the address counter is pulsed. The divided clock is also applied to the video shift registers 153, 1 55 to shift out 256 pulses.At the 256th shift pulse, output appears at the output of circuit 1 66 which resets fliopflop 162 and inhibits the clock to the video shift registers 153, 1 55 and address counters 1 54, 1 56. The clock remains inhibited until the next horizontal drive pulse is applied to circuit 1 70 which then provides a delayed pulse to set flip-flop 1 62 at the proper time for starting the next horizontal line. Again, 256 shift pulses are counted out and flip-flop 1 62 again resets and waits for the proper time to start the next horizontal line, and so on. In this way, both the vertical and the horizontal lines of data are synchronized with the vertical and the horizontal video signals.

As indicated previously, a horizontal drive pulses corresponds to the left side of the raster display. The appearance of such pulse from circuit 1 65 is applied to circuit 1 70 to start a time delay which then starts the circuit 1 62. This time delay is necessary to center the display on the CRT by producing a margin on the left-hand side. When circuit 1 62 is started, the readout from the refresh memory begins by reading out the first horizontal line for display, then the second, the third, and so on up to the 256th line to produce the full display. When the counter 1 54 again attains the zero state, it waits for the next vertical sync pulse to appear again.

A four-bit binary counter 1 75 is used to generate a single write-enable pulse for a single write cycle when individual bits of data are to be transferred from the microprocessor to the refresh memory 151. These individual data bits are used for numerical display of range, etc., on the television CRT display. Only the first three states of this counter are utilized, and it is stopped on the fourth count to wait for another microprocessor input. The write cycle is initiated in response to the microprocessor resetting counter 1 75 to a zero state at which no write occurs. When this counter 1 75 is advanced to state 1, output Q enables the write cycle.The following clock pulse advances counter 1 75 to its second state and the Q output ends that write cycle. The counter 1 75 is stopped by circuit 1 77 and is set to go into an idle state and wait for the next microprocessor routine.

Gate circuit 1 78 serves as a synchronizer between the scratch pad memory and the refresh memory during the data transfer. The data transfer is enabled when signal is applied to terminal 1 80. When the transfer enable signal is applied, the scratch pad memory was previously set to its zero address, and the refresh write memory address was initialized to correspond to the zero address of the scratch pad memory for the particular angle that was just measured. At this time, the clock output on terminal 1 82 is applied to the address counter in the scratch pad memory.

Each clock output advances the scratch pad memory address by 1. The data transfer ends when all 1 28 bits from the scratch pad have been written into the refresh memory.

Referring now to Figs. 6 and 7, there are shown simplified and detailed flow charts, respectively, illustrating the logic sequence of operations of the apparatus of the present invention. After initializing all circuits prior to a scan, the scratch pad memory 24 is enabled and the scratch pad memory 25 is disabled selectively (Fig. 3) to load sea scatter (or echo-inhibit) information N times, as described above. The scratch pad clock is then disabled and interrupt signals therefor are cleared.

With the scratch pad memories thus loaded, the data conversion can take place in the course of transferring data from scratch pad memory to refresh memory. The angle conversion circuits are initialized and the data in scratch pad memory is then converted to X- and Y-coordinate data thereby for storage in the refresh memory. The data thus stored may be processed thereafter to provide the desired video display, as described above. Also, the scratch pad memories are again initialized in preparation for loading with updated data from a subsequent scan. In this manner, the data collected during successive scans, enhanced by eliminating sea scatter (or by inhibiting sonar echoes), converted to orthogonal coordinate data, and then stored in refresh memories for driving a video display unit, thus provides improved image display of surrounding reflective targets.

Still another aspect of the present invention includes the ability to write only "1" into the refresh memory. This provides all bright spots on the CRT display to represent reflections that accumulate along a line of relative movement, as formed during successive scans. This mode of operation is selected by setting the strobe input at terminal T (Fig. 5) to "O" or "ON" during selected scans after a regular scan. This provides "1 '5" only in successive memory locations to produce a display of successive locations, or the relative movement, of a target which may not be large enough to produce a noticeable reflection in any one scan. As a 1 is written into each new memory location, the 1 's denoting reflections at previous memory locations are not erased.

The strobe pulse may be held on for an extended period of time by a conventional timing circuit following normal operation during an initial scan. This feature enables a small target not readily noticeable within the resolution of the system to be enhanced in display so that its relative movement can be tracked, for example, to provide a displayed line-of-movement as an unambiguous-collision avoidance readout. With reference to Fig. 5, this operating condition is established in response to pin 9 of the timing generator 201 circuit attaining the logic "high" state. This is achieved in response to the strobe input (T) and the transfer enable 1 80 and the Interrupt (N) all attaining the logic "high" state.If the strobe (T) is in the "low" state, then the write enable (WE) applied to the pin 9 input of timing generator 201 can only be activated in response to the data inputs appearing in the "1" state, thereby causing a series of "1 's" to be written into successive memory locations.

Therefore, the method and apparatus of the present invention provide improved televisiontype raster display of a radar or sonar signal and facilitate convenient bright display of echo data at locations which are remote from the radar transponder (or sonar transducer). Television signals thus generated may be conducted, as in closed circuit television systems, to standard television monitors, and may also be recorded using standard video recorders. In addition, scanecho data may be processed to remove uncorrelated data such as sea scatter, fish, etc., for improved display of reflective images. Alphanumeric data may also be generated and incorporated into the composite video signal for display of range settings, and the like, along with the reflective images.

APPENDIX-1 Hex Add Hex Address Nemonic Mode OP code Operation Loop Description <img class="EMIRef" id="026950371-00100001" />

<tb> <SEP> SEI <SEP> 78 <tb> #2 <SEP> #1 <SEP> LDA <SEP> <SEP> Im <SEP> A9 <SEP> access <SEP> DDR-A <tb> <SEP> #2 <SEP> <SEP> - <SEP> 2# <SEP> ##1#-1### <SEP> <SEP> (6821) <SEP> disable <tb> <SEP> #3 <SEP> <SEP> STA <SEP> abs <SEP> 8D <SEP> CA1 <SEP> IC# <tb> <SEP> #4 <SEP> - <SEP> <SEP> 8 <SEP> pulse <SEP> CA2 <tb> <SEP> #5 <SEP> <SEP> - <SEP> #A <SEP> <SEP> CRA# <tb> <SEP> #6 <SEP> <SEP> STA <SEP> abs <SEP> 8D <SEP> similar <SEP> to <SEP> above <tb> <SEP> #7 <SEP> <SEP> - <SEP> 8# <SEP> <SEP> temporarily <tb> <SEP> #8 <SEP> <SEP> - <SEP> #B <SEP> <SEP> CR-B# <tb> <SEP> +9 <SEP> LDA <SEP> Im <SEP> A9 <tb> <SEP> #A <SEP> - <SEP> ## <tb> <SEP> (PB <SEP> STA <SEP> abs <SEP> 9D <SEP> PA <SEP> and <SEP> PB <SEP> inputs <tb> <SEP> #C <SEP> - <tb> <SEP> (PD <SEP> - <SEP> fA <SEP> DDR-A# <SEP> <tb> <SEP> #E <SEP> <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> #F <SEP> - <SEP> ## <tb> <SEP> 1# <SEP> <SEP> - <SEP> #B <SEP> <SEP> DDR-B# <tb> <SEP> 11 <SEP> LDA <SEP> Im <SEP> A9 <SEP> 3113 <SEP> access <SEP> DR-A <tb> <SEP> 12 <SEP> - <SEP> 2C <SEP> ##1#-11## <SEP> <SEP> disable <SEP> CA1 <tb> <SEP> 13 <SEP> STA <SEP> abs <SEP> 8D <SEP> pulse <SEP> CA2 <tb> <SEP> 14 <SEP> - <SEP> 8# <tb> <SEP> 15 <SEP> - <SEP> #A <SEP> <SEP> C <tb> <SEP> 16 <SEP> LDA <SEP> Im <SEP> A9 <SEP> ##11-#1## <SEP> <SEP> access <SEP> DR-B <tb> <SEP> 17 <SEP> - <SEP> 34 <SEP> disable <SEP> CB1 <tb> <SEP> 18 <SEP> STA <SEP> abs <SEP> 8D <SEP> toggle <SEP> CB2 <tb> <SEP> 19 <SEP> - <SEP> 9# <tb> #2 <SEP> <SEP> 1A <SEP> - <SEP> #B <SEP> <SEP> CRB# <tb> APPENDIX-2 Hex Add Hex Address Nemonic Mode OP code Operation . Loop Description <img class="EMIRef" id="026950371-00110001" />

<tb> #2 <SEP> <SEP> 1B <SEP> LDA <SEP> Im <SEP> A9 <SEP> access <SEP> DDP-A <tb> <SEP> 1C <SEP> - <SEP> 38 <SEP> ##11-1### <SEP> <SEP> 1C2 <SEP> 682 <tb> <SEP> 1D <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 1E <SEP> - <SEP> 8# <SEP> <SEP> CA2 <SEP> high <tb> <SEP> 1F <SEP> - <SEP> 88 <SEP> CR-A# <SEP> <tb> <SEP> 2# <SEP> <SEP> STA <SEP> abs <SEP> 8D <SEP> access <SEP> DDR-B <tb> <SEP> 21 <SEP> - <SEP> 8# <tb> <SEP> 22 <SEP> - <SEP> 89 <SEP> CR-B# <tb> <SEP> 23 <SEP> LDA <SEP> Im <SEP> A9 <SEP> PA <SEP> outputs <tb> <SEP> 24 <SEP> - <SEP> FF <tb> <SEP> 25 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 26 <SEP> - <SEP> ## <tb> <SEP> 27 <SEP> - <SEP> 88 <SEP> DDR-A# <tb> <SEP> 28 <SEP> LDA <SEP> Im <SEP> A9 <SEP> PBo, <SEP> 1 <SEP> outputs <tb> <SEP> 29 <SEP> - <SEP> #3 <SEP> <SEP> ####-##11 <SEP> PB2, <SEP> 7 <SEP> inputs <tb> <SEP> 2A <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 2B <SEP> - <SEP> ## <tb> <SEP> 2C <SEP> - <SEP> 89 <SEP> DDR-B# <tb> <SEP> 2D <SEP> LDA <SEP> Im <SEP> A9 <SEP> @ <SEP> <SEP> access <SEP> DR-A <tb> <SEP> 2E <SEP> - <SEP> 24 <SEP> ##1#-#1## <SEP> <SEP> CA, <SEP> Z, <SEP> disable <SEP> IR <tb> <SEP> 2F <SEP> STA <SEP> abs <SEP> 8D <SEP> CA2 <SEP> straight <SEP> hand <tb> <SEP> 3# <SEP> <SEP> - <SEP> 8# <SEP> <SEP> shake <tb> <SEP> 31 <SEP> - <SEP> 88 <SEP> CR-A# <SEP> <tb> <SEP> 32 <SEP> LDA <SEP> Im <SEP> A9 <SEP> access <SEP> DR-B <tb> <SEP> 33 <SEP> - <SEP> 34 <SEP> ##11-#1## <SEP> <SEP> disable <SEP> CB1, <SEP> 2 <tb> <SEP> 34 <SEP> STA <SEP> abs <SEP> 8D <SEP> <tb> <SEP> 35 <SEP> - <SEP> 8D <tb> <SEP> 36 <SEP> - <SEP> 89 <SEP> CR-B# <tb> <SEP> 37 <SEP> LDA <SEP> Im <SEP> A9 <tb> <SEP> 38 <SEP> - <SEP> FF <SEP> PB#FF <tb> <SEP> 39 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 3A <SEP> - <SEP> ## <SEP> <SEP> DR-B# <tb> #2 <SEP> <SEP> 35 <SEP> - <SEP> 89 <tb> APPENDIX-3 Hex Add Hex Address Memonic Mode OP code Operation Loop Description <img class="EMIRef" id="026950371-00120001" />

<tb> 92 <SEP> 3C <SEP> LDA <SEP> Im <SEP> A9 <SEP> IC13 <SEP> 6532 <tb> <SEP> 3D <SEP> - <SEP> 93 <SEP> f--X11 <SEP> 1 <SEP> PB,, <SEP> outputs <tb> <SEP> 3E <SEP> STA <SEP> abs <SEP> 8D <SEP> PB2 <SEP> 7 <SEP> input <tb> <SEP> 3F <SEP> - <SEP> 93 <SEP> PB7 <SEP> input <tb> <SEP> 4+ <SEP> - <SEP> 45 <SEP> DDR-Be <tb> <SEP> 41 <SEP> LDA <SEP> Im <SEP> A9 <SEP> Pay <SEP> 3 <SEP> outputs <tb> <SEP> 42 <SEP> - <SEP> (PF <SEP> Xq92-1111 <SEP> PA47 <SEP> inputs <tb> <SEP> 43 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 44 <SEP> - <SEP> (P1 <tb> <SEP> 45 <SEP> - <SEP> 45 <SEP> DDR-A <tb> <SEP> 46 <SEP> STA <SEP> abs <SEP> 8D <SEP> disable <SEP> timer <tb> <SEP> 47 <SEP> - <SEP> 94 <tb> <SEP> 48 <SEP> - <SEP> 45 <tb> <SEP> 49 <SEP> STA <SEP> abs <SEP> 8D <SEP> disable <SEP> Int. <tb>

<SEP> 4A <SEP> - <SEP> 84 <tb> <SEP> 4B <SEP> - <SEP> 45 <tb> <SEP> 4C <SEP> LDA <SEP> Im <SEP> A9 <SEP> Mem <SEP> 4 <SEP> WE <SEP> on <tb> <SEP> 4D <SEP> - <SEP> 55 <SEP> 9191-11 <SEP> Mem <SEP> 5 <SEP> WE <SEP> off <tb> <SEP> 4E <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 4F <SEP> - <SEP> +2 <tb> <SEP> SD <SEP> - <SEP> 45 <tb> <SEP> 51 <SEP> LDA <SEP> Z <SEP> A5 <SEP> v <SEP> load <SEP> N <SEP> repeater <tb> <SEP> 52 <SEP> R7 <SEP> f7 <SEP> G3 <SEP> into <SEP> working <SEP> sig <tb> <SEP> 53 <SEP> STA <SEP> Z' <SEP> 85 <tb> <SEP> 54 <SEP> R-G <SEP> 06 <tb> <SEP> 55 <SEP> LDA <SEP> Im <SEP> A9 <SEP> .<SEP> disable <SEP> rear <SEP> scatter <tb> <SEP> 56 <SEP> - <SEP> (P2 <SEP> < > 2 <SEP> *-X1d <SEP> in <SEP> S <SEP> Pad <SEP> clock <tb> <SEP> 57 <SEP> STA <SEP> abs <SEP> 8D <SEP> (release <SEP> clear) <tb> <SEP> 58 <SEP> - <SEP> (P(P <tb> 92 <SEP> 59 <SEP> - <SEP> 45 <SEP> DR-At2 <tb> APPENDIX-4 Hex Add Hex Address Nemonic Mode OP code Operation Loop Description <img class="EMIRef" id="026950371-00130001" />

<tb> f2 <SEP> 5A <SEP> 1 <SEP> Z <SEP> EA <tb> <SEP> SB <SEP> EA <tb> <SEP> SC <SEP> EA <tb> <SEP> SD <SEP> EA <tb> <SEP> 5E <SEP> EA <SEP> 1C2 <tb> <SEP> 5F <SEP> LDA <SEP> -abs <SEP> AD <SEP> < <SEP> Initiate <SEP> hand <SEP> shake <tb> <SEP> 69 <SEP> 0 <SEP> (P(P <SEP> 1 <SEP> clear <SEP> IRQ-A <SEP> flag <tb> <SEP> 61 <SEP> - <SEP> 88 <SEP> AcDR-A <tb> <SEP> 62 <SEP> BIT <SEP> abs <SEP> 2C <SEP> v <SEP> wait <SEP> for <SEP> S. <SEP> Pad <tb> <SEP> 63 <SEP> - <SEP> 8f <SEP> t <SEP> Int.<SEP> flag <tb> <SEP> 64 <SEP> - <SEP> 88 <SEP> V~CR-A7 <tb> <SEP> 65 <SEP> BPL <SEP> 1(P <tb> <SEP> 66 <SEP> - <SEP> FB <tb> <SEP> 67 <SEP> BIT <SEP> abs <SEP> 2C <SEP> v <SEP> Wait <SEP> for <SEP> S. <SEP> Pad <tb> <SEP> 68 <SEP> - <SEP> +2 <SEP> 9 <SEP> to <SEP> complete <SEP> scan <tb> <SEP> 69 <SEP> - <SEP> 45 <SEP> VtPB6 <tb> <SEP> 6A <SEP> BVS <SEP> 79 <tb> <SEP> 6B <SEP> - <SEP> FB <tb> 02 <SEP> 6C <SEP> LDA <SEP> Im <SEP> A9 <tb> <SEP> 6D <SEP> - <SEP> +3 <SEP> (P3 <SEP> (P(P(P(P-(P(P1 <SEP> 11 <SEP> compliment <SEP> WE's <tb> <SEP> 6E <SEP> EOR <SEP> abs <SEP> 40 <tb> <SEP> 6F <SEP> - <SEP> (P2 <tb> <SEP> 7(P <SEP> - <SEP> 45 <tb> <SEP> 71 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 72 <SEP> - <SEP> f2 <SEP> PB(i <SEP> 3 <tb> +2 <SEP> 73 <SEP> - <SEP> 45 <tb> APPENDIX-5 Hex Add Hex Address Nemonic Mode OP code Operation Loop Description <img class="EMIRef" id="026950371-00140001" />

<tb> +2 <SEP> 74 <SEP> DEC <SEP> Z <SEP> C6 <SEP> Dec <SEP> (.) <SEP> (are <SEP> scit. <tb>

<SEP> syrata) <tb> <SEP> 75 <SEP> PC <SEP> (P6 <tb> <SEP> 76 <SEP> BEQ <SEP> F(P <SEP> As <SEP> if <SEP> completed <tb> <SEP> 77 <SEP> - <SEP> 98 <tb> <SEP> 78 <SEP> LDR <SEP> Im <SEP> R9 <tb> <SEP> 79 <SEP> - <SEP> +2 <SEP> (P-(P(P1 <SEP> f <SEP> 11 <SEP> visible <SEP> bead <SEP> scatter <tb> <SEP> 7A <SEP> STA <SEP> abs <SEP> 8D <SEP> visible <SEP> S. <SEP> Pad <SEP> clock <tb> <SEP> 7B <SEP> - <SEP> X <SEP> 9 <SEP> (cut <SEP> off) <tb> <SEP> 7C <SEP> - <SEP> 45 <SEP> PA <SEP> and <SEP> 2 <tb> <SEP> 7D <SEP> JMP <SEP> abs <SEP> 4C <tb> <SEP> 7E <SEP> - <SEP> 5F <tb> <SEP> 7F <SEP> - <SEP> (P2 <tb> <SEP> 84 > <SEP> LDA <SEP> Im <SEP> A9 <SEP> < <SEP> disable <SEP> S.<SEP> Pad <tb> <SEP> 81 <SEP> - <SEP> f5 <SEP> 9-191 <SEP> clock <SEP> visible <SEP> arc <tb> <SEP> 82 <SEP> STA <SEP> abs <SEP> 8D <SEP> 9 <SEP> scatter <tb> <SEP> 83 <SEP> X <tb> <SEP> 84 <SEP> - <SEP> 45 <SEP> PA <SEP> and <SEP> 05 <tb> <SEP> 85 <SEP> LDR <SEP> Im <SEP> A9 <tb> <SEP> 86 <SEP> - <SEP> f1 <SEP> f-~1 <SEP> clear <SEP> S. <SEP> Pad <tb> <SEP> 87 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 88 <SEP> - <SEP> (P(P <tb> <SEP> 89 <SEP> - <SEP> 45 <SEP> PA <SEP> and <SEP> 91 <tb> <SEP> 8A <SEP> LDR <SEP> Im <SEP> A9 <tb> <SEP> 8B <SEP> - <SEP> 7(P <SEP> Init <SEP> X <SEP> address <tb> <SEP> 8C <SEP> STA <SEP> abs <SEP> 8D <SEP> emitter <SEP> IC1, <SEP> 2 <tb> <SEP> 8D <SEP> - <SEP> < <SEP> PR <SEP> and <SEP> 6ss4 <tb> <SEP> 85 <SEP> - <SEP> 88 <tb> <SEP> 8F <SEP> CLC <SEP> 18 <tb> <SEP> 92 <SEP> ROL <SEP> abs <SEP> 2E <tb> <SEP> 91 <SEP> - <SEP> X <tb> <SEP> 91 <SEP> - <SEP> 89 <tb> f2 <SEP> 93 <SEP> SEC <SEP> 38 <tb> APPENDIX-6 Hex Add Hex Address Nemonic Mode OP code Operation Loop Description <img class="EMIRef" id="026950371-00150001" />

<tb> +2 <SEP> 94 <SEP> ROL <SEP> abs <SEP> 2E <tb> <SEP> 75 <SEP> , <tb> <SEP> 96 <SEP> - <SEP> 87 <tb> <SEP> 97 <SEP> LDA <SEP> Im <SEP> A9 <tb> <SEP> 98 <SEP> - <SEP> 89 <tb> <SEP> 99 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> 9A <SEP> - <SEP> < <SEP> Initialize <SEP> Y <SEP> addresss <tb> <SEP> 9B <SEP> - <SEP> 88 <SEP> PAt80n <tb> <SEP> 9C <SEP> SEC <SEP> 38 <tb> <SEP> 9D <SEP> RDL <SEP> abs <SEP> 2E <tb> <SEP> 9E <SEP> - <SEP> (P(P <tb> <SEP> 9F <SEP> - <SEP> 89 <tb> (P2 <SEP> A(P <SEP> LDA <SEP> Im <SEP> A9 <SEP> disable <SEP> rear <SEP> scatter <tb> <SEP> Al <SEP> - <SEP> < <SEP> disable <SEP> S. <SEP> Pad <SEP> clock <tb> <SEP> A2 <SEP> STA <SEP> abs <SEP> 8D <SEP> (release <SEP> clear) <tb> <SEP> A3 <SEP> - <SEP> (P(P <tb> <SEP> A4 <SEP> - <SEP> 45 <SEP> DR-At2 <tb> <SEP> A5 <SEP> LDA <SEP> Im <SEP> A7 <SEP> put <SEP> transfers <tb> <SEP> A6 <SEP> - <SEP> +9 <SEP> ,-1X1 <SEP> enable <SEP> high <tb> <SEP> A7 <SEP> STA <SEP> abs <SEP> 8D <tb> <SEP> A8 <SEP> - <SEP> (P(P <tb> <SEP> A9 <SEP> - <SEP> 45 <tb> <SEP> AA <SEP> BIT <SEP> abs <SEP> 2C <SEP> v <SEP> Wait <SEP> on <SEP> completion <tb> <SEP> AB <SEP> - <SEP> 32 <SEP> of <SEP> data <SEP> transfer <tb> <SEP> AC <SEP> - <SEP> 45 <tb> <SEP> AD <SEP> FF <SEP> 70 <tb> <SEP> AE <SEP> - <SEP> FC <tb> <SEP> AF <SEP> EA <SEP> Im <SEP> A9 <SEP> f <SEP> lower <SEP> data <SEP> transfer <tb> <SEP> Bf <SEP> - <SEP> 01 <SEP> -ss1 <SEP> [X] <tb> <SEP> B1 <SEP> STR <SEP> abs <SEP> 8D <tb> <SEP> B2 <SEP> X <tb> <SEP> B3 <SEP> - <SEP> 45 <tb> <SEP> B4 <SEP> JrP <SEP> abs <SEP> 4C <SEP> [EB] <tb> <SEP> B5 <SEP> - <SEP> 51 <SEP> [EM] <tb> <SEP> B6 <SEP> - <SEP> +3 <SEP> [EB] <tb> APPENDIX-@ Nemonic Explanation (for Model 6502 Microprocessor) SEI Set interrupt disable LDA Load data from memory into accumulator STA Store data from accumulator into memory R6 Register number R7 Register number BIT Test status of bits in accumulator BPL Test specific bit in accumulator BVS Bit test EOR Exclusive OR DEC Decrement BEQ Branch on results equal JMP Jump to address specified in next two lines ROL End-around shift SEC Set carry Im Immediate (in address mode) abs absolute (in address mode) Z Zero page (in address mode) CR-A Control register A CR-B Control register B DDR-A Data direction register A DDR-B Data direction register B DR-A Data register A DR-B Data register B APPENDIX-8 Nemonic Explanation (for Model 6502 Microprocessor) A Accumulator V Denotes 7th bit PA Port A on I/O chips PB Port B on I/O chips CA-1 On side A of I/O chips, 1 identifies interrupt CA-2 On side A of I/O chips, 2 identifies output driver CB-1 On side B of I/O chip, 1 identifies interrupt CB-2 On side B of I/O chip, 2 identifies output driver IRQ Interrupt request between processor and I/O chip WE Write enable

Claims (16)

  1. CLAIMS .1. A method of generating a display of remote objects as the composite of echo reflection signals therefrom, the method comprising the steps of: transmitting a high-energy signal in the direction of remote reflective objects; receiving reflections of the transmitted signals back from such objects at delay intervals following the transmissions thereof which are proportional to the distances to such objects; storing a plurality of successive separate representations of received reflections for subsequent sequential recall; converting the stored representations of received reflections into coordinate data indicative of received reflections; accumulating the coordinate data at sequentially addressed locations; and accessing the coordinate data from the sequentially addressed locations in synchronism with raster-formatted output manifestations to produce a raster-type display of the received reflections.
  2. 2. The method according to claim 1 including the step of quantifying the amplitudes of received reflections with respect to a selected amplitude limit for storing each of said representations as one of at least two distinct logic states.
  3. 3. The method according to claim 1 wherein the steps of transmitting a high-energy signal and of receiving reflections include transmitting and receiving electromagnetic, radio-frequency signals.
  4. 4. The method according to claim 1 wherein the steps of transmitting a high-energy signal and of receiving reflections include transmitting and receiving acoustic-pulse signals.
  5. 5. The method according to claim 1 wherein: the transmission of high-energy signal recurs successively in angular directions which vary as a function of time; and the step of converting the stored representations includes altering the coordinate data in response to the angle at which a reflection is received.
  6. 6. The method according to claim 1 wherein the step of storing the successive representations is performed as a selected rate relative to an interval during which reflections are received for providing an output indication of the distance to an object from which a reflection was received.
  7. 7. The method according to claim 1 wherein the steps of transmitting and receiving at a selected angular direction are repeated after a delay period and comprising the additional step of: comparing each of the successive, separate representations of reflections received during a transmitting and receiving step in the selected angular direction with the corresponding successive separate representation of reflections received during a previous transmitting and receiving step in the same selected angular direction to produce representations of correlated reflections for subsequent, successive recall; and wherein the steps of converting, accumulating and accessing are performed with respect to the correlated reflections.
  8. 8. The method according to claim 1 wherein: in the step of accumulating coordinate data, the successive separate representations of received reflections at successive relative locations are accumulated and stored in sequential addressed locations; and in the step of accessing, the accumulated coordinate data is accessed to produce a display of each of a sequence of locations along a path of relative movement of such object.
  9. 9. Apparatus for producing an output indication of remote objects as a composite of signal reflections received therefrom the aparatus comprising: means for transmitting high-energy signal in the direction of remote objects; means for receiving reflections of the transmitted signals from remote objects to produce signals representative thereof; storage means connected to the means for receiving to store a plurality of separate signals derived in rapid succession from reflections received following the transmission of the highenergy signals; converter means coupled to said storage means for transforming each of the plurality of separate signals stored in the storage means to coordinate data signals; memory means coupled to receive the coordinate data signals for storage thereof in successively addressed memory locations;; display means for producing a raster-type display of signals applied thereto; and output means coupled to said display means and to said memory means for accessing at a selected rate the signals stored in the memory means at the successive locations for applying to the display means in synchronism with the raster-type operation thereof a succession of signals which are representative of the coordinate data signals stored in the memory means.
  10. 10. Apparatus as in claim 9 comprising quantizing means coupled to receive reflected signals for applying to said storage means said signal having either one of only two logic states that are determined relative to a selected amplitude of received signal.
  11. 11. Apparatus according to claim 9 wherein the means for transmitting and the means for receiving respectively transmit and receive electromagnetic, radio-frequency signals.
  12. 1 2. Apparatus according to claim 9 wherein the means for transmitting and the means for receiving respectively transmit and receive acoustic-pulse signals.
  13. 1 3. Apparatus as in claim 9 wherein: the means for transmitting produces a plurality of successive high-energy signals for transmission to remote objects along angular directions which vary with time; resolver means for producing output signals indicative of the angle of transmission; and said converter means being coupled to receive the output signals from the resolver means for producing said coordinate data signals indicative of the corresponding angular directions.
  14. 14. Apparatus as in claim 9 wherein said storage means operates at a selectable rate- to derive from the received reflections said separate signals which are indicative of the distances to the objects from which reflections are received.
  15. 1 5. Apparatus according to claim 9 comprising: comparator means coupled to receive from said storage means the separate signals stored therein from a previous transmission and reception with corresponding separate signals derived from a current transmission and reception to produce outputs representative of correlated received reflections; auxiliary storage means coupled to receive said outputs for storage thereof in successive addressed locations; and said converter means is selectively coupled to said auxiliary storage means for producing said coordinate data signals in response to the separate signals stored therein.
  16. 16. Apparatus as in claim 9 comprising: strobe means coupled to the memory means and selectively operable therewith to control storage of each of the coordinate data signals associated with reflections received in the directions of successive relative locations of the remote object during successive transmissions and receptions of high-energy signals; and said output means accesses each of the stored coordinate data signals to produce a display of the succession of locations along a path of relative movement of the remote object.
    1 7. A method of generating a display of remote objects as the composite of echo reflection signals therefrom substantially as hereinbefore described with reference to the accompanying drawings.
    1 8. Apparatus for producing an output indication of remote objects as a composite of signal reflections received therefrom substantially as hereinbefore described with reference to the accompanying drawings.
GB7938389A 1978-11-13 1979-11-06 Digital scan converter Withdrawn GB2037117A (en)

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US95998878 true 1978-11-13 1978-11-13
US327679 true 1979-01-15 1979-01-15

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443797A (en) * 1980-01-22 1984-04-17 Decca Limited Radar display apparatus
EP0639032A2 (en) * 1993-08-09 1995-02-15 C-Cube Microsystems, Inc. Structure and method for a multistandard video encoder/decoder
US5910909A (en) * 1995-08-28 1999-06-08 C-Cube Microsystems, Inc. Non-linear digital filters for interlaced video signals and method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443797A (en) * 1980-01-22 1984-04-17 Decca Limited Radar display apparatus
EP0639032A2 (en) * 1993-08-09 1995-02-15 C-Cube Microsystems, Inc. Structure and method for a multistandard video encoder/decoder
EP0639032A3 (en) * 1993-08-09 1995-11-29 C Cube Microsystems Structure and method for a multistandard video encoder/decoder.
US5598514A (en) * 1993-08-09 1997-01-28 C-Cube Microsystems Structure and method for a multistandard video encoder/decoder
US5740340A (en) * 1993-08-09 1998-04-14 C-Cube Microsystems, Inc. 2-dimensional memory allowing access both as rows of data words and columns of data words
US6071004A (en) * 1993-08-09 2000-06-06 C-Cube Microsystems, Inc. Non-linear digital filters for interlaced video signals and method thereof
US6122442A (en) * 1993-08-09 2000-09-19 C-Cube Microsystems, Inc. Structure and method for motion estimation of a digital image by matching derived scores
US5910909A (en) * 1995-08-28 1999-06-08 C-Cube Microsystems, Inc. Non-linear digital filters for interlaced video signals and method thereof

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