GB2034079A - Lift control system - Google Patents

Abstract

A control system, for use with a lift cage CG, has an induction motor IM, normally driven by AC source 12, a dc current source BA for use in case of emergency, and an inverter INV for inverting the dc current into an ac current to be supplied to the motor. The control system includes a speed detector 6 for detecting the speed of the cage and generating a first signal when the cage speed reaches a maximum available speed and until the cage speed decreases to a minimum available speed and a second signal when the cage speed reaches the minimum available speed and until the cage speed increases to the maximum available speed. The second signal is used to cause the inverter to invert the dc current into the ac current for driving the cage while the first signal is used to caused the inverter to generate an intermittent or chopped dc current for damping the cage. <IMAGE>

Description

SPECIFICATION Control system for use in a lift The present invention relates to a lift or an elevator and, more particularly, to-a control system for controlling the movement of the lift when an accident such as power failure takes place.

Generally, from the view point of safety operation, when an accident should occur, a cage of the lift is forcibly and mechanically held still even during its operation and, at the same time, an electric power supply line is disconnected from a motor, which drives the lift, for stopping the cage.

When the cage is stopped at an intermediate distance between the floors, the passengers can be trapped in the cage. In order to rescue the trapped passengers, the lift is temporarily driven by a battery which is provided for the emergency cases. However, since such battery is not always charged fully, the battery may be half dead. When such a battery is used, there may be possibility that the motor is supplied with an insufficient voltage and, therefore, the motor may not give a sufficient driving torque. In this case, the motor torque may become so small that it can not regulate the cage speed against the difference in weight between the cage and a counter weight and, in the worst it may happen, the speed of the cage may become over-speeding. As a consequence, a speed regulator which is so-called a governer is actuated to forcibly stop the cage again.

Accordingly, a primary object of the present invention is to provide a control system for controlling the lift to move within a limited range of speed when an accident should occur.

Another object of the present invention is to provide a control system of the above described type which is simple in construction and can readily be manufactured at low cost. According to the present invention, there is disclosed a control system for use in a lift having a cage, a motor drive by an ac current, a dc current source and an inverter for inverting the dc current into ac current to be supplied to the motor, said control system comprises a speed detecting means for detecting the speed of the cage, means for generating a first signal when the cage speed reaches a maximum available speed and until the cage speed decreases to a minimum available speed, means for generating a second signal when the cage speed reaches a minimum available speed and until the cage speed increases to the maximum available speed, means responsive to the second signal for actuating said inverter to invert the dc current of the dc current source into the ac current, said inverted ac current driving the motor to increase the speed of the cage, a chopper for chopping the dc current, and means responsive to the first signal for actuating the chopper to convert the dc current into a chopped dc current, said chopped dc current being supplied to the motor as a damping current to decrease the speed of the cage.

According to another aspect of the present invention, there is also disclosed a control system for use in a lift having a cage, said control system comprising a motor adapted to be driven by a three phase ac current for driving the cage, a source of dc current having positive and negative sides, a circuit having a first diode and a first transistor connected in parallel to each other between a first common terminal and-the positive side of the dc current source, a second diode and a second transistor connected in parallel to each other between the first common terminal and the negative side of the dc current source, a third diode and a third transistor connected in parallel to each other between a second common terminal and the positive side of the dc current source, a fourth diode and a fourth transistor connected in parallel to each other between the second common terminal and the negative side of the dc current source, a fifth diode and a fifth transistor connected in parallel to each other between a third common terminal and the positive side of the dc current source, and a sixth diode and a sixth transistor connected in parallel to each other between the third common terminal and the negative side of the dc current source, said first, second and third common terminals being connected to the motor through switches, a speed detecting means for detecting tbe speed of the cage, means for generating a first signal when the cage speed reaches a maximum available speed and until the cage speed decreases to a minimum available speed, means for generating a second signal when the cage speed reaches the minimum available speed and.until the cage speed increases to the maximum available speed, control means connected to the respective bases of the first, second, third, fourth, fifth and sixth transistors in the circuit and also to said means for generating the first signal and said means for generating the second signal, said control means upon receipt of the second signal, sequentially causing the first to sixth transistors to conduct in a predetermined order to invert the dc current into three phase ac current, said three phase ac current being supplied from the first, second and third common terminals to the motor of the first signal, intermittently causing two of the odd or even numbered transistors to conduct for supplying chopped dc current to the motor for damping the cage.

The foregoing and other objects, features and advantages of the invention will be apparent from the following description of the invention with reference to the accompanying drawings in which: Fig. 1 is a block diagram of a lift provided with a control system according to the present invention; Fig. 2 is a graph showing the speed change when the control system according to the present invention is actuated; Fig. 3 is a circuit diagram showing the details of a controller shown in Fig. 1; Fig. 4 is a graph showing waveforms obtained at major points in the circuit shown in Fig. 3; Fig. 5 is a circuit diagram showing a flow of damping current; and Fig. 6 is a circuit diagram similar to Fig. 3, showing a modified form of the controller.

Referring to Fig. 1, a lift includes an induction motor IM normally supplied with a three phase alternating current from a commercial ac power source 2 through a drive controller 4. The - induction motor IM has a drive shaft connected through a reduction gear arrangement GC to a sheave SHover which ropes are passed from a cage CG to a counter weight CW. A control system according to the present invention includes a speed detector 6 for detecting the speed of the cage CG. The speed detector 6 can be a tachometer generator coupled to a sheave SH or to the drive shaft of the induction motor IM for producing a voltage indicative of the speed of the cage CG. The output signal from the speed detector 6 is applied to first and second comparators 8 and 10.The first comparator 8 contains a reference voltage producer which produces a reference voltage corresponding to a maximum available speed of the cage, while the second comparator 10 contains a reference voltage producer which produces a reference voltage corresponding to a minimum available speed of the cage CG. The outputs of the first and second comparators 8 and 10 are applied to a bistable multi-vibrator 1 2 while the output of the vibrator 12 is connected to a controller 14. The output of the controller 14 is connected to an inverter INV.

An accident detector AD is connected to the drive controller 4 and is operable to detect the accident such as an interruption of the electric power from the ac power source 2 or a breakdown of the drive controller 4 and to produce an emergency signal to the controller 14 and also to a relay 1 6. The relay 16 is operatively associated with switches Hb1, Hb2, and Hb3, which are normally held in a closed position, and also with switches Hal, Ha2 and Ha3 which are normally held in an opened position. The switches Hal, Ha2 and Ha3 are connected between the inverter INV and the induction motor IM while the switches Hb1, Hb2 and Hb3 are connected between the drive controller 4 and the induction motor IM.

When the relay 1 6 is in a first or normal position, that is, when the accident detector AD detects no accident, the switches Hbl, Hb2 and Hb3 are held in the closed position while the switches Hal, Ha2 and Ha3 are held in the opened position. When the accident detector AD detects an accident, the emergency signal is applied to the relay 1 6 to turn the latter to a second or emergency position and, accordingly, the switches Hbl, Hb2 and Hb3 are turned to the opened position while the switches Hal, Ha2 and Ha3 are turned to the closed position.

The inverter INV is coupled with a battery BA and includes positive and negative lead lines 20 and 22 which extend from the battery BA. Seriesconnected diodes D1 and D2 are connected between the lines 20 and 22 in a reverse biased direction. Similarly, series-connected diodes D3 and D4 and sehes-connected diodes D5 and D6 are connected between the lines 20 and 22. The inverter NV further includes series-connected transistors T1 and T2 connected between the lines 20 and 22. More particularly, the collector of the transistor T1 is connected to the line 20 and the emitter of the same is connected to the collector of the transistor T2. The emitter of the transistor T2 is connected to the line 22.Similarly, seriesconnected transistor 13 and T4 and seriesconnected transistors T5 and T6 are connected between the lines 20 and 22. A junction J 1 between the diodes D1 and D2 is connected to a junction J2 between the transistors T1 and T2 and also to the switch Ha 1. A junction J3 between the diodes D3 and D4 is connected to a junction J4 between the transistors T3 and T4 and also to the switch Ha2. Likewise, a junction J5 between the diodes D5 and D6 is connected to a junction J6 between the transistors T5 and T6 and also to the switch Ha3. The bases of transistors Ti to T6 are connected to the controller 14 which individually supplies control signals to the transistors T1 toT6.

The operation of the control system will now be described hereinafter.

When the accident detector AD detects an accident and produces the emergency signal, the relay 1 6 is so actuated as to disconnect the induction motor IM from the ac power source 2 and connect the same to the battery BA through the inverter INV and, at the same time, the controller 14 actuates on the inverter INV to invert the dc current of the battery BA into three phase ac current. The details of the inversion are described later in connection with Fig. 3. Such inverted ac current is applied through the switches Hal, Ha2 and Ha3 to the induction motor IM.

Accordingly, the induction motor IM is driven to move the cage CG and the cage CG is normally operated at a given rated speed determined by the frequency of the supplied ac current. When the speed of the cage increases and reaches the maximum available speed V2 by an accident, the first comparator 8 generates a high level signal to the multi-vibrator 1 2 to produce one of the two binary signals, for example, a low level signal. The time at which the low level signal is generated from the multi-vibrator 12 corresponds to the moment tl in a graph shown in Fig. 2 in which the axes of ordinate and abscissa represent velocity and time, respectively. Upon receipt of the low level signal from the multi-vibrator 12,-the controller 14 is actuated to produce a chopped dc current or a dc damping current from the inverter INV. In this case, the inverter INV operates as a chopper. The damping current is then applied to the induction motor IM to slow down the cage CG. When the speed the cage CG- reaches a minimum available speed V3, the second comparator 10 generates a high level signal to the multi-vibrator 12 to produce a high level signal to the multi-vibrator 12 to produce the other of the two binary signals, that is, a high level signal. The time at which the high level signal is generated from the multi-vibrator 1 2 corresponds to the moment t2 shown in Fig. 2.Such a high level signal is applied to the controller 14 which again actuates the inverter INV to invert the dc current of the battery BA into three phase ac current. Accordingly, the speed of the cage CG increases until it reaches the speed V2. Thereafter, a similar operation is repeated to keep the speed of the cage CG within the limited available speed.

When the cage CG reaches a level near one of a plurality of floors or stairs at the moment t6 shown in Fig. 2, a mechanical brake of any known type is actuated to bring the cage CG to a proper stopping position.

Referring to Fig. 3, the controller 14 according to one embodiment of the present invention includes first and second oscillators 30 and 32 which are capable of producing a train of pulse signals 0-1 and 0-2, respectively. The waveform of such pulse signals 0-1 and 0-2 are shown in Fig. 4. The oscillator 30 is connected to a counter 34 having three outputs 00, Q1 and Q2 representing decimal numbers of 1,2 and 4, respectively. The outputs 00, Ol and Q2 of the counter 34 is connected to a decoder 36 having seven outputs, QO, 01, Q2, 03, Q4, OS and Q6 in which the output 06 is connected to a reset terminal R of the counter 34. The outputs QO to Q6 sequentially produce a pulse signal as the counter 34 counts from 0 to 6.The signals from the outputs 00 to Os of the decoder 36 are represented by reference characters A, B, C, D, E and F, and the waveforms of which are shown in Fig. 4. The outputs 00, 01 and 02 of the decoder 36 is connected to an OR gate 38. Similarly, outputs Q1.02 and 03 are connected to an OR gate 40; outputs 02, 03 and Q4 are connected to an OR gate 42; outputs Q3, Q4, and OS are connected to an OR gate 44; outputs Q4, OS and QO are connected to an OR gate 46; and outputs Q5, QO and Q1 are connected to an OR gate 48.

Accordingly, each of the OR gates 38 to 48 produce a pulse signal having a pulse duration corresponding to three sequential pulses from the decoder 36. The outputs signals from the OR gates 38 to 48 are represented by reference characters A', B', C', D', E' and F', respectively, and the waveforms of which are shown in Fig. 4.

The outputs of the OR gates 38 to 48 are connected to one input of AND gates 50, 52, 54, 56, 58 and 60 respectively. The other input of AND gates 50 to 60 are connected to the output of the multi-vibrator 12. The output of the AND gates 52, 54, 56 and 58 are connected to photocouplers 68, 70, 72 and 74, respectively, while the output of the AND gates 50 and 60 are connected through OR gates 62 and 64 to photocouplers 66 and 76, respectively. These photocouplers 66 to 76 constitutes buffer.circuits each including light emitting diode LD and a photoresponsive transistor PT.The photoresponsive transistor PT of the photocoupler 66 is connected to the transistor T1 of the inverter INV in such a manner that the collector and emitter of the photoresponsive transistor PT are respectively connected to the collector and base of the transistorT1. In a similar manner, the photoresponsive transistors PT of the photo couplers 68, 70, 72, 74 and 76 are connected to the transistors T6, T3, T2, T5 and T4 of the inverter lNV, respectively.

The second oscillator 32 is connected to one input of an AND gate 78 and, in turn, the OR gate 62 and 64. The other input of the AND gate 78 is connected through an inverter 80 to the output of the multi-vibrator 12. The operation of the controller 14 described above is explained hereinbelow.

When the accident detector AD detects the accident and produces the emergency signal, a source of electric power (not shown) is connected for supplying power to the controller 14. At such a moment, since the speed of the cage GC is considerably low, the multi-vibrator 12 produces a high level signal to enable the AND gates 50, 52, 54, 56, 58 and 60 on one hand and to disabie the AND gate 78 on the other hand. Accordingly, upon receipt of the emergency signal, the train of pulses from the oscillator 30 is applied to the counter 34 and to the decoder 36 which sequentially produces the pulse signals A, B, C, D, E and F from the outputs 00, 01,02, 03, Q4 and Q5, respectively.Three sequential signals are combined with each other in the OR gates 38 to 48 to form pulse signals A', B', C', D', E' and F' as shown in Fig. 4 each having a longer pulse duration than that of any one of the pulse signals A to F. Since the AND gates 50 to 60 are enabled, the pulse signals A' to F' are applied to the photp couplers 66 to 76, respectively. In this case, that is, when the muiti-vibrator 12 produces a high level signal, the signals AO to FO applied to the photo-couplers 66 to 76, respectively, are exactly -the same as the signals A' to F' produced from the OR gates 38 to 48. When the photo-coupler receives the high level signal, the transistor coupled thereto conducts. Accordingly, in the inverter INV, the dc current from the battery BA is inverted into three phase ac current which is supplied to the induction motor IM.

Thereafter, when the speed of the cage CG becomes higher and reaches a maximum available speed V2 by an accident, a high level signal is produced from the first comparator 8 to cause the multi-vibrator 12 to produce a low level signal.

Upon receipt of the low level signal from the multivibrator 12, the AND gates 50 to 60 are disabled while the AND gate 78 is enabled. Accordingly, the sequential pulse signals A' to F' are prevented from being transmitted through the AND gates 50 to 60. On the contrary, the pulse signal from the second oscillator 32 is applied through the AND gate 78 to the OR gate 62 and 64 and further to the photo-couplers 66 and 76. In this case, that is, when the multi-vibrator 12 is producing a low level signal, the signals AO and FO applied to the photo-couplers 66 and 76 correspond to the pulse signal produced from the second oscillator 32 while the signals BO, CO, DO and EO applied to the photo-couplers 68, 70, 72 and 74 are maintained in a low level state.Accordingly, in the inverter INV, the transistorT1 and T4 are simultaneously turned on and off for producing a chopped dc current or damping current ID which is applied to the induction motor IM as shown in Fig. 5 in which a reference character CL designates a stator coil of the induction motor IM. Thus, the induction motor IM produces the damping torque to speed down the cage CG. When the speed of the cage CG is reduced to a minimum available speed V3, the second comparator 10 produces a high level signal to cause the multi-vibrator 12 to produce a high level signal to cause the -multi-vibrator 1? to produce a high level signal. Again, the three phase ac current is applied to the induction motor IM.

Referring to Fig. 6, the controller 14 of a modified form is shown. This controller 14 includes a third oscillator 82 arranged to produce a high frequency pulse signal such as of several kilo Hz which is used as a carrier wave. The structure of the modified form is described hereinbelow together with its operation.

When the multi-vibrator 12 produces a high level signal, the AND gates 50 to 60 are enabled and, also, an AND gate 84 connected between the first oscillator 30 and the counter 34 is enabled.

Accordingly the pulse signal produced from the first oscillator 30 is applied through the AND gate 84 to the counter 34. Thus, the decoder 36 sequentially produces a pulse signal in the same manner as described above. In this modification, the AND gates 50 and 60 are connected to the outputs (10 to Q5 of the decoder 36, respectively, while the OR gates 38 to 48 have one input connected to the output of the corresponding AND gates while the remaining inputs are connected directly to the outputs of the decoder 36 in a similar manner as described above. Accordingly, the OR gates 38,40, 42,44,46 and 48 produce pulse signals AO, BO, CO, DO, EO and FO, respectively, which are in turn applied to buffer circuits 92, 94, 96, 98, 100 and 102.Each of the buffer circuits includes AND gates 104 and 106, an emitter-grounded transistor 11 2 having the base thereof connected through a resistor 108 to the output of the AND gate 104 and an emitter grounded transistor 114 having the base thereof connected through a resistor 110 to the output of the AND gate 106. A pulse transformer 11 6 includes primary and secondary windings, the primary winding being connected between the collectors of the transistors 112 and 114. Series connected diodes 118 and 120 and series connected diodes 122 and 124 are connected in parallel to each other between junctions J7 and J8.The secondary winding of the pulse transformer 11 6 is connected between a junction of the diodes 118 and 120 and a junction of the diodes 122 and 1 24. A series circuit of a resistor 1-26 and a capacitor 128 is connected between the junctions J7 and J8. The output signal from the buffer circuit 92 is taken out across the capacitor 128 which is inserted between the base and emitter of the transistor T1 of the inverter INV.

In a similar manner, the buffer circuits 94, 96, 98, 100 and 102 are connected to the transistors T6, T3, T2, T5 and T4, respectively. In this case, when the multi-vibrator 12 produces a high level signal, a NAND gate 86 produces a high level signal and therefore the AND gate 88 is enabled. Thus, the high frequency pulse signal 0-3 through the AND gate 88 is supplied to the AND gate 106 and also is supplied to the AND gate 104 through the inverter 90. Therefore, when the OR gate 38 produces positive going pulse signal, it is carried on the carrier wave obtained from the oscillator 82.Since the pulse transformer 11 6 is responsive to the high frequency signals, the pulse signal AO carried on the high frequency carrier wave is efficiently transmitted to the secondary winding of the transformer 116 and is rectified by the diodes 118 to 1 24 so that the signal corresponding to the signal AO is produced across the capacitor 1 28. In a similar manner, the pulse signals BO, CO, DO, EO and FO from the OR gates 40, 42, 44, 46 and 48, respectively, are efficiently produced from the outputs of the buffer circuits 94, 96, 98, 100 and 102, respectively; When the multi-vibrator 12 produces a low level signal, the AND gates 50 to 60-and AND gate 84 are disabled while the NAND gate 86 is enabled.Accordingly, at the moment when the multi-vibrator 12 produces a low level signal the counter 34 stops counting the pulse and is held at the condition in which the finaily counted number is memorized. Accordingly, the decoder 36 produces a high level from one of the outputs QO to OS and is maintained at such a condition. Such a high level signal from the decoder 36 causes two of the OR gates 38,40,42,44, 46 and 48 to produce a high level signal. For example, when the output Q1 of the decoder 36 produces a high level signal, the OR gates 38 and 48 produce a high level signal. Such high level signals are applied to the buffer circuits 92 and 102. Accordingly, the AND gates 106 and 104 in the buffer circuits 92 and 102 are enabled.In this case, since the NAND gate 86 is enabled, the pulse signal produced from the oscillator 32 is transmitted through the NAND gate 86 and to the AND gate 88 in which the transmitted pulse signal from theoscillator 32 is frequency-modulated by the carrier wave produced from the oscillator 82. The frequency-modulated pulse signal is transmitted through the AND gates 104 and 106 of the buffer circuits 92 and 102 and further to the secondary side of the pulse transformer. Accordingly, in the inverter INV, the transistors T1 and T4 are simultaneously turned on and off by the pulse signal produced from the buffer circuits 92 and 102 for producing a chopped dc current or damping current ID to the induction motor IM.

It is to be noted that the speed detector 6 which has been described as constituted by a tachometer generator can be constituted by a magnetic sensing member provided closely adjacent the sheave SH for detecting the number of passage or ribs of the sheave SH past such magnetic sensing members. The number of passage of the ribs detected corresponds to the speed of rotation of the sheave SH.

Since the control system according to the present invention prevents the cage CG from being undesirably speeded up, the cage can be driven within a reasonable speed even by an unstable power source such as one provided for the emergency use.

When the induction motor IM is a two winding motor, the dc damping can be carried out by the winding which is not being used for the inverter driving.

It is to be noted that the control system according to the present invention can be used for a lift having a compact dc motor for the emergency use.

Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Therefore, unless such changes and modifications depart from the true scope of the present invention, they should be construed as included therein.

Claims (6)

1. A control system for use in a lift having a cage, motor driven by an ac current, a dc current source and an inverter for inverting the dc current into an ac current to be supplied to the motor, said control system comprising a speed detecting means for detecting the speed of the cage, means for generating a first signal when the cage speed reaches a maximum available speed and until the cage speed descreases to a minimum available speed-means for generating a second signal when the cage speed reaches a minimum available speed and until the cage speed increases to the maximum available speed, means responsive to the second signal for actuating said inverter to invert the dc current of the dc current source into the ac current, said inverted ac current driving the motor to increase the speed of the cage, a chopper for chopping the dc current, and means responsive to the first signal for actuating the chopper to convert the dc current into a chopped dc current said chopped dc current being supplied to the motor as a damping current to decrease the speed of the cage.

2. A control system as claimed in Claim 1, wherein the dc current source is a battery.

3. A control system for use in a lift having a cage, said control system comprising a motor adapted to be driven by a three phase ac current for driving the cage, a source of dc current having positive and negative sides, a circuit having a first diode and a first transistor connected in parallel to each other between a first common terminal and the positive side of the dc current source, a second diode and a second transistor connected in parallel to each other between the first common terminal and the negative side of the dc current source, a third diode and a third transistor connected in parallel to each other between a second common terminal and the positive side of the dc current source, a fourth diode and a fourth transistor connected in parallel to each other between the second common terminal and the negative side of the dc current source, a fifth diode and a fifth transistor connected in parallel to each other between a third common terminal and the positive side of the dc current source, and a sixth diode and a sixth transistor connected in parallel to each other between the third common terminal and the negative side of the dc current source, said first, second and third common terminals being connected to the motor, a speed detecting means for detecting the speed of the cage, means for generating a first signal when the cage speed reaches a maximum available speed and until the cage speed decreases to a minimum available speed, means for generating a second signal when the cage speed reaches the minimum available speed and until the cage speed increases to the maximum available speed, control means connected to the respective bases of the first, second, third, fourth, fifth and sixth transistors in the circuit and also to said means for generating the first signal and said means for generating the second signal, said control means, upon receipt of the second signal, sequentially causing the first to sixth transistors to conduct in a predetermined order to invert the dc current into three phase ac current, said three phase ac current being supplied from the first, second and third common terminals to the motor for driving the cage, said control means, upon receipt of the first signal, intermittently causing two of the odd or even numbered transistors to conduct for supplying chopped dc current to the motor for damping the cage.

4. A control system as claimed in Claim 3 further comprising a source of three phase ac current, a normally closed switch means connected between the source of three phase ac current and the motor, a normally opened switch means connected between the motor and the first, second and third common terminals, a relay for simultaneously operating the normally closed switch means and the normally opened switch means, and an accident detecting means coupled to the relay, said accident detecting means, upon detection of accident in the source of ac current, opening the normally closed switch means and closing the normally opened switch means.

5. A control system as claimed in Claim 3 wherein said predetermined order in which the first to sixth transistors are sequentially brought in a conductive state is first, sixth, third, second, fifth and fourth.

6. A control system substantially as herebefore described with referen.ce to and as illustrated in the accompanying drawings.