GB2030332A - Data Processing System Having a Reading and Recording Magnetic Unit - Google Patents

Abstract

In a data processing system a programmed controller 104 for a peripheral unit controls the transfer of data both in the read mode and in the write mode between a magnetic record SM and a data source SD which includes central processor CPU 100 and a system store 101. When the controller 104 is carrying out a read transfer it is commanded in correspondence to each recording position reached on the record SM and carries out sequential reading of the information, decoding of it and storage in internal registers. When the stored information makes up a word, the controller performs a direct memory access operation to the system store 101 independently of the CPU in order to transfer the read word in parallel to the store from where it may be accessed by the CPU. Conversely, when a record transfer is performed the controller has access to the system store 101 independently of the CPU, stores the word read and then records it serially on the record according to a predetermined coding. The controller comprises a program store R0M. The read and write programs take place independently of the CPU which speeds up operation of the controller; there is no need to access CPU programs. <IMAGE>

Description

SPECIFICATION Data Processing System Having a Reading and Recording Magnetic Unit The present invention relates to a data processing system comprising a central unit and a magnetic unit for reading and recording data.

Controllers for peripheral units in which supervision of reading and recording of the data is carried out by the central unit are already known. In these the reading speed depends on the access time to the programs held in the central unit, on the time for decoding and carrying out the instructions and on the degree of compatibility of these operations with other operations of the system. The object of the invention is to speed up the control of the read/record magnetic unit.

According to the present invention there is provided a data processing system comprising a central unit and a plurality of peripheral units including a magnetic unit for reading and recording data serially on a magnetic record, the magnetic unit being arranged to transfer data under the control of a peripheral controller between the magnetic record and storage means associated with the central unit, the central unit being arranged to provide command signals for the recording and/or reading of the data in order to command the peripheral controller, the controller including a program store which contains a program governing the magnetic unit, and processing means which are conditional upon the command signals and are controlled in correspondence to each recording position for carrying out the program in order to govern the recording and reading independently of the central unit.

The invention will be described in more detail, by way of example, with reference to the accompanying drawings, wherein: Fig. 1 shows the general layout of the controller having various devices for decoding instructions; Fig. 2 (comprising Figs. 2a and 2b) shows the general electrical layout of one preferred embodiment of the controller; Fig. 3 shows the time sequencing relating to the execution of the program contained in the store; Fig. 4 shows the time sequencing relating to the main signals which are concerned in reading the magnetic record; Fig. 5 shows other signals of which use is made during reading; Fig. 6 is a flow chart of the succession of main logic operations performed during reading; Fig. 7 is a flow chart of the succession of main logic operations performed during writing; and Fig. 8 shows the general layout of a system which includes the controller.

The block diagram shown in Fig. 8 includes a data source SD which is made up for example by a data processing system having a central processing unit CPU 100 connected to a systems store 101.

The system also includes some peripheral units such as a keyboard 102, an output unit (printer) 103 and, in the example illustrated, two units 105 for magnetic reading and recording which are governed by corresponding peripheral controllers 104. The number of units 105 has been kept to two in order to simplify the drawing, but any number can be used and this only depends on the power and speed of processing of CPU 100. The block diagram of one controller 104 is given in detail in Figs. 1, 2a and 2b.

It should be explained that the buses BS, BCO (which are shown in Fig. 8 as a single line) which connect the controllers 104 and the other peripheral units with the CPU 100 actually represent one bus BS for the exchange of data and one bus BCO for the exchange of control signals between the block SD and the peripheral units.

The reading and recording unit 105 employs a magnetic record SM, which can be a magnetic tape, a magnetic card or a magnetic disc, on which the data is recorded bit-seriaily. In particular, the magnetic record SM is advantageously a small disc (diameter 60 mm) which is capable of holding 8K bytes which are recorded sequentially following a spiral path which runs from the periphery to the centre of the disc, substantially as described in our French patent Application No. 7,805,325, (U.K.

8376/78).

The peripheral controller 104 is shown in Fig. 1 and comprises a program store ROM, a group of logic circuits LC for control and which also includes a program counter PC1-3, which addresses the store ROM by means of address bus AB. An instruction bus FO-N, to which a plurality of buses FD1, FD2 ... FDN are connected, commands decoding devices D1-DN which are referred to below as decoders. The group of logic circuits LC is connected to the data source SD by means of the system data bus BS and control bus BCO and to read/write amplifier circuits AP by means of two buses BL and BP. Buses BL and BP carry respectively the command signals generated by the logic circuits LC and the read and write logic signals from and to the circuits AP.The circuits AP are connected in turn to the magnetic record SM by means of the command bus BM.

Depending on the type of instruction which is present on bus FO-N, a signal FN, depending on its logic level, enables or disenables decoder D1 to decode a group of further signals FD1 originating from the same bus F0-N; in the positive case at least one enabling signal E2-EN is produced for the decoders D2-DN following it down the line.Consequently, corresponding to a first type of instruction, one or several of the decoders D1-DN are enabled to decode the corresponding group of signals FD1-FDN and to establish the corresponding command signals K1-KN. Both the instruction bus FO N and the decoded signals K1 -KN are connected directly to the input of the group of control logic circuits LC, as a result of which these circuits are commanded both by commands K1-KN provided by the decoders Dl-KN which have been activated, and by the signals FO--N not used by the decoders Dl -KN. In the case of a second type of instruction on the instruction bus FO-N, the signal FN prevents operation of the decoders Dl-KN and consequently the circuits LC are commanded directly and exclusively by the signals FO-FN.

A preferred embodiment of the controller will now be described in detail, with reference to Fig. 2, in which for the sake of clarity the number of the decoders Di-DN has been reduced to two, i.e.

decoders Dl and D2. The remaining devices shown in Fig. 2 (which taken together constitute the block LC in Fig. 1) are as follows: Buses FO-3, FO-5, F1---3, 6 carry inputs to various devices of the controller, the signals of which originate from the instruction bus FO-7: a multiplexer Ml which is adapted to selectively connect signals from the bus COND (indicating particular conditions) to its output SKIP: a counter C2, connected to the program counter by means of bus FCO-3; a multiplexer M2 which is adapted to selectively connect buses BA, BB, FO-3, BC to a counter C1 by means of a bus BMC; a read-write store RAM which has an input from bus FO-3 and from a bus BCR originating from the counter C1, which are reserved respectively for the addresses and for the data, and has an output to bus BC; a storage device LH1 which will be referred to as a latch below, which is enabled by a signal COMON to receive data present on bus BCR; a multiplexer M3 which is adapted to selectively connect bus BC or system bus BS to a data register RD1 by way of a bus MO-3; a second data register RD2, which together with the register RD1 has the task of storing groups of signals to be transmitted to or originating from the data source SD; a second latch LH2 which is enabled by a signal OUDAN to receive data present on buses BA and BB; a logic circuit 1 which generates timing signals and commands a wait or a jump of an instruction in the execution of the program; a logic circuit 2 which controls the program counter in order to carry out a jump in the program upon a predetermined instruction, and to generate a reading signal for the peripheral unit; a logic circuit 3 containing the reading and writing logic elements; a logic circuit 4 which generates control signals for interchange of data between the controller and the data source; and a logic circuit 5 which is adapted to control the two data registers RD1 and RD2 and the multiplexer M3.

The signals indicated in the block diagram as F1, F2, F3, F7 all belong to the address bus FO-7.

The letter "V" indicates a constant and positive voltage level, whilst signal REP represents a general reset signal for the system.

The logic operation of the two decoders controlled by the instructions generated by the ROM, and the functions commanded by the command signals generated by the decoders in the logic circuits can be clearly seen from the three tables which follow. It will be noticed that a logic level "1" of signal F7 enables the decoder Dl and this in its turn activates the enabling signal CO 1 SN (E2 of Fig. 1 ) for the decoder D2, in the presence of the configuration 010 of the signals F4-6 . When a signal SO-7 directly concerns a logic circuit, this is indicated in the appropriate column and the signal is underlined; the third column shows the decoded signals which are activated.

Table 1 (D1 and D2 enabled) Devices Decoder commanded signal Signal F7F6F5F4F3F2F1FO directly activated task 1 0 1 0 1 0 1 0/1 block 3 COMSN read/write control 1 0 1 0 0 1 1 0/1 C1 COM3N choice U/D on C1 1 1 0001 0 lNR4N initiate interruption for SD 1010110 0 COMGN clear RD 1 0 1 0 0 0 0 0 COMON load C1 in LH 1 0 1 0 1 0 00 DMR4A initiate request DMA and SD 1 1 001 0 0 COM2N enable int. from AP Table 2 (D1 enabled and D2 disenabled) Devices Decoder commanded signal Signal F7F6F5F4F3F2F1FO directly activated task 1 1 1 1 0 0 0 1 block 2 NOPON activate VIAIN for read 1 1 1 1 0 0 1 1 block 2 NOPON stop read 1 1 1 1 0 0 0 0 NOPON no op.

1 0 0 1 X X X X C2 PEREN write 4 bits address jump in C2 1 0 0 0 0 0 0 0 block 5 SHIFT shift RD and load '1' 1 0 0 0 0 0 0 1 block 5 SHIFT shift RD and load '0' 1 0 0 0 0 1 0 1 block 5 SHIFT circular shift RD 101 1 0 0 0 0 M1 SHISN 101 1 0 0 1 0 M1 SKISN 101 1 0 1 0 0 Ml SKISN Table 2 (D1 enabled and D2 disenabled) con Devices Decoder commanded signal Signal F7F6F5F4F3F2F1F0 directly activated task 1 0 1 1 0 1 1 0 M1 SKISN skip (jump one instruction in program) 1 0 1 1 1 0 0 0 Ml SKISN conditioned by the various signals 1 1 1 1 0 0 1 Ml SKISN 1 0 1 1 1 0 1 0 M1 SKISN COND.

101 1 1 1 0 0 Ml SKISN 1 0 1 1 1 1 1 0 M1 SKISN 1 1 0 1 X X X X RAM LODIN load cell XXXX of RAM in D1 1 1 1 1 0 0 0 1 block 2 NOPON activate VIA IN for read 1 1 1 1 0 0 1 1 block 2 NOPON stop read 1 1 1 1 0 0 0 0 NOPON noop 1 0 0 1 X X X X C2 PEREN write 4 bits address jump on C2 1 0 0 0 0 0 0 0 block 5 SHIFT shift RD and load '1' 1 0 0 0 0 0 0 0 block 5 SHIFT shift RD and load'0' 1 0 0 0 0 1 0 1 block 5 SHIFT circular shift RD 101 1 0 0 0 0 Ml SKISN 1 0 1 1 0 0 1 0 M1 SKISN 1 1 1 0 1 0 0 Ml SKISN 1 0 1 1 0 1 1 0 M1 SKISN # skip (jump one instruction in 1 0 1 1 1 0 0 0 M1 SKISN # the program) conditioned by 1 0 1 1 1 0 0 1 M1 SKISN # the various signals 101 1 1 0 1 0 Ml SKISN 1 0 1 1 1 1 0 0 M1 SKISN 1 0 1 1 1 1 1 0 M1 SKISN 1 1 0 1 X X X X RAM LODIN load cell XXXXof RAM in D1 1 1 1 OXXXX RAM WROON loadl C1 in cell XXXX of RAM 1 1 0 0 0 0 0 0 WAISN generate wait state Table 3 (D1 and D2 disenabled) Devices Decoder Commanded Signal Signal F7F6F5F4F3F2F1F0 Directly Activated Task 0 1 X X X X X X PC write 6 bits address jump in PC2-PC3 0 0 1 0 X X X X C1-M2 load cell XXXX 0 0 0 1 1 1 1 1 C1-M2 of Ram in Cl load D1 and C1 From Tables 1 to 3, it will be clear to those skilled in the art that a simplified example of the carrying out of the concept described above with reference to Fig. 1 has been provided. Obviously those skilled in the art will be able to design a whole range of ways of carrying out the basic concept which has been described, whilst the example which is given in Fig. 2 and in Tables 1 to 3 could of course also be adapted to other logic circuits included in other types of programmable controllers.

For simplicity and clarity of description, the operation of some of the more significant devices in Figs. 2a and 2b will now be described.

The store RAM, by means of the multiplexer M2 and counter C1, is able to selectively store information recorded in one of the two registers RD1 and RD2 or which are read directly from the ROM via bus FO-3, or it may also add on to data already stored. The latch LH 1 is enabled by means of the command signal COMON to memorise instructions present on bus BCR which are suitable for commanding the amplifier circuits AP.

Data register RD1 has its input M03 selected by a multiplexer M3 and can selectively register the most significant part of the information present on the system bus BS or on the bus BC originating from the RAM. The register R2 is only able to load directly the less significant part of the information present on bus BS. Signal OUDAN enables the latch LH2 to store information present on buses BA and BB when this is to be transmitted to the data source SD.

The program counter for the ROM is divided into three parts PC1, PEZ and PC3. The first part PC1 carries 4 less significant bits of the address; they can be forced to a predetermined value as a result of an instruction in the program. The parts PC2 and PC3 analogously carry the 6 more significant bits of the address FO-5, which can be programmed directly by an instruction in the program.

The logic circuit 1 employs a signal having a frequency of 2MHz from a quartz crystal oscillator 1 1 and generates timing signals CKCON, TEOON and a signal WAITA which orders a waiting state in the controller. Input of the signal SKIPN blocks CKCON and so determines a skip of one instruction in the carrying out of the program. Signal WAITA blocks the program controller PCI-3 when it is set by the signal WAISN and unblocks it when it is reset by one of the two signals OUDAN and TAENN which will be referred to again below. Signals BLOCN and STEPN originate from the data source of the system, and have the purpose of blocking the timing signal TEOON.

Signal VIAIN which is provided by the logic circuit 2 and which is commanded by signals NOPON, FO, F1, directly controls the amplifier circuits AP in order to cause the magnetic record SM to be read.

Signal SALTA generated by logic circuit 6 is adapted to reset the part PC1 of the program counter (containing the 4 less significant bits of the current program address) and to consequently force a jump in the carrying out of the program to a predetermined memory location and dependent upon the value of the 6 more significant bits of the current address, contained in PC2 and PC3.

Signals COM2 N AND CKINO control a resettable flip-flop 7, respectively enable and disenable the logic circuit 6 to be commanded by the signal GAINA. Signal GAINA is a synchronising signal which originates directly from circuits AP and which consequently indicates the validity of the signal LETTA read from the record SM.

A more detailed description of the operation of the circuits 6 and 7 will now be provided with reference to the timing schedule in Fig. 4.

Logic circuit 3 generates the write signal WR and read signal DISRO using a magnetic head (not shown) included in the magnetic recording unit 105. win particular signal WR is generated by a flipflop 9 (commanded by COM5N) and directly controls the circuits AP which regulate the operation of the magnetic head.

Signal LETTA originating from the magnetic head by way of circuit AP simply indicates the logic level of the information magnetically recorded on the magnetic record SM. NRZ signals are used, a '1' bit being indicated by a transition within the cycle (see Fig. 5). A flip-flop 10 memorises, at the point in time indicated by GAINA, the present logic level of signal LETTA and controls an exclusive OR- circuit 8 (signal ILEEN). The flip-flop 9, in the read mode predisposes the exclusive-OR circuit 8 for successive reading (signal BISCO) as a result of an order from the program (signal COM5N). The result is that the signal DISRO from exclusive-OR circuit 8 reproduces all significant transitions of the magnetic flux, as will be explained with reference to Figs. 5 and 6.Logic circuit 4 is designed to generate, with suitable timing, the request signal DMR4N for direct access (so called DMA) to the store of the CPU included in the data source SD. This operation is commanded by signal DMR4A. The remainder of the signals which enter logic circuit 4 are signals which originate from the data source SD via control bus BCO and have the purpose of selecting the controller either simply upon the initiative of the data source SD (signals MEMWI and MEMRI and CSA) or for acknowledging a request for access to the DMA (signals DMA4N, lOWOl, IORO1). Depending on whether the data originate from or are being transmitted to the data source SD, either signal OUDAN is activated by circuit SO, or signal TAENN is activated by circuit S1.

Circuit 5 controls the data registers RD1, RD2 and multiplexer M3: the latter commands the loading operation of the register RD1 from the system bus BS (signal TAENN) or from the bus BC (signal LODIN) or the shift operation (shift SHIFT).

In order to simplify the description, details of operation of the logic parts and the flip-flops included in circuits 1 to 5 have been purposely omitted, since these details will be readily understood from the diagram by any person skilled in the art.

In Fig. 2 it will be seen how all the logic circuits are timed by means of signals comprised within the cycle of the timing signal CKCON. Signal TEOON, which times the program counter PC1-3, is still this same signal CKCON but, as can be seen, it is not conditional upon signal SKIPN for operational reasons. As a result of this it follows that every particular instruction or logical operation in the controller is carried out within one period of the timing signal CKCON, the various logic leading edges and levels taking advantage of this.

In particular the signals shown in Fig. 3 represent the timing of the addressing operation of the ROM (bus AB), for reading the instructions from the ROM (bus F07, and the timing of the logic circuts commanded by the commands generated by the decoder D2. It will be seen how, in one period, the leading edge of TEOON provides an increment to counter PC1-3 and provides for addressing the present instruction from the ROM. This in its turn presents the relative instruction to the bus FO-7.

The following trough of CKCON then enables the decoder D2 for decoding which consequently leads to actuation of the commands in the same cycle of the timing signal CKCON.

Figs. 4-7 show timing of signals and flow diagrams relating to writing and reading operations of information coded according to code DF. Code DF comprises cells of information defined by clock signals which may or may not contain a transition depending on the logic level of the information. It follows that LETTA or WR signals represent respectively the logic level of information signals read from or written on to the magnetic carrier SM, and have a first transition corresponding to the start of an information cell (clock transition) and a second transition inside the cell only in the case when a logic '1' is present. The choice of such a code is obviously only one possible example and other codes can be used.

In considering Fig. 4, the signals TEOON, CKCON, AB, Fro~7 and D2 are as in Fig. 3 and represent the timing of signals belonging to the logic circuits 6 and 7 and relating to one reading operation of information from the magnetic carrier SM.

A reading operation always starts with a read command VIAIN which is delivered by the controller to the circuits AP. immediately following command COM2N activates the signal ABINO which in its turn enables the circuit 6 to be commanded by the signal GAINA. Corresponding to the times 1 C and 2C, signal LETTA undergoes transitions which represent clock transitions; these are the start and the finish of one cell of information. Signal GAINA remains activated for the duration of the cell, and its leading edge activates signal CONDO. CONDO in its turn activates signal SALTA. The same logic circuit 6 then provides for resetting of these two signals. Signal SALTA clears as was said when Fig. 2 was being described, the less significant part PC1 of the program counter PCl-3, so that a certain address is imposed on the address bus AB.This address in this particular type of application contains the address to jump to the initial instruction of the reading program.

It should be made clear that the program jump commanded directly by the external signal GAINA is completely general. Actually, if the OR of other external signals is fed into the input of the circuit 6 with the signal GAINA, then each one of these external signals is able to command independently a jump within the program which was being carried out while waiting for such an external signal. The jump commanded by each such external signal consequently causes the carrying out of a sequence of instructions in response to the signal itself.

It should be stressed that the same signal GAINA, also commands the logic circuit 3 of Fig. 2, in addition to the carrying out of the reading program. Circuit 3 is in a position, as has been explained, by signal by means of signal DISRO, if inside the read cell a further transmission of signal LETTA occurs (presence of a logic '1') or if the signal LETTA has a constant level (present of a logic '0').

The relationships between the command for the reading program and the logic circuit 3 will now be explained in detail with reference to the timing diagram shown in Fig. 5 and the flow diagram given in Fig. 6.

Signal FLEEN in Fig. 5 shows simply the storage (inverted) of signal LETTA at the instant indicated by signal GAINA. Signal DISRO represents the exclusive-OR of the two signals FLEEN and BISCO and consequently switches at each transition of one of these two signals. The read program, commanded by signal GAINA, examines the level of signal DISRO in accordance to the points indicated with the letter "T"; when the signal DISRO is at the low logic state, it responds to it at the high logic level. If signal DISRO is actually at level '0', the program generates command COM5N; COM5N in its turn switches signal BISCO of which DISRO is a function. It will be clear at this point that the logic level of signal DISRO, examined according to the above points, correctly interprets the logic levels of the information signals recorded on the magnetic carrier.

The logic steps of all the operations commanded by the program during a reading operation of the magnetic carrier will now be systematically gone through with reference to the diagram in Fig. 6.

A reading operation always starts with the initiation of a command VIAIN directed to the circuits AP and of signal COM2N, to enable the controller to be commanded by a signal GAINA (blocks 21 and 22). From this time on, counting by a suitably initialized counter (block 23) starts. If the signal GAINA does not arrive within the reset time of the counter, signal VIAIN is reset and the read operation is stopped. In this case interruption by signal GAINA is also disabled (blocks 24 and 25). If, on the other hand, the signal GAINA does arrive at a suitable time, signal SALTA is actuated, which forces a jump to predetermined addresses in the program, counter. In this case also, interruption by the signal GAINA is disabled (blocks 24 and 26), in order to eliminate unwanted commands and commands generated by noise on the record.The instructions corresponding to the above said addresses command (block 33) a second jump to the section of the program which verifies the logic level of the information read, i.e. the logic level of signal DISRO (block 27). If signal DISRO is 'O' a shift is commanded and an 'O' is loaded in registers Rod1~2 and signal COMSN is generated in order to bring back signal DISRO to the value '1' (blocks 28, 29). If, on the other hand, signal DISRO has a logic level of '1', the command is simply given for the shift and a '1' is loaded into registers RD1--2. This cycle, starting from activation of the enabling command (block 22) is repeated up to the point where registers RD1--2 are completeyfilled (a test carried out by block 31).When this does happen, transfer in parallel of the content of registers RD1--2 into system bus BS is commanded.

From bus BS the data will be transferred to the CPU in the data source, by means of direct access to the store (DMA). The read cycle will then be taken up again starting from block 22.

The flow diagram in Fig. 7 shows a program for writing on the magnetic support. The program starts with a command for access to the store of the CPU (DMA) in order to load the data into registers Rid1~2 (blocks 34 and 42). Signal COM5N is activated in order to command a first transition of the writing signal (block 35). This transition represents the start of a cell of information (clock). After a waiting period (block 36) which is necessary in order to suitably time the writing of the information, the logic level of the less significant bits present in registers RD1-2 (block 37) is examined and, depending on this level, a second transition of the writing signal (block 38) is or is not commanded.

After a further period of waiting (block 39) the program commands a shift in registers Rid1~2 in order to displace the bits following the one which was examined (block 40) into the position for examination.

This cycle starting from the generation of the clock (block 35) is repeated until all the bits loaded in registers Rod1~2 have been examined (test carried out by block 41). When this examination has been completed, the cycle is taken up again from block 34 with a new request DMA to the central processing unit and the related loading of registers RD1--2.

From the description provided it will be clearly seen how a programmable controller of the type described, which does not have an excessively complicated construction, is in a position to carry out all the control operations for a peripheral magnetic unit in a particularly rapid and efficaceous manner.

Claims (16)

Claims

1. A data processing system comprising a central unit and a plurality of peripheral units including a magnetic unit for reading and recording data serially on a magnetic record, the magnetic unit being arranged to transfer data under the control of a peripheral controller between the magnetic record and storage means associated with the central unit, the central unit being arranged to provide command signals for the recording and/or reading of the data in order to command the peripheral controller, the controller including a program store which contains a program governing the magnetic unit, and processing means which are conditional upon the command signals and are controlled in correspondence to each recording position for carrying out the program, in order to govern the recording and reading independently of the central unit.

2. A system according to claim 1, wherein the controller further includes a register which is adapted to store at least one word in turn for the transfer when carrying out predetermined instructions for transfer.

3. A system according to claim 1 or 2, wherein the program is addressed by means of addressing means into which the processing means for a predetermined address corresponding to each recorded position of the magnetic record.

4. A system according to claim 3, wherein the addressing means comprise a program counter into which the processing means impose an address consisting of a collection of predetermined addresses which correspond to the initial instruction from a reading program in response to a validity signal provided by a circuit for actuating the magnetic unit.

5. A system according to claim 4, wherein the actuating circuit generates, in the reading mode, coded logic signals which correspond to the magnetic information read from the record, the processing means including means for memorising the logic signals corresponding to an item of magnetic information at a time indicated by the validity signal.

6. A system according to claim 5, insofar as dependent on claim 2, wherein the reading program includes a series of instructions which can be carried out by the processing means in order to examine the memory means and record a corresponding piece of binary information in the register.

7. A system according to claim 6, wherein the series of instructions includes at least one instruction which can be carried out by the processing means in order to generate, as a function of the memorized binary information, a signal for predeposing the memory means to memorize the logic signals corresponding to the next piece of information read, so that the memory means are conditioned jointly by the logic signals, the validity signal and the predeposing signal.

8. A system according to claim 6 or 7, comprising means for counting the number of bits of information memorized in the register, which is activated in response to an instruction from the program and causes the carrying out of one of the transfer instructions in response to a predetermined number counted from the instructions.

9. A system according to any one of claims 4 to 8, wherein the reading program includes instructions for activating a second counter for counting the waiting time for the validity signal and for disabling the validity signal from controlling the processing means beyond a predetermined waiting time.

10. A system according to any of Claims 4 to 9, which further includes a timing circuit for generating a timing signal for the instructions from the programs read from the program store, the program store being permanently enabled to govern the address instructions from the program counter, the counter being timed by a first semi-period in the timing signal and the processing means being timed using signals derived from the second semi-period of the timing signal, so that the increment from the program counter, the reading of the instructions addressed by the latter and the carrying out of the instructions take place always during a single period of the timing signals.

1 A system according to claim 2 or any subsequent claim insofar as dependent on claim 2, wherein a writing program comprises a second series of instructions which can be carried out by the processing means in order to examine the binary information contained in the register following the transfer from the central unit, the processing means including timing means and recording means which are controlled jointly by the timing means and the second instructions in order to generate coded signals which are representative of the binary information examined and for registering it on the carrier.

12. A system according to claim 1 wherein the second series of instructions includes an instruction which can be carried out in order to control the recording means to generate separation signals which are interspaced with the coded signals.

13. A system according to claim 1 1 or 12, comprising means for counting the number of bits of binary information recorded and which can be actuated in response to a further instruction of the second series in order to force the carrying out of a predetermined one of the transfer instructions in response to a determined number counted by the counter.

14. A system according to any of the preceding claims, wherein the processing means include means for reading the program contained in the store in order to generate signals which represent instructions in the program and a hierarchy of a decoding means for generating control signals for the processing means, the hierarchy of decoding means including a main decoding means which is selectively enabled by one of the signals representing instructions to generate a first group of the plurality of control signals and at least one secondary decoding means, which can be selectively enabled by control signals forming part of the first group to generate respectively further groups of control signals, the signals representing the instructions which are not being used by the decoding means directly commanding the logic circuits.

1 5. A system according to claim 14, in which the processing means further include a plurality of registers and a second store for storing information and data, and wherein the said signals which are not used comprise addresses or information and that the said addresses selectively command a program jump in the first store, addressing of the information in the second store and comprising means for storing the information contained in the instructions in the registers.

16. A data processing system substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.