GB2029171A - Reading magnetic records - Google Patents

Abstract

The boundaries of each bit and the clock information are denoted on a magnetic record by regular boundary transition of, e.g. N-N polarity. The binary values are denoted by the phase positions of interior transitions int, e.g. S-S, relative to the boundaries. The interior transitions have phases of for example 120 DEG or 240 DEG relative to the boundary transitions. To decode the record, a counter measures the time interval between the boundary transitions Bnd of a bit. A further counter measures the time interval between the interior transition of the bit and one of its boundary transitions. A comparator compares a count corresponding to 180 DEG of phase with the count corresponding to 120 DEG or 240 DEG of phase to determine whether the interior transition has a phase of more or less than 180 DEG and thus the binary value of that bit. <IMAGE>

Description

SPECIFICATION Reading magnetic records The present invention relates to arrangements for extracting binary data and clock information from a magnetic record and also to a peak detector for use in such arrangements.

According to one aspect of the present invention, there is provided apparatus for extracting binary data and clock information from a record in which the boundaries of binary bits representing that data and information are represented by first magnetic transitions and the binary values of the bits are represented by second magnetic transitions (opposite to the first), which have selected ones of two positions relative to the boundaries according to the values represented thereby, the apparatus comprising record reading means for producing electrical signals in response to the transitions as the record moves relative thereto, means responsive to these electrical signals to distinguish in them between events of first and second significances cording to whether they represent bit boundaries or the values of the bits respectively, first means for producing for each bit a representation of the time interval between the successive events of the first significance, representing the boundaries of that bit, second means for producing for each bit a representation of the time interval between its event of the second significance and one of its events of the first significance, means for comparing the said representations for each bit and for indicating whether the said time interval between its event of the second significance and one of its events of the first significance is less than or greater than a predetermined proportion of the time interval between the said successive events of the first significance of that bit, which predetermined proportion is intermediate the proportions of that time interval at which the events of the second significance are selectively produced, and means for samping the indication produced by the comparing means at the time of production of each event of the first significance, thereby to extract the data.

According to an embodiment of the present invention the responsive means includes a pair of peak detectors for producing signals representing the events of the first and second significances respectively, each peak detector comprising a comparator, a store for storing the value of the output of the comparator, the comparator being arranged to compare the value of the signal with the value stored in the store, and means for reducing the value stored in the store at a rate proportional to that value.

For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which:~ Figure 1 is a schematic diagram of a magnetic record together with waveform diagrams for explaining the manner of decoding data on the record; Figure 2 is a block diagram of a decoding arrangement embodying the present invention; Figure 3A to C respectively show the circuit of a peak detector of the arrangement of Fig.

2, waveforms explaining the operation of the detector, and a modification of the detector.

Figure 4 is a block diagram of polarity and signal processing circuits of Fig. 2, Figure 5 shows a part of an alternative decoding arrangement, Figure 6 shows alternative manners of processing read head outputs, Figure 7 is a circuit diagram of a peak detector in accordance with the invention, and Figure 8 is a waveform diagram illustrating the operation of the peak detector of Fig. 7.

Referring to Fig. 1, the present exemplary decoding arrangement is for use with a magnetic record 11, in the form of a ticket for example, carrying two tracks of binary data 12, 13 symmetrically arranged about the longitudinal axis, AA, of the ticket.

In this example, for ease of explanation of the invention the two tracks are records of a common pattern of magnetising current, shown graphically by waveform 14. This waveform also ideally corresponds to the resulting pattern of the instantaneous flux set up, at the time of reading, in the read head as the record passes the head. If two tracks are provided in this manner a single read head can extract the information recorded on the ticket irrespective of which end of the ticket is fed to it first.

At the time of writing, a conventional ring head was energised by a bipolar magnetising current in accordance with the waveform 14 comprising a series of bit intervals 15 of equal length.

Each bit interval is divided into two parts; during the first part the current in the ring head is contant and of one polarity + I, and is reversed - I in the second part. Bit significance is conveyed through the binary phase modulation of the instant Int of the interior reversal of the current I (and thus of flux 0) relative to the boundaries Bnd. The magnitude I of the current is chosen to ensure magnetic saturation of the record. The preferred phase values are 120 and 240 degrees giving a duty ratio of 1/3 and 2/3 respectively. The boundaries Bnd provide the reference for the phase angles, and represent the timing of each bit, i.e. the boundaries Bnd carry clock information, even though the mean reading speed may vary.

It will be seen that, for any data sequence, there are always two flux reversals Bnd and Int per bit. The magnetising current according with pattern 14 produces magnetic remanance patterns, as shown in the tracks 12 and 13, in which the direction of the arrow heads indicates the sense of the local magnetisation, and the flux reversals Bnd and Int are respectively represented by boundary transition N-N and interior transitions S-S in the tracks.

In order to read the data recorded on the ticket 11, one track e.g. 13 on the ticket is moved past a read head 16 Fig. 2 of conventional ring design. Magnetic flux then circulates in the head which reproduces the original pattern 14, but with the original abrupt transitions having now become diffuse. For data recovery, the pertinent parts of the waveform are those where the value of the instantaneous circulating flux passed through zero, since their timing is least sensitive to variations in coupling efficiency between medium and head.

In practice, these nearly coincide with points of inflexion in the waveform, that is the points of maximum gradient. The head produces a voltage which is the time differential of the field pattern, in the track, each transition N-N, S-S producing a voltage pulse, the polarity of which depends both on whether the field transition is N-N or S-S, i.e.

whether the field transition represents a bit boundary Bnd, or an interior transition Int, and on the direction of movement of the ticket. Furthermore, the peak of each pulse occurs at an inflexion of the read head flux; those instants which are favourable in the recovery of their relative timing.

Taking the ticket shown in Fig. 1, if the track 13 is moved past the head 16 in Fig. 2 in the standard pass direction, i.e. "START" engages the head first, a waveform similar to that shown at (a) in Fig. 1 (continued) is produced, in which bit boundaries Bnd are represented by positive pulses and negative pulses represent interior transitions. The correspondence in time between the remanence patterns on the track 13 and Figs. 1 a, c, e is illustrated by aligning lines 0 to T with lines 01 toT1.

If the ticket is turned round so that track 12 passes the same read head 16 in the standard pass direction i.e. "END" engages the head first, the waveform (b) is produced.

The correspondence in time between the remanance pattern in track 12 and Figs. 1 b, d and fis illustrated by aligning lines U, V, W, X, Y and Z. The bit boundaries Bnd still produce positive pulses and the interior transitions Int still produce negative pulses.

If track 12 or 13 was moved past the read head 16 in the direction opposite to the standard pass direction, the polarities of the waveforms (a) and (b) would be inverted, i.e.

bit boundaries Bnd would be represented by negative pulses and interior transitions by positive pulses.

The decoding arrangement of Figs. 2 to 4 is based upon direct sensing of the peaks of the read head voltage, and is arranged to extract the data and the clock information from the ticket 11, irrespective of the direction of movement of the ticket past the read head 16 and irrespective of whether track 12 or 13 passes the read head. The decoding arrangement is also arranged to extract that data and clock information even though there may be variations in the speed of movement of the ticket past the read head, however there must not be an appreciable variation of speed within the duration of a single bit.

In the arrangement shown in Fig. 2, the read head 16 feeds a push-pull amplifier 17 whose antiphase outputs are applied to positive and negative peak detectors 21, 22 which each produce negative pulses, shown at (a') and (a") respectively in Fig. 1, in response to the peaks of the positive and negative pulses produced by the head. One form of the peak detectors 21 is shown in Fig.

3A. These pulses are fed to a polarity processor 23 (shown in Fig. 4) which also receives information from a pass direction sensor 24 regarding the direction of movement of the ticket 11 past the head 16. (In most applications, here would be no need for sensing direction, as the required information would be derived from the drive commands to the ticket transport mechanism (e.g. an extra pair of contacts on a motor reversing relay)). The polarity processor 23 uses the pass direction information to produce positive boundary pulses representing the bit boundaries Bnd on a first output 231 and positive interior pulses representing the interior transitions Int on a second output 232 irrespective of whether the corresponding pulses produced by the head 16 were positive or negative.A signal processor 25 (shown in Fig. 4) extracts the clock information and the data from the boundary pulses and the interior pulses fed to it.

The peak detectors 21 and 22 will now be described with reference to Figs. 3A to C.

When the information on the track 12 or 13 on the ticket 11 is read back dynamically using the conventional 'ring' head 16, successive magnetic transitions along the record become differentiated to give pulses of alternating polarity. So long as it is possible to identify the peaks and their timing, the bit significance is recoverable. If the reading speed is increased, pulses become proportionately greater in amplitude but their time scale becomes proportionately compressed. Thus changes in speed produce changes in pulse amplitude and length. If the peaks of the pulses are to be detected by comparison with a threshold level, that level must for all conditions be set above the noise level yet be small enough to detect minimum height peaks.

Difficulties arise in simultaneously meeting both these requirements when the reading speed may fall anywhere within a wide range.

The circuit of Fig. 3 avoids this problem by employing a threshold whose value remains the same proportion of the previous peak for a range of variation of reading speed.

The circuit shown in Fig. 3A is for the detection of positive peaks.

The incoming pulse is applied to the noninverting input terminal, p, of high gain differential amplifier, A. The voltage across capacitor C1 is applied to the inverting input, q, and serves as the detection threshold. So long as the input at p has risen above that at q, D1 conducts and allows A to charge C1 so as to follow the rise. Resistor R1 allows a positive swing of the output of A which exceeds the actual voltage on C1.

When, however, the voltage at p falls to below q (that is, after a peak has been passed), the output of A falls and reverse biases D1, making it non-conductive and therefore leaving C1 initially holding the peak voltage experienced. During the time that the voltage from A is rising, capacitor C2 acquires charge via diode D2 with negligible effect on the voltage across the output terminals. As the input peak is passed and the voltage from A falls, the current through C2 reverses and D2 becomes non-conductive. Initially, the drop in voltage is communicated by C2 to form a negative-going edge at the output followed by a fairly rapid decay as the charge leaks away via R2. Thus, the output waveform is a sequence of sharp negative-going pulses which are approximately coincident with the peaks in the input voltage waveform.

After the occurrence of a peak, charge is able to leak away from C1 through NLR sufficiently to ensure that, at the time of the next peak, A will once again receive a positive differential input. The use of a leak of fixed resistance is long-established practice but here, the NLR exhibits nominally square law conduction; that is the current flowing is directly proportional to the voltage applied.

Such a two-terminal device may be contrived by strapping the gate of an enhancement-mode insulated gate field effect transistor (e.g. Siliconix Type MEM 511C) to its drain. Alternatively, a combination of resistors and diodes such as is shown in Fig. 3C may be used to approximate the desired characteristic. As the applied voltage rises above a minimum value, first D3 and later D4 conduct and short circuit their associated resistor, so increasing the incremental conductance.

When the capacitor C1 is discharged via a constant value resistance, the rate of loss of charge is proportional to the voltage and consequently to the instantaneous charge. The decay is therefore exponential with time.

However, when the rate of loss of charge is instead proportional to the square of the charge, then integration shows that the decay follows a hyperbolic inverse law. Thus, if O is the charge at time T, and q is the charge at the variable time t, then t - T = G (1 /q - 1 /0) where G is a constant. The charge will therefore fall from Q to a given fraction xQ in the time interval G(lx - which clearly is inversely proportional to O.

Now, the amplitude of a read head signal and the time scale are inversely related as the reading speed is varied. It follows that, across C1, the proportion of a peak value decayed by the time of the next peak will be insensitive to reading speed.

Of course, any amplitude modulation arising from other than a variation of reading speed will exert an influence on the above proportion, and therefore on the width of the output pulses. Thus, although there is some tolerance to such transfer gain modulation, it is limited in extent. However, the time of the late edge of the output is comparatively unaffected so, within the tolerance, decoding may proceed in the normal way.

Tha polarity and signal processing circuits will now be described with reference to Fig.

4.

The polarity processor is fed with negative pulses from the peak detectors, together with a binary signal from the pass direction sensor 24. A commutator, COM, receives at its inputs CM1 and CM2 negative pulses from 21 and 22 respectively. The binary signal from 24 is applied directly to the input CM3 and, via inverter 41, to the input CM4.

For the standard direction of pass of the ticket 11 under the read head, the pulses received at input CM2 mark the bit boundaries. Bnd, while those at CM1 mark the datadependent interior transitions, Int. Then, for the opposite pass direction, the polarity of the read head output would be reversed, with the result that boundary (clock) pulses would now be received at CM 1 and the interior pulses Int at CM2.

As shown, COM comprises four AND gates G1 to G4 and two OR gates G5, G6 (e.g. TTL Series 7451), and ensures that boundary and interior pulses always appear at their appropriate outputs y and x respectively, whatever reading direction is involved.

Referring to Fig. 1, waveforms (a') and (a") or (b') and (b") show the timing of the trains of boundary and interior pulses received at the two inputs of the signal processor 25 of Fig. 4. Waveform (c) and (d) then represents the inverted output of a bistable B1 of the processor. Waveform (e) or (f) represents the instantaneous contents of counters CT1 and CT2 of Fig. 4. (Strictly, these waveforms should show a 'staircase rise and, for practical frequencies of PG in Fig. 4, this would be reasonably evident.) The occurrence of an interior pulse Int puts the bistable B1 into the set condition, whose output then enables and AND gate G7 and initiates the flow pf pulses from a fast pulse generator, PG, into the counter CT1 (e.g. TTL Series 7493).At the time when a boundary pulse occurs, the contents of the counter CT1 give a measure of the time interval since the instant of the preceding interior pulse. At the same time, the other counter, CT2, gives a measure of the time interval since the instant of the preceding boundary pulse.

A magnitude comparator, MC, (e.g. TTL Series 7485) compares the output of the counter Cil with that of the counter CT2 shifted downward one binary place (so effectively dividing its contents by 2). Therefore, at the time of the boundary pulse, the output of the comparator MC is logic 0 or logic 1 in dependence on whether the second time segment of the bit had occupied more or less than half the bit interval; that is, it extracts the bit significance. An AND gate G8 samples the output of the comparator in response to the boundary pulses and furnishes the data output at output 252.

Following each boundary pulse, after a short interval introduced by delay D, the bistable B1 is reset and the contents of the counters CT1 and 2 are cleared to zero, ready to read the next bit.

The boundary pulses are fed to an output 251 for use as clock pulses.

By comparing a count representing the length of the second time segment of a bit with 3 the count representing the length of the whole bit, the data can be extracted unaffected by variations in the speed of movement of the ticket past the read head (assuming there are no substantial fluctuations within the time of one bit).

The track 12 causes the production of the code 01001 whilst the track 13 causes the production of the code 01101 where the bits have become both complemented and in reverse order. By providing suitable preambles and postambles to the codes recorded in the tracks, the presence at the start of the data stream of either the START or END of the recorded message can be distinguished, and this information used to process the codes and resolve the differences. However this processing is not part of the present invention and so will not be described.

The pass direction sensor 24 is a known device and so will not be described in detail.

Although the polarity and signal processors 23 and 25 have been described in relation to the logical significance of pulses, it will be appreciated that, using state-controlled logic elements, it is possible for the circuits to be respectively sensitive to transitions of one sense or the other: the generation of corresponding physical pulses may not be needed in practice.

Furthermore the processors 23 and 25 have been described in relation to two peak detectors detecting positive and negative pulses which are received at respective inputs. However, alternative methods of processing the read head outputs are possible which are based upon the early recovery or reconstitution of the original write current waveform.

Fig. 6 shows three examples.

In Fig. 6(a), after pre-amplification (61), the read head output is integrated (62) and the flux waveform thereby recovered in analogue form. To improve the restoration of the steady component of the integrator output, the resistive feed back (62 may be made symmetrically non-linear with conductance an increasing function of the voltage sustained (e.g.

silicon carbide, or two oppositely-poled diodes in parallel). From the flux analogue, a hardlimiter/amplifier 63 produces a rectangular waveform conveying the pertinent timing information.

In Fig. 6(b), after pre-amplification (61), the read head output is differentiated 64 to give an analogue of the second derivative of the head flux, going through zero instantaneous amplitude at the points of inflexion. Again a hard-limiter/amplifier 63 produces a corresponding rectangular waveform.

In Fig. 6(c), a rectangular waveform is produced by a circuit whose instantaneous output alternates between two levels as the input passes through positive and negative peaks.

(Such a circuit 65 is shown in Fig. 7.

Referring to Figs. 7 and 8, the peak detector of Fig. 7 is operable to produce a square wave b, the rising and falling edges e of which indicate the positions of the peaks of an input signal p. In Fig. 8, the signal p is shown as having a roughly sine-waveform for the purposes of illustration only; the peaks of other signals would also be detected by the detector as will be described hereinbelow.

An amplifier S is given enough positive feedback via a resistor R5 for it to behave as a Schmitt trigger circuit having hysteresis in the response of its output bto its input a. As shown in Fig. 8(a) the alternative positive and negative voltage levels of the waveform b produced at the output b are respectively above and below the range of variation of the input signal p. As shown in Fig. 8(b), the negative level of b is produced when the level of the signal at the input a is more than the negative boundary level nL of the hysteresis band and the positive level of b is produced when the level of the signal at the input a is more positive than the positive boundary level pL of the hysteresis band.

A comparator comprising an amplifier A compares the input signal p with the voltage q on a capaitor C. The capacitor C is connected to the output b of the Schmitt trigger S by two paths. One path, comprising a diode D1 and a resistor R7, causes the capacitor C to charge when the output b is positive. The other path comprising a diode D3 and a resistor R6, allows the capacitor C to discharge when the output b is negative.

The charging and discharging of the capacitor C is controlled by the output rof the amplifier A, the output rbeing connected to the paths by diodes D2 and D4 and to the input a of the Schmitt trigger via a resistor R3.

The circuit operates in the following manner: A is a high gain amplifier whose output with respect to earth is gain G times the differential input voltage. It presents a high resistance at its inputs and a low incremental resistance at its output. Consider the condition when D1, D2 are short-circuited nd D3, D4 are open.

Let the output in parallel with R7 give a resultant source resistance of R.

If a sinusoid P sin t is applied to p, it can be shown that the voltage at q lags by an angle where tan = RC/(G + 1). For large G and small RC, this constitutes a time lag of one time constant of RC/(G + 1) sec. Again for large G, the current in C is very nearly i=((GC#/(G+ 1)P cos(t~@) and so, as the current in R7 at all times exceeds the crest value, the output of A absorbs the surplus.

Thus, so long as the voltage across C is rising, the current in R7 divides into two small parts flowing in the same sense. Their directions agree with the forward direction of D1, D2, and therefore the postulated short circuits could be removed without effect.

A time interval of RC/(G + 1) after the peak at p has been passed, the current in C has fallen to zero and D1 can no longer conduct.

The negative feedback then ceases, and the output at rresponds to the p input with full open-loop gain. Thus the fall at ris a much magnified version of that of p.

Thus consider the condition where the voltage at p is rising and the voltages at r, a and bare all positive. Diodes D1 and D2 are therefore made conductive via R7 and connect rto capacitor C. At the same time, diodes D3 and 4 are reverse biassed via resistor R6. While the voltage at p is rising, C charges via D1 so that its voltage at qtends to follow p. However, when p starts to fall, the voltage at r(and hence also that at the junction of R7, D1 and 2) falls below q. D1 then becomes cut off, causing C to hold the crest value.

If, now, pcontinues to fall, rwill go negative, causing a to pass through the hysteresis band, thereby triggering S into its alternative state, i.e. b negative. D3 and 4 now become conductive via R6 while, this time, D1 and 2 are reverse biassed. C can now discharge via D3, so letting q catch up with p and thereafter follow it downwards. The return transition in the state of S occurs when p ceases to fall and has risen sufficiently to overcome the hysteresis at a. Local negative feedback around A will help stabilise the equivalent hysteresis band seen at p.

Thus, the exemplary peak detector provides a binary output whose transitions occur just after a significant peak or trough in the input waveform p. It is insensitive to minor perturbations because of the inclusion of hysteresis in the triggering characteristic. Clearly, the narrower the hysteresis band, the greater the sensitivity to change of direction of the input waveform and the more nearly in time do the output transitions approach the turning points of the input. Circuit operation is dependent upon changes in intantaneous values and, at least in principle, not upon time constants or differential rates; it should not therefore be unduly sensitive to variations in the rate at which peaks are presented to the detector.

The reconstituted rectangular wave may, in all three instances, be applied to a differentiating circuit 66 to give a train of sharp pulses of alternating polarity. In that case a means is required for separating the negative and positive pulses and converting them to negative pulses to be fed to the two inputs of the commutator. Such a separating means is shown in Fig. 5.

Referring to Fig. 5 the output of the single peak detector is applied to the inverting input terminal of a differential comparator, DC1 (e.g. Type 710), and to the non-inverting input terminal of another DC2. These comparators are appropriately biased at their other input terminals so that DC1 and 2 respond respectively to the positive and negative parts of the input waveform. The effect of the opposite input terminal polarities is that the pulsed outputs of DC1 and 2 both move in the same sense.

In the same way as was described above in the peak-sensing example, it is possible to dispense with the formation of pulses at transitions, and simply to apply the reconstituted rectangular wave directly to polarity and signal processing circuits 23 and 25 constructed from state-controlled logic elements.

Although the invention has been described by way of example in relation to a magnetic record in the form of a ticket, it is applicable to other forms of magnetic record such as a tape record.

The invention has been described in the foregoing, in relation to a ticket having two identical tracks and a single decoding system comprising a single reading head. This has been done for simplicity of presentation. In practice, the two tracks would not be identical but instead would carry independent messages. Two decoding systems with respective heads for reading the two tracks simultaneously would be provided.

Although a conventional inductive sensing head, 16, appears in Fig. 2, it is also possible to use a magnetostatic ('Flux-sensitive') head based upon, for example, the Hall or the magnetorestrictive effect. Such a device senses the local gradient of the external field, and its output therefore passes through zero each time a pole aligns with the head gap.

If, after amplification (61), the head output is hard limited (63), for intance as shown in Fig. 6(d), then a rectangular waveform results whose transitions correspond to the pole positions along the ticket, thus reproducing the original code waveform, 14, of Fig. 1.

Claims (10)

1. Apparatus for extracting binary data and clock information from a record in which the boundaries of binary bits representing that data and information are represented by first magnetic transitions and the binary values of the bits are represented by second magnetic transitions (opposite to the first), which have selected ones of two positions relative to the boundaries according to the values represented thereby, the apparatus comprising record reading means for producing electrical signals in response to the transitions as the record moves relative thereto, means responsive to these electrical signals to distinguish in them between events of first and second significances according to whether they represent bit boundaries or the values of the bits respectively, first means for producing for each bit a representation of the time interval between the successive events of the first significance, representing the boundaries of that bit, second means for producing for each bit a representation of the time interval between its event of the second significance and one of its events of the first significance, means for comparing the said representations for each bit and for indicating whether the said time interval between its event of the second significance and one of its events of the first significance is less than or greater than a predetermined proportion of the time interval between the said successive events of the first significance of that bit, which predetermined proportion is intermediate the proportions of that time interval at which the events of the second significance are selectively produced, and means for sampling the indication produced by the comparing means at the time of production of each event of the first significance, thereby to extract the data.

2. Apparatus according to claim 1, wherein the responsive means includes a pair of peak detectors for producing signals representing the events of the first and second significances respectively, each peak detector comprising a comparator, a store for storing the value of the output of the comparator, the comparator being arranged to compare the value of the signal with the value stored in the store, and means for reducing the value stored in the store at a rate proportional to that value.

3. Apparatus according to claim 1 or 2, wherein the responsive means includes a circuit having first and second inputs for receiving signals representing the events of the first and second significances respectively, a third input for receiving a signal indicative of the direction of movement of the record past the reading means, a first output, a second output, and circuit means responsive to the signal received at the third input for presenting signals representing the events of the first significance to the first output and signals representing the events of the second significance to the second output, irrespective of the said direction of movement.

4. Apparatus according to claim 1, 2, or 3, wherein: the first means comprises a first counter and first counter control means responsive to the successive reception of signals representing events of the first significance to cause the first counter to count clock pulses for the time interval between those signals; the second means comprises a second counter, and second counter control means respeonsive to the successive reception of signals of representing events of the first and second significance to cause the counter to count clock pulses for the time interval between those signals; and the comparing means comprises a magnitude comparator arranged to respond to a signal representing an event of the first significance to compare half the count in the first counter with the count in the second counter.

5. Apparatus according to Claim 1, wherein the responsive means includes a peak detector comprising a source and sink circuit for acting as a source in response to an input signal having a level greater than a predetermined first level and as a sink in response to an input of level less than a second level different to the first level, capacitive means, arranged to be charged when the circuit acts as a source and discharged when the circuit acts as a sink, and comparing means for comparing a signal, the peak of which is to be detected, with the voltage on the capacitive means to produce the said first input of the source and sink circuit when the signal is increasing and the said second input of the source and sink circuit when the signal is decreasing.

6. Apparatus for extracting binary data and clock information from a record substantially as hereinbefore described with reference to Fig. 1, 2 and 4 of the accompanying drawings.

7. Apparatus for extracting binary data and clock information from a record substantially as hereinbefore described with reference to Figs. 1, 2, 6aor b, 5 and 4 of the accompanying drawings.

8. Apparatus for extracting binary data and clock information from a record substantially as hereinbefore described with reference to Figs. 1, 2, 3A and B, and optionally C and 4 of the accompanying drawings.

9. Apparatus for extracting binary data and clock information from a record substantially as hereinbefore described with reference to Figs. 1, 2, 6c, 7, 8, 5 and 4d the accompanying drawings.

10. Apparatus for extracting binary data and clock information from a record substantially as hereinbefore described with reference to Figs. 1, 2, and 4 as modified by Fig. 6d, and to Fig. 5 of the accompanying drawings