GB2029140A - Speech processor with automatic gain control - Google Patents

Abstract

A speech processor, e.g. in a hearing aid, has an automatically varying gain control determined by the amplitude of the input averaged over successive short time intervals (optimally 27 ms). For averaged signals below a threshold level of about one-fifth of the peak the gain is decreased with increasing amplitude, and for averaged signals above that threshold the gain is increased with increasing amplitude. The processing circuit comprises a main amplifier 12 for the input signals and a parallel gain control path comprising an integrator 16 which integrates input signals over each time interval and a level switch 18 which switches inputs above and below the threshold to an antilog circuit 19 or to an amplifier 20 respectively. Circuit 19 provides an output exponentially related to the input and amplifier 20 has a linearly decreasing characteristic. The outputs from circuits 19 and 20 are combined and control the gain of amplifier 12. <IMAGE>

Description

SPECIFICATION Speech processors This invention relates to speech processors. It has application inter alia in hearing aids.

Currently available hearing aids have amplifiers which are either of a simple type amplifying the whole frequency spectrum of audio signals more or less equally or else are frequency selective and in addition to overall amplification preferentially amplify the higher frequency signals to which the hard of hearing are more insensitive.

The blanket amplification of all signals, while of some benefit is nevertheless of reduced effectiveness since in raising the entire level of the input to the ear it causes the ear to adjust to the new level as a norm and to fail to recognise signals which are small relative to the new level, which are just those signals which were difficult to hear without an aid. Similarly the preferential amplification of higher frequencies distorts those sounds which were difficult to hear and thus tends to make them harder to recognise.

It is an object of the invention to provide a speech processor which does not have the problems described above.

Accordingly the present invention comprises a speech processor in which the gain is continuous varied by a gain control signal which is determined by the amplitude of the input signal averaged over successive intervals short compared to the fundamental period of the input signal but long enough so that a change in amplitude of the envelope of the signal can be recognised in such interval, and in which for such an averaged input signal below a predetermined value the gain control signal decreases with increasing amplitude thereof and for levels of such averaged input signal above the said predetermined value the gain control signal increases with increasing amplitude thereof.

In carrying out the invention the intervals of time over which the averaging of the amplitude of the input signal is carried out to obtain the gain control signal is between 0.20 to 0.34 ms and is preferably around 0.27 ms.

The predetermined value referred to is conveniently about one-fifth of the peak value of the signal but may lie between one-third and one-eighth of the peak value. Below this predetermined value the decrease in gain with increase in amplitude is linear and above this value this increase in gain with increase in amplitude is exponential.

In order that the invention may be more fully understood, reference will now be made to the accompanying drawings in which: Figure 1 illustrates a typical speech waveform, Figure 2 is a desired amplification/input voltage characteristic for a speech processor embodying the invention, and Figure 3 is a block diagram of the processor.

Referring now to Fig. 1 there is shown therein a fragment of a typical speech signal waveform over a short duration of time. The peak value is indicated as having the level 1 and a line is drawn in the figure at about 1 /5th of the maximum amplitude so as to divide the figure into two parts A and B.

When the wave is in the region it has an amplitude greater than 1 /5th of its peak, while when in the region B the waveform has an amplitude less than 1 /5th of its peak. The time axis is divided into a sequence of time intervals of value q. The value of q is conveniently chosen so as to be equal to about 0.27 ms. The time q is referred to herein as being the "quip" time. The waveform is averaged over each quip time to obtain a single value control signal which is used to control the gain of the amplifier during the quip time in accordance with the characteristic of Fig. 2.

The curve of Fig. 2 is a curve of amplification against speech input voltage for the complete processor. It will be seen that for low levels of input the amplification is large and decreases with increase of input until the input reaches a value of about 1 /5th of its peak value. Thereafter the amplification increases with increase of input voltage. The decreasing portion is linear whereas the increasing portion is exponential. The actual slope of the amplification characteristic can be conveniently varied by a manual control but the overall pattern namely an initial decrease followed by a subsequent increase is maintained throughout. It may also be desirable when changing the slope to ensure that the value of the amplification at the 1/5 point is constant irrespective of changes in the setting and this value can suitably be unity.

A block circuit diagram of a processor embodying the invention is shown in Fig. 3. An input signal is applied at a terminal 10 and is fed into two parallel channels. One channel is the main amplifier channel and comprises an initial delay circuit 11 which delays the signal by the time interval q. The delay circuit 11 is followed by the main amplifier 1 2 which includes a multiplication section 1 3 in which the incoming signal is multiplied by a gain control signal obtained from the second channel which is a signal processing channel. The output from amplifier 1 2 is taken to an output potentiometer 1 4 providing overall manual control of the level of the output at output terminal 15.

The processing channel comprises an integrator 1 6 which integrates the input waveform in successive quip times to produce an output which is single valued over the period of each quip time. The magnitude of the output represents the average value of the signal in the immediately preceding quip time.

The quip time q over which integration takes place is determined by a clock pulse train supplied at input terminal 1 7. The clock pulse train has a square waveform and each half wave has a period equal to the quip time.

Integrator 1 6 is provided with two integrating circuits which function in alternate sequence over successive quip times. The output value of each integrating circuit is held for the succeeding quip time after integration. This arrangement enables integrator 1 6 to provide a continuous output.

The output from integrator 1 6 is fed to a modulus circuit 1 7 which provides an output equal to the absolute value of its input. Thus irrespective of the polarity of the input to circuit 1 7 its output will always be of the same polarity. The modulus circuit output is fed to a level switch 1 8 which detects whether the input signal is above or below the threshold value V at which the characteristic of the amplifier is changed. High signals, namely those above the threshold value V are fed to an antilog circuit 1 9 while low level signals below V are fed to a gain shaping amplifier 20. Antilog circuit 1 9 is designed to provide an output which is related exponentially to the input.Amplifier circuit 20 provides an output which decreases in linear relationship to the value of the input. The outputs from the two circuits 1 9 and 20 are combined in a summing circuit 21 and are fed from there to the multiplication section 1 3 of the main amplifier 1 2. The threshold value of voltage V may be set by determining a long term average of the peak values of the input signal and scaling down this average to say one-fifth.

The speech processor described above acts to amplify low level signals relative to the remaining parts of a signal and thus enables these parts of a speech signal to be more readily heard. in addition by increasing amplification of high level signals the apparent dynamic range of the speed signal is increased and this is a further aid to hearing.

While the above described circuit acts as an amplifier of the input signals, with the overall amplification level being controlled by the output potentiometer 14, it will be appreciated that the speech processor could equally well function by differential attentuation of the input signal, followed if required by a linear amplifier.

A speech processor embodying the invention has particular application in hearing aids but can also be used wherever clarity of speech is important. Examples of fields of use are in sound recording, intercom, paging and telephone systems and whenever speed recognition is inadequate.

Claims (6)

1. A speech processor in which the gain is continuously varied by a gain control signal which is determined by the amplitude of the input signal averaged over successive intervals short compared to the fundamental period of the input signal but long enough so that a change in amplitude of the envelope of the signal can be recognised in such interval, and in which for such an averaged input signal below a predetermined value the gain control signal decreases with increasing amplitude thereof and for levels of such averaged input signal above the said predetermined value the gain control signal increases with increasing amplitude thereof.

2. The speech processor as claimed in Claim 1 in which the intervals of time over which the averaging of the amplitude of the input signals is carried out to obtain the gain control signal is between 0.20 and 0.34 ms.

3. The speech processor as claimed in Claim 2 in which the said intervals of time are approximately 0.27 ms.

4. The speech processor as claimed in any one of the preceding claims in which the said predetermined value is between one-third and one-eighth of the peak value.

5. The speech processor as claimed in Claim 4 in which the said predetermined value is about one-fifth of the peak value.

6. A speech processor substantially as described herein with reference to the accompanying drawings.