GB2028517A - Testing digital circuits - Google Patents

Abstract

In order to avoid the need to design expensive test procedures a circuit under test 10 is tested against a perfect reference circuit 11 (which may be a computer model). Random digital inputs are applied to the two circuits from a pseudo random generator 12. Mis-matches between the outputs are detected by exclusive OR gates 13. The reference circuit is also constructed to provide inhibiting outputs when input bit patterns are such as to give rise to an indeterminate output. These inhibiting outputs inhibit the OR gate outputs at AND gates 14. Any OR gate output which is not inhibited leads to a fail signal at the output of an OR gate 15. <IMAGE>

Description

SPECIFICATION Testing digital circuits This invention relates to a method of testing digital circuits suitable for testing complex, multiterminal circuits such as are implemented today as integrated circuits. Testing such circuits can represent the major part of the cost thereof and it is becoming increasingly difficult to test satisfactorily circuits of extreme complexity. This is because the basis of testing lies in devising tests which will detect likely failure modes. Such testing has the following serious disadvantages: 1) Each new device to be tested calls for a lot of throught and study by a well trained engineer before any tests can be made. He must devise a list of tests, which will then have to be built or programmed into the test equipment. This process will take perhaps three months and cost money, all to be costed against the new device in question.

2) The test equipment designer will have to omit many classes of test in order to make the test equipment practical -not unreasonably large or expensive.

3) The test equipment designer may make mistakes, and omit tests that he thought he had included.

4) When the test equipment is in service, certain failure modes will occur very often which were not foreseen by the designer, and this will make it necessary to update the test equipment.

(In software, this is called "software maintenance".) 5) The testing is "closed", being limited initially to the failures thought of by the designer with the result that unexpected failure modes will generally go undetected.

It may be interpolated here that, if a failure mode can be foreseen as very likely, available effort should surely be devoted to reducing its likelihood rather than to detecting it when it occurs. In general, a well designed system should have a large number of failure modes of more or less equal (though very small) probability, not a small number of high probability failure modes.

The known testing method can only economically be designed to detect small numbers of failure modes. It is very expensive and very difficult to think up all the tests required to detect a large number of failure modes in very complex circuits.

6) The building, commissioning and maintenance of test equipment present major problems. In particular, there is insufficient consideration of the checking of test equipment in use, which can be erroneously passing faulty circuits.

The object of the present invention is to provide an entirely different method of testing which largely avoids the disadvantages mentioned above.

According to the present invention, there is provided a method of testing a multi-input digital circuit wherein random digital inputs are applied simultaneously to inputs of the circuit under tests and to the inputs of a reference model, outputs of the circuit under test and corresponding outputs of the reference model are compared and faults are detected when the comparisons show discrepencies.

As a practical matter the random digital inputs can be generated by a pseudo random generator which is a well known device in relation to the generation of cyclic redundancy check codes. A psuedo random generator is implemented as a shift register with feedback from selected stages via exclusive OR gates. Such a generator can be constructed to provide a non-repeating code chain of virtually any desired length and therefore a long enough test sequence to perform a satisfactory test can be developed.

The reference model may be a hardware circuit if such a circuit known to be perfect exists. A reference circuit can be custom built to specification or the reference model may be in software form, i.e. a computer model.

There are various extensions to the basic method which will be necessary or desirable, depending upon circumstances. Firstly, random inputs can lead to 'don't care' situations in which an output is indeterminate. The test circuit and reference model could then produce different results which would lead to a fault being signalled when there was no fault. These situations are dealt with by inhibiting the detection of faults when inputs assume don't care combinations.

Secondly, the digital testing may have superimposed thereon programmed or random variation of parameters such as supply voltage, temperature, and pulse duration to ensure that the test device is up to specification in these respects.

The don't care procedure may be used to prevent fault detection if a parameter goes out of range.

Thirdly, as testing proceeds, knowledge gained thereby may be employed to improve the efficiency of testing, eg. by introducing some determinacy into some inputs, minimizing the length of the test sequence, and so on.

The invention will be described in more detail, by way of example, with reference to the accompanying schematic drawings, in which: Fig 1 shows a test set-u p for practising the invention, and Figs 2 and 3 show two examples of arangements for dealing with don't care situations.

In Fig 1 a circuit under test 10 (test circuit for short) and an identical reference circuit 11 have inputs A, B, C etc. As already noted the reference circuit may actually be a computer model. A pseudo-random generator 12 is pulsed from a clock source 16 and generates random binary words applied identically to the two sets of inputs.

The circuits have outputs Z, Y, X etc which are distinguished by subscript T and Rforthe test and reference circuits. The reference circuit also has corresponding don't care outputs Z1, Y1, etc.

Each output Z etc has a corresponding exclusive OR gate 13 to which ZR and ZT etc are applied. So long as the R and T inputs to all gates match, the gates produce no "1" outputs; the test circuit is behaving as it should. If any gate produces a "1", this may result from a fault as from a don't care situation. In order to inhibit fault detection in the latter situation, the output of each exclusive OR gate 13 is applied to a corresponding AND gate 14 which receives the corresponding Zl, Y etc signal on an inventing input. The outputs of all AND gates 14 are fed to an OR gate 15. A "1" output from the gate 1 5 signals a fault, i.e. fails the test circuit.

Fig. 2 shows a very simple example of the generation of an inhibiting signal to take care of a don't care situation. Part of the circuit under test is a a bistable 17 having set and clear inputs S and C connected to the A and B circuit inputs. The Q output is taken to be output XT. If the set and clear inputs of a bistable are pulsed simultaneously, the output is unpredictable. Accordingly, the reference circuit includes not only a reference bistable 1 8 producing XR but an inhibit bistable 19 which produces Xl when it is set. The bistable 19 is set by an AND gate 20 when A=B=1. The bistable 19 is cleared by a gate 21 with the NAND function when at least one of A and B is O.

Fig 3 shows another example of the generation of an inhibit signal Wl for a circuit operating with clock pulses specified as having a minimum duration of 1 Ons. The test circuit 10 has a clock input D and other inputs typified by an input C. A typical output is output WT. The reference circuit 11 has corresponding inputs and outputs. An inhibit bistable 22 for generating Wl is set by a narrow pulse detector 23 when clock pulse duration is less than 1 Ons. The bistable 22 is cleared by a wide pulse detector 24 when clock pulse duration is more than 1 Ons. W may provide an overall inhibiting action or be used selectively to inhibit fault detection only on one or more sensitive outputs.

In principle, the reference circuit, including the provision for generating the inhibit signals, can be automatically designed and built, without human intervention, using the specification of the circuit to be tested. The reference circuit could for instance be wholly in software, a simple transform of the device specification. The algorithm for transforming the specification into a reference circuit will be written only once, and will suffice for any test equipment design in the future. In other words, the algorithm can be costed against many test machines. If the specification for the device contains insufficient information for the algorithm to create a reference circuit, the device sould be banned for being inadequately specified.

The method may be implemented in practice as follows. A new kind of device arrives at the test department. With it comes the performance specification for the device. The latter is fed into the computer, which then generates (perhaps in software) the reference circuit. Immediately, it is then possible to begin testing the devices.

However, the complete sequence of excitations for such a device with (say) fifteen input pins is very long, (ie a very long pseudo-random code sequence has to be used) so the testing is expensive. However, it can commence more or less immediately, within hours of arrival of the device and its specification.

If and when the volume of such devices increases, a streamline program becomes economically justified for such a device, to shorten the testing time per unit. This is a procedure whereby two reference circuits are tested against; each other, one circuit being perfect while the other has one fault built into it. It is preferable to introduce known faults one at a time, and find out how far the testing sequence has to run until all of them have been severally found. Both circuits reside only in software during this procedure.

The streamline procedure just described can curtail the test program. It may be possible to shorten it additionally from the front end, ie start the pseudo-random-sequence from a later point.

To do this, when a fault is discovered as the two reference circuits are tested against each other, the test sequence is back-tracked by n steps and then run forward again to see if the fault is discovered. Various values of n are tried and-the minimum value which will ensure detection of the fault is thus ascertained. It will thus be found which segments of the pseudo-random sequence are required to detect all faults. That part of the sequence encompassing all these segments is all that is required to carry out the test.

An alternative procedure to the stream lie procedure is to automatically keep a record of the stage in the test routine when devices were found to be fault. After a throughput of say 10,000 units, it may be decided to be politic to test only up to the last test pattern needed to find the faulty ones revealed in the first 10,000. The quality control department will then decide to overrule this decision should evidence from the field indicate that testing needs to be extended.

Another technique whereby test throughput times can be greatly reduced is for certain inputs to be treated as special. E.g. it might be decided that the CLOCK input should sequence continuously, regularly, and not follow a pseudo-random sequence like the other inputs. Similarly, it might be decided that the +5v input should alternate every half cycle between +5+ and +46 volts, or that it should have an out of sync sine wave of 1 volt amplitude superposed on it However all such improvements, or shortening in the test sequence, cost money, and it might well be cheaper merely to build more test machines. Note that devices can in principle be tested in parallel, ie a plurality of test circuits can be tested against one reference circuit. Test equipment of the kind described will be vastly cheaper to build than equipment based upon known testing techniques, so it may be -uneconomic to make much effort to improve its throughput time.

Claims (12)

1. A method of testing a multi-input digital circuit wherein random digital inputs are applie#d simultaneously to inputs of the circuit under test and to the inputs of a reference model, outputs of the circuit under test and corresponding outputs of the reference model are compared and faults are detected when the comparisons show discrepancies.

2. A method according to claim 1, where the reference model is a hardware reference circuit.

3. A method according to claim 1, where the reference model is a software model.

4. A method according to claim 1, 2 or 3, where the reference model responds to input bit patterns which lead to indeterminate outputs to inhibit fault detection when discrepancies in such outputs exist.

5. A method according to any of claims 1 to 4, where at least one parameter affecting circuit performance is varied in respect of the circuit under test during the test

6. A method according to any of claims 1 to 5, where at least one further input of the circuit under test and the corresponding reference model input(s) is or are fed with bit sequences which are predetermined in a non-random manner.

7. A method according to any of claims 1 to 6, where the random digital inputs are supplied by a pseudo-random generator.

8. A method according to claim 7, where the pseudo-random sequence is terminated at a point whereat most faults will be found.

9. A method according to claim 8, where the said point is determined on the basis of previous test records.

10. A method according to claim 8, where the said point is determined by testing the reference model against a reference model with a succession of known faults to ascertain the point by which all such faults wil have been detected.

11. A method according to claim 8, 9 or 10 where the pseudo-random sequence is shortened from the front by commencing at a start point from which up to the terminating point most faults will be found.

12. A method according to claim 1 1, insofar as dependent on claim 10, where the start point is determined during the testing of the reference model against the reference model with a succession of known faults by back-tracking from the detection of each fault to determine the length of the run up thereto to detect the fault.