GB2028037A - Analogue to digital converter - Google Patents

Abstract

This invention is an analogue to digital converter in which an analogue input is fed to the first of a series of stages, each of which compares the input level with a reference level and gives a 1 or 0 output constituting one digit in the digital conversion. Each stages has a transfer function in which its output sweeps twice through it range in response to its input sweeping through its range once, and the output from one stage is the input to the next.

Description

SPECIFICATION Analogue to digital converter This invention relates to an analogue to digital converter, and one object is to provide such a converterwhich uses solid state circuit components, which gives a fast response and which is not very expensive.

According to the present invention, an analogue to digital converter comprises a series of stages each having a signal input and a reference input and means giving a digital indication of the relative levels of the two inputs; the analogue input being applied to the first stage, each stage having a transfer function in which in response to the input sweeping through its range, the output sweeps more than once through its range, the reference input for each stage being at a level corresponding to an intermediate level in the output from the previous stage, and the input to each succeeding stage being the output from the preceding stage.

As only one settling time is required for all the stages, the total sampling time is only that one settling time together with the propagation delay in each stage multiplied by the number of stages. Atypical total sampling time for an eight-stage converter to achieve a Gray code output is about 44 nanoseconds so that the system is very fast.

A prior system has used a number of voltage comparators in parallel set at equal spacings over the voltage level, and such a system is expensive both in terms of operating power and cost, particularly if required to perform at high speeds.

The use in accordance with the present invention of the transfer function defined for each stage with the input to a succeeding stage being the output from the preceding stage, enables each stage to give one digit in the final digital output of decreasing significance with the advantages of solid stake circuitry over power consumption economical use of a single chip, and accuracy over a large temperature range.

Each stage conveniently comprises a linear rectifier giving the transfer function defined above, so that if for example the input varies over a range from -v to +v the output can be in the form of a straight sided 'V' with its peak at 0 volts and its ends respectively at-v and +v. Then the reference input can be at a level corresponding to v12 and in that way a digital output can indicate in which part of the input range a particular input signal lies.

The invention may be carried into practice in various ways, and two embodiments will now be described by way of example with reference to the accompanying drawings; in which FIGURE lisa block diagram showing the general principle of operation of the converter; FIGURE 2 is a series of diagrams showing the transfer functions for the different stages in the diagram of FIGURE 1; FIGURE 3 is a circuit diagram showing one stage of the converter of FIGURE 1 in one possible realisation; and FIGURE 4 is a circuit diagram corresponding to FIGURE 3 of another embodiment of a stage of the converter.

FIGURE 1 shows, largely in block diagram form, a circuit for converting an analogue signal to a 4-bit binary signal. The circuit includes an input buffer 10, which is formed by a linear amplifier, and which feeds a chain of three similar circuits 12, 14 and 16.

These three circuits all have essentially the same transfer function, which is illustrated in FIGURE 2A; as this figure shows, the output voltage declines linearly from its maximum value to its minimum value as the input value increases from its minimum value to the mid-point of its possible range, and then the output rises to its maximum value, again linearly as the input voltage rises from its mid-value defined by a reference value, to its maximum value.

If the reference values for the circuits 14 and 16 are set respectively at the mean values of the outputs from the circuits 12, and 14, the transfer function of the two circuits 12 and 14, taken together, will have the form shown in FIGURE 2B, and the transfer function of the three circuits 12, 14 and 16 taken together will have the form shown in FIGURE 2C.

The outputs of the input buffer 10 and the three circuits 12, 14 and 16 are each connected to a comparator 18,20,22 or 24, each of which provides a logic '0' output when the input to that comparator is in the lower half of its range, and a logic '1' output when the input is in the upper half of its range.

Thus, in operation, the output of the comparator 18 will indicate whether the input voltage lies in the upper or lower half of its range. Within each of these half-ranges, the output voltage of the circuit 12 will seep across its full range.

By monitoring this output voltage, the comparator 20 will indicate whether the input voltage to the circuit 10 lies in the upper or lower half of the relevant half-range, so that the outputs of the comparators 18 and 20, taken together, indicate in which of the four quarters of the input range the input voltage falls.

Within each of these quarter ranges, the output voltage of the circuit 14 will sweep across its full range.

The comparators 22 and 24 and the circuit 16 operate in a manner analogous to that just described, so that, if the input voltage range is considered as divided into sixteen equal sub-ranges, numbered from 1 to 16, the outputs from the four comparators 18,20 and 22 and 24 will adopt a state indicative of the subrange within which the input voltage falls, in accordance with the following table; Sub-Range Output of Comparator: 18 20 22 24 1 0 1 1 1 2 0 1 10 3 0100 4 0101 5 0001 6 0000 7 0010 Sub-Range Output of Comparator 8 0011 9 1011 10 1 0 1 0 11 1 0 0 0 12 1 0 0 1 13 1 1 0 1 14 1 1 0 0 15 1 1 1 0 16 1 1 1 1 It will be seen that this is a Gray code, and this may be directly suitable for some application.However, in most cases a normal binary code is more suitable, and FIGURE 1 includes three exclusive-NOR gates 26,28 and 30 which serve to convert the Gray code into the following binary code, which is available at terminals 32,3436 and 38: Sub-Range Output at Terminal 32 34 36 38 1 0000 2 0001 3 0010 4 0011 5 0100 6 0101 7 0110 8 0111 9 1000 10 1 0 0 1 11 1 0 1 0 12 1 0 1 1 Sub-Range Output at Terminal 13 1 1 0 0 14 1 1 0 1 15 1 1 1 0 16 1 1 1 1 FIGURE 3 shows one possible form of the circuits 10, 12 and 14; the circuit 10 is in effect formed by the input stage of the circuit 12, while the circuit 14 is similar to but complementary to the circuit 12.The circuit 16, and any further similar circuits which may be added to provide finer resolution (i.e. 32,64 or more sub-ranges) will be similar to eitherthe circuit 12 or the circuit 14, each circuit being complemen tary to those preceding and following it.

The input stage of the circuit 12 is formed by a differential amplifier comprising two Darlington pairs 32 and 34. The input voltage is applied to the input of the Darlington pair 32, while the input of the other Darlington pair is connected to a reference vol tage which can be adjusted to balance any offset in the input voltage range. In the present example, the mid-point of the input voltage range is at ground potential, and therefore the reference voltage is at or close to ground potential.

The emitter currents for the Darlington pairs 32 and 34 are supplied by a constant current source 36 which is not shown in detail. The source 36 is connected to the emitters of the Darlington pairs 32 and 34 through an adjustable potentiometer 38, and fixed emitter resistors 40 and 42; the potentiometer 38 allows the two sides of the differential amplifier to be matched.

The emitters of the two Darlington pairs 32 and 34 are connected to the comparator 18, to provide a differential-mode input signal to the comparator.

The collector loads of the Darlington pairs are formed by, firstly, two resistors 44 and 46, one for each collector load. In addition, a third resistor 48 is arranged to be effectively connected in parallel with whichever of the resistors 44 and 46 is carrying the heavier current. This is achieved by connecting the resistor 48 through diodes 50 and 52 to the collectors of the two Darlington pairs 32 and 34, so that the junction between the diodes 50 and 52 and the resistor 48 follows the voltage on whichever collector is the more negative.

In this way, the transfer function shown in FIGURE 2A is obtained, by taking the output of the circuit form this junction point. So that the voltage across the associated one of the resistors 44 and 46 is the same as the voltage across the resistor 48 diodes 54 and 56 are inserted in series with the resistors 44 and 46 to balance the forward voltage drops of the diodes 50 and 52.

Provided that the input voltage applied to the Darlington pair 32 differs from the ground potential by more than a certain margin, one of the diodes 50 and 52 is conductive, while the other is reverse biased. If, for example, the diode 50 is conductive the resistors 44 and 48 are effectively in parallel to form the collector load of the Darlington pair 32, while the resistor 46 alone forms the collector load of the other Darlington pair. Because the combination of the resistors 44 and 48 has a lower resistance than the resistor 46 alone, the reverse bias on the diode 52 will not be maintained if the input voltage falls below the margin mentioned above, since, below this margin even though the collector currents of the two Darlington pairs 32 and 34 have not become truly equal, the voltage drops across the resistors 44,46 and 48 have become equal. Under these conditions, therefore, both the diodes 50 and 52 are conductive and the current through the resistor 48 is shared between the two diodes. This means that, in fact, the transfer function of the circuit will not be exactly that shown in FIGURE 2A; instead, the sharp point at the mid-point of the input range will be somewhat rounded, However, by suitable selection of compo nent values, this rounding can be kept within limits.

As mentioned above, the circuit 14 is generally similar to, but complementary to, the circuit 12, and corresponding components will be designated by the same reference numerals, with the addition of a prime. The voltage at the junction of the resistor 48 with the diodes 50 and 52 is applied to the input of the Darlington pair 32', while the input of the Dar lington 34' is connected to a reference voltage, supplied by a source 58. The reference voltage is set to be equal to the mid-point of the range of the range of voltage which will be applied to the Darlington pair 32', or the average value of the function of FIGURE 2A.

The output to the comparator 20 is taken from the collectors of the DArlington pairs 32' and 34' rather than their emitters, since the collectors are closer to ground potential.

That output will be 0 or 1 depending on whether the input at 32 on the one hand, is between V12 and -V12 (where the total input range is-V 0 + V) or, on the other hand is between + V12 and + V, as described above.

As indicated above, the circuit of FIGURE 3 does not achieve exactly the transfer function of FIGURE 2A. FIGURE 4 shows a circuit which is improved in this respect. This circuit differs from the circuit of FIGURE 3 in that the Darlington pairs 32 and 34 are replaced by single transistors 132 and 134, the resis tor48 is replaced buy a constant current source 148 (not shown in detail), and in that two furthertransistors 60 and 62 are connected to divert from the collectors of the transistors 132 and 134, respectively, currents which are more or less equal to the current reaching the collectors through the diodes 50 and 52, respectively.This means that the currents through the collector resistors 44 and 46 are, in effect, controlled directly by the transistors 132 and 134, without interference from the diodes 50 and 52, and therefore the collector voltages follow linearly any change in input voltage. This is in contrast to the circuit of FIGURE 3, in which the collector voltages are similar in magnituve over that part of the input voltage range over which both the diodes 50 and 52 are conductive; the extent of that part of the input voltage range depends on the current through the resistor 48, which has to be transferred from one to the other of the Darlington pairs 32 and 34.

The zero reference on the base of the transistor 134 is set by a potentiometer 133.

The transistors 60 and 62 are controlled in the following manner. An emitterfollowertransistor64 or 66 is connected to follow the voltage at the collector of each of the transistors 132 and 134. The output voltages of the transistors 64 and 66 are shifted in a negative direction by two zener diodes 68 and 70 and two variable resistors 72 and 74 and the shifted voltages are then applied to the bases of the transistors 62 and 60 respectively. The transistors 60 and 62 are connected as a differential amplifier, whose common emitter current is supplied by a constant current source 76. The current set by the source 76 is equal to the current set by the source 148, so that the transistors 60 and 62 can divert the whole of the current through the diodes 50 and 52.

Over a small range of input voltages, both the diodes 50 and 52 will be conductive. As the input voltage passes through this range the transistors 60 and 62 will switch. For example, if the input voltage is rising, the transistor 60 will turn off, while the the transistor 62 turns on. The transfer of current from one transistor to the other within the switching range more or less matches the transfer of current from one diode to the other within this range. The net result is that the currents through the diodes 50 and 52 are substantially wholly carried by the trans istors 60 and 62 over the whole input voltage range.

Because the range of input voltages over which both diodes 50 and 52 are conductive is so small, the transfer function of the circuit will be substantially that shown in FIGURE 2A; there will be little round ing of the sharp point.

To bias the zener diodes 68 and 70, two constant current sources 78 and 80 are used. These are not connected directly to the bases of the transistors 60 and 62; instead, two transistors 82 and 84 feed the currents to the transistors 60 and 62. The transistors 82 and 84 have their emitters connected to the bases of the transistors 60 and 62, and have their own bases capacitively coupled to the emitters of the emitter followers 66 and 64. This arrangement serves to increase the switching speed of the transistors 60 and 62; a negative going edge at, for exam ple, the emitter of transistor 66 will turn the transistor 82 more fully on, helping the transistor 60 to turn off.

The circuit also includes a field effect transistor 86 which helps to increase the switching speed of the transistors 132 and 134. The transistor 86 is connected as a source follower, and its output is capacitively coupled to the emitter of the transistor 134.

Thus, in operation, a positive-going signal at the input will result in a positive pulse at the emitter of the transistor 134 helping this transistor to become less conductive as the transistor 132 becomes more conductive.

The circuit of FIGURE 4 also differs from that of FIGURE 3 in that the signals passed from one stage to the next are differential signals, so that subsequent stages do not need to incorporate reference voltage sources such as 58 (FIGURE 3). The use of differential circuitry helps to compensate for drift resulting from temperature changes. Also, instead of using circuits which are complementary to one another, circuits of only one polarity are used, and a level-shifting circuit is provided, to shiftthe signals produced by the circuit, as so far described, to a level suitable for application to the bases of the transistors 132 and 134 of the following circuit (not shown).

The differential signals supplied to the levelshifting circuit comprise, on the one hand, the voltage at the junction of the diodes 50 and 52 and the current source 148, and on the other hand as a reference voltage, the voltage at the mid-point of a chain of two equal resistors 88 and 90, connected between the collectors of the transistors 132 and 134. In the absence of thermal drift, this reference voltage is constant; thermal drift will affect it to the same extent as the voltage taken from the diodes 50 and 52.

The level-shifting circuit is generally similar to the circuit which drives the transistors 60 and 62; transistors 92, 94,96 and 98 correspond to transistors 64, 66,82 and 84; zener diodes 100 and 102 correspond to zener diodes 68 and 70; and adjustable resistors 104 and 106 correspond to the adjustable resistors 72 and 74. However, because the voltage at the junc tion of the resistors 88 and 90 is equal to the highest voltage reached at the junction of the diodes 50 and 52 (neglecting the voltage drop in the diodes), rather than the mid-point of the range of this voltage, the potentiometers 104 and 106 of the level-shifting circuits are adjusted to produce different shifts in the two signals, which can then be used respectively as the input and the reference in the next circuit.

Claims (13)

1. An analogue to digital converter comprising a series of stages each having a signal input and a reference input and means giving a digital indication of the relative levels of the two inputs, the analogue input being applied to the first stage; each stage having a transfer function in which in response to the input sweeping through its range, the output sweeps more than once through its range, the reference input for each stage being at a level corresponding to an intermediate level in the output from the previous stage, and the input to each succeeding stage being the output from the preceding stage.

2. A converter as claimed in Claim 1 in which the means gives a 1 or 0 output in dependence on which of the input levels is the greater.

3. A converter as claimed in Claim 1 or Claim 2 in which the said digital indication is one digit in the complete digital output.

4. A converter as claimed in any of the preceding claims in which the transfer function of each stage the output sweeps twice across its range as the input sweeps once across its range.

5. A converter as claimed in Claim 4 in which the reference input for each stage is the value of the signal input at which the output changes from its first sweep to its second sweep.

6. A converter as claimed in any of the preceding claims in which each stage includes a differential amplifier receiving the two inputs.

7. A converter as claimed in any of the preceding claims in which each stage includes a linear rectifier.

8. A converter as claimed in Claim 6 and Claim 7 in which the differential amplifier has a pair of transistors respectively coupled to opposite ends of a pair of rectifiers connected back-to-back.

9. A converter as claimed in Claim 8 in which the reference input is connected to the common point of the rectifiers.

10. A converter as claimed in any of Claims 6-9 in which the amplifier includes a pair of Darlington pairs of transistors.

11. A converter as claimed in any of the preceding claims including a Gray-code-to-binary-code converter for the digital outputs from the various stages.

12. A converter as claimed in Claim 11 including a number of exclusive NOR gates each of which receives the output from one stage (other than the first stage) and the output from the preceding stage.

13. An analogue-to-digital converter arranged substantially as herein specifically described with reference to the accompanying drawings.