GB2027562A - Digital control of a thyristor circuit - Google Patents

Abstract

The thyristor circuit comprises main, dropping, recharging and additional thyristors 25-28, and operates in two stages to apply chopped d.c. to load 31 e.g. a motor. In the first stage the digital control applies a regular train of pulses to thyristor 26, a second pulse train, progressively delayed with respect to the first, to thyristor 28 and a pulse train with fixed delay relative to the second to thyristor 27. In the second stage, a regular train of pulses is applied both to thyristors 25 and 27 and a progressively delayed pulse train is applied to thyristor 26. The trains of pulses are generated in the two stages by AND gates 14-17 and delay circuit 23 under control of clock 1, counter 2, decoder 3, bidirectional counter 4 and control unit 5, with switching from one stage to the other effected by decoder outputs 7, 8 through AND gates 18-20, NOT gate 21 and flip-flop 22. <IMAGE>

Description

SPECIFICATION Device for digital control of thyristor inverter The invention relates to apparatus used for the control of static converters utilizing gas-discharge, vacuum and semiconductor devices with gate electrodes, and more particularly to an apparatus for digital control of a thyristor inverter.

The invention is applicable for use in the traction and industrial electric drive d.c. systems and provides a means for regulating the speed of rotation of electrical machines and for regulating the voltage across active/inductive loads as well.

There is disclosed an apparatus for digital control of a thyristor inverter, comprising a decoder having its inputs coupled to the outputs of a clock counter, whose output is coupled to the output of a master oscillator, and to the outputs of a bidirectional counter having its add and subtact inputs coupled to add and subtract outputs of a control unit which has its individual output coupled to the rest inputs of the bidirectional counter and the master oscillator, the outputs of the decoder and an individual output of the clock counter being coupled to the gate electrodes of the thyristors of the inverter via a switching unit comprised, according to the invention, of seven AND gates, a NOT gate, a sign flip-flop, and a delay circuit, the individual output of the clock counter being coupled to the first inputs of the first and second AND gates, the output of the first AND gate being coupled to the gate electrodes of the main and recharging thyristors of the inverter, the output of the second AND gate being coupled to the gate electrode of the dropping thyristor of the inverter, which also connects the output of the third AND gate, the individual control pulse output of the decoder being coupled to the first inputs of the third and fourth AND gates, the output of the fourth AND gate being coupled to the gate electrode of the additional thyristor of the inverter and, via the delay circuit, to the gate electrode of the recharging thyristor of the inverter, the subtract output of the control unit being coupled to the first input of the fifth AND gate, the add output of the control unit being coupled to the first inputs of the sixth and seventh AND gates, the first regulation step switching pulse output of the decoder being coupled to the second input of the seventh AND gate and, via the NOT gate, to the second input of the sixth AND gate, the second input of the fifth AND gate being coupled to the second regulation step switching pulse output of the decoder, the outputs of the fifth and sixth AND gates being coupled to the first individual input of the sign flip-flop, the output of the seventh AND gate being coupled to the second individual input of the sign flip-flop, the first individual output of the sign flip-flop being coupled to the second inputs of the second and fourth AND gates, and the second individual output of the sign flip-flop being coupled to the second inputs of the first and third AND gates.

The apparatus of the invention provides for numerical control of a two-stage thyristor inverter, which requires the application of three and two trains of pulses for the first and second regulation steps respectively to the gate electrodes of the thyristors of the i nverter.

The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows a block diagram of an apparatus for numerical control of a thyristor inverter and a circuit diagram of the thristor inverter, according to the invention; Figures 2a, b, c, d, e, fshow timing diagrams of signals present at different points of the apparatus, for the first regulation step, according to the invention; Figures 3 a, b, c, d, e, fshow timing diagrams of signals present at different points of the apparatus, for the second regulation step, according to the invention.

The apparatus for numerical control of a thyristor inverter comprises according to the invention a master oscillator 1 (Figure 1) implemented as a multivibrator and having its output coupled to the input of a clock counter 2 designed for high-speed carry of 1's and having the number of its outputs equal to a double number of the flip-flops incorporated therein.

The apparatus also comprises a decoder 3 having one group of its inputs coupled to the outputs of the clock counter 2, a bidirectional counter 4 having its outputs coupled to the other group of the inputs of the decoder 3, and a control unit 5 incorporating pulse generators and feedback elements.

The decoder 3 made a conventional decoding matrix. The decoder 3 has an individual output 6 to provide trains of control pulses movable in time. These trains of control pulses are time-shifted relative to one another by a quarter of the pulse period. Also, the decoder 3 has a first individual regulation step switching pulse output 7 and a second individual regulation step switching pulse output 8.

The clock counter 2 has an individual control pulse output 9.

An individual output 10 of the control unit 5 is coupled to reset inputs of the master oscillator 1 and the bidirectional counter 4. An add output 11 of the control unit 5 is coupled to the add input of the bidirectional counter 4, whereas a subtract output 12 of the control unit 5 is coupled to the subtract input of the bidirectional counter 4.

There is also provided a switching unit 13 having seven AND gates 14, 15, 16, 17, 18, 19 and 20, a NOT gate 21, a sign flip-flop 22, and a delay circuit 23.

A controlled two-stage thyristor inverter 24 comprises a main thyristor 25, a dropping thyristor 26, a recharging thyristor 27 and an additional thyristor 28. The inverter 24 also comprises a switching circuit incorporating a serial arrangement of a switching capacitor 29 and a switching choke 30.

A load comprised of a serial arrangement of an armature 31 and a winding 32 shunted by a diode 33 is connected in the circuit of the main thyristor 25.

The individual control pulse output 9 of the clock counter 2 is coupled to the first inputs of the first and second AND gates 14, 15. The output of the first AND gate 14 is coupled to the gate electrodes of the main thyristor 25 and the recharging thyristor 27. The output of the second AND gate 15 and the output of the third AND gate 16 are coupled to the gate electrode of the dropping thyristor 26.

The individual output 6 of the decoder 3 is coupled to the first inputs of the third AND gate 16 and the fourth AND gate 17. The output of the fourth AND gate 17 is coupled to the gate electrode of the additional thyristor 28 and, via the delay circuit 23, to the gate electrode of the recharging thyristor 27.

The subtract output 12 of the control unit5 is coupled to the first input of the fifth AND gate 18, whereas the add input 11 of the control unit 5 is coupled to the first inputs of the sixth AND gate 19 and the seventh AND gate 20.

The first regulation step switching pulse output 7 of the decoder 3 is coupled to the second input of the seventh AND gate 20 and, via the NOT gate 21, to the second input of the sixth AND gate 19. The second regulation step switching pulse output 8 of the decoder 3 is coupled to the second input of the fifth AND gate 18.

The outputs of the fifth and sixth AND gates 18, 19 are coupled to the first individual input of the sign flip-flop 22, whereas the output of the seventh AND gate 20 is coupled to the second individual input of the sign flip-flop 22.

The first individual output of the sign flip-flop 22 is coupld to the second inputs of the second and fourth AND gates 15, 17, whereas the second individual output of the sign flip-flop 22 is coupled to the second inputs of the first and third AND gates 14, 16.

Figure 2 illustrates the timing diagrams of the signals present at different points of the apparatus circuitry during the first regulation step as follows: (a) voltage pulses 34 (Figure 2, voltage U26) applied to the gate electrode of the dropping thyristor 26 (Figure 1); (b) voltage pulses 35 (Figure 2, voltage U28) applied to the gate electrode of the additional thyristor 28 (Figure 1); (c) voltage pulses 36 (Figure 2, voltage U27) applied to the gate electrode of the recharging thyristor 27 (Figure 1); (d) voltage U29 (Figure 2) across the switching capacitor 29 (Figure 1); (e) voltage U (Figure 2) across the load; (f) currentithroughthe load.

Figure 3 illustrates the timing diagrams of the signals present at different points of the apparatus circuitry during the second regulation step as follows: (a) voltage pulses 37 (Figure 3, voltage U25) applied to the gate electrode of the main thyristor 25 (Figure 1); (b) voltage pulses 38 (Figure 3, voltage U28) applied to the gate electrode of the dropping thyristor 28 (Figure 1); (c) voltage pulses 37 (Figure 3, voltage U27) applied to the gate electrode of the recharging thyristor 27 (Figure 1); (d) voltage U29 (Figure 3) across the switching capacitor 29 (Figure 1); (e) voltage U (Figure 3) across the load; (f) current i across the load.

The apparatus of the invention operates in the following manner.

The individual input 10 (Figure 1) of the control unit5 provides a potential to block the master oscillator 1 and to cause the flip-flops of the bidirectional counter 4 to change to the 0 state.

When a first pulse from the add output 11 of the control unit 5 arrives at the add input of the bidirectional counter 4 the flip-flops of the latter assume the 1 state.

At the moment the application of the first pulse occurs a potential from the individual output 10 is obtained which makes the master oscillator 1 operative and the output of the latter provides clock pulses having the repetition frequency as follows.

f= fO .

where Fo is the switching frequency of the thyristors 25, 26,27, 28; n is the number of the flip-flops in the clock counter 2 and in the bidirectional counter 4.

Under these conditions, a train of pulses with the repetition frequencyfo is provided by the individual control pulse output 9 of the block counter 2.

During the first regulation step, it is necessary to control the thyristors 26, 27, 28 in which case the main thyristor 25 is made inoperative. A signal appears at the first regulation step switching pulse output 7 of the decoder 3 on completion of the first regulation step and is not present at the beginning of this step.

When no signal is present at the input of the NOT gate 21 the output of the latter produces a signal coming to one inputs of the sixth AND gate 19 and the other input of the sixth AND gate 19 accepts the pulses from the add output 11 of the control unit 5, which provides a condition in which a signal appears at the output of the sixth AND gate 19. The latter signal is applied to the first individual input of the sign flip-flop 22 and causes it to change to the state which enables the appearance of a signal at the first individual output of the sign flip-flop 22, which is then passed to the second inputs of the second and fourth AND gates 15, 17.

When a pulse coming from the individual control pulse output 9 of the clock counter 2 coincides with a signal applied to the second input of the second AND gate 1 5 the output of the latter produces the train of pulses 34 (Figure 2a) with the repetition frequency fO to be applied to the gate electrode of the dropping thyristor 26.

The individual output 6 (Figure 1) of the decoder 3 furnishes a train of control pulses which are shifted relative to the pulses available from the individual control pulse output 9 of the clock counter 2 by a time interval as follows

where T is the switching period of the thyristors 25, 26, 27, 28.

When a pulse obtainable from the individual output 6 of the decoder 3 arrives at the first input of the fourth AND gate 17 (the second input of the fourth AND gate 17 being provided with a signal from the first individual output of the sign flip-flop 22), the output of the fourth AND gate 17 produces pulses 35 (Figure 2b) applied to the gate electrode of the additional thyristor 28 (Figure 1).

At the same time, the pulses 35 are applied to the input of the delay circuit 23. Now, pulses 36 (Figure 2c) coming to the gate electrode 27 (Figure 1) appear at the output of the delay circuit 23 after a time interval which is the sum of the time necessary for the recovery of the blocking properties of the additional thyristor 28 and the time during which the switching capacitor 29 is recharged to acquire the reverse polarity.

The appearance of the next pulse available from the add output 11 of the control unit 5 at the add input of the bidirectional counter 4 results in an increase in the time interval t. As a result, the arrival of each next pulse at the add input of the bidirectional counter 4 causes an increase in the time interval between the pulse 34 (Figure 2a) applied to the gate electrode of the dropping thyristor 26 (Figure 1) and the pulse 35 (Figure 2b) applied to the gate electrode of the additional thyristor 28 (Figure 1).

The time interval between the pulses 35 and 36 (Figures 2b, c) applied, respectively, to the gate electrodes of the additional and recharging thyristors 28 (Figure 1) and 27 will be maintained constant during the entire first regulation step.

At the moment when the dropping thyristor 26 is driven to conduction, the voltage U (Figure 2e) across the switching capacitor 29 (Figure 1) and across the power supply is applied to the load through which the current i (Figure 2f) begins to pass in this case.

Under these conditions, the recharging of the switching capacitor 29 (Figure 1) occurs via the load circuit so that the switching capacitor 29 acquires the reverse polarity (Figure 2d).

The appearance of the pulse 35 (Figure 2b) at the gate electrode of the additional thyristor 28 (Figure 1) results in the shunting of the load circuit and the switching capacitor 29 is further recharged via the additional thyristor 28; in this case, the current i (Figure 2f) in the load continues to pass through the circuit of the diode 33 (Figure 1) due to the effect of the electromagnetic energy that has been stored within the period of the pulse provided by the voltage U (Figure 2e) applied to the load.

The appearance of the pulse 36 (Figure 2c) at the gate electrode of the recharging thyristor 27 (Figure 1) drives the latter to conduction and the switching capacitor 29 is recharged via the resonant circuit comprised of the switching capacitor 29 proper, the recharging thyristor 27 and the switching choke 30.

Increasing the time interval between the pulse 34 (Figure 2a) applied to the gate electrode of the dropping thyristor 26 (Figure 1) and the pulse 35 (Figure 2b) applied to the gate electrode of the additional thyristor 28 (Figure 1) results in an increase in the duration of the pulse provided by the voltage U (Figure 2e) applied to the load, which, in turn, causes the armature 31 (Figure 1) to rotate at a greater speed.

The maximum duration of the pulses obtainable from the voltage U (Figure 2e) applied to the load during the first regulation step is equal to the time within which the switching capacitor 29 (Figure 1) is recharged completely by the load current passing through the dropping thyristor 26.

After the first regulation step has been completed, the first individual regulation step switching pulse output 7 of the decoder 3 provides a signal causing the disappearance of the signal at the output of the NOT gate 21 and the appearance of a signal at the first input of the seventh AND gate 20.

When the next pulse from the add output 11 of the control unit 5 appears at the second input of the seventh AND gate 20, the output of the latter provides a signal applied to the second individual input of the sign flip-flop 22 which changes to the other state which causes the signal to appear at the second individual output of the sign flip-flop 22 and at the second inputs of the first and third AND gates 14, 16.

When the pulse from the individual control pulse output 9 of the clock pulse 2 and the signal applied to the second input of the first AND gate 14 are in coincidence, the train of pulses 37 (Figure 3a) with the repetition frequency f0, available from the output of the first AND gate 14, comes to the gate electrode of the main thyristor 25. At the same time, the pulses 37 (Figure 3c) are delivered to the gate electrode of the recharging thyristor27 (Figure 1).

The individual output 6 of the decoder 3 provides a train of control pulses which are shifted relative to the pulses obtainable from the individual control pulse output 9 of the clock counter 2 and are applied to the first input of the third AND gate 16. This train of the pulses 38 (Figure 3b) is then applied to the gate electrode of the dropping thyristor 26 (Figure 1).

Each pulse applied to the add input of the bidirectional counter 4 results in an increase in the time interval between the pulse 37 (Figures 3a, c) applied, respectively, to the gate electrodes of the main and recharging thyristors 25 (Figure 1), 27 and the pulse 38 (Figure 3b) applied to the gate electrode of the dropping thyristor 26 (Figure 1). To decrease this time interval, the pulses from the subtract output 12 of the control unit 5 are applied to the subtract input of the bidirectional counter 4.

The application of the pulse 37 (Figure 3a) to the gate electrode of the main thyristor 25 (Figure 1) drives the latter to conduction and the voltage U (Figure 1) drives the latter to conduction and the voltage U (Figure 3e) from the power supply is applied to the load. At the same time, the recharging thyristor 27 (Figure 1) is rendered conducting to provide a path through which the switching capacitor 29 is recharged to acquire the reverse polarity (Figure 3d).

The current i (Figure 3f) in the load tends to increase from the rated minimum value to the rated maximum value at which the pulse 38 (Figure 3b) is applied to the gate electrode of the dropping thyristor 26 (Figure 1).

With the dropping thyristor 26 driven to conduction, the voltage U29 (Figure 3d) across the switching capacitor 29 (Figure 1) is applied to the main thyristor 25, thereby driving it to cut-off.

The current i (Figure 3f) continues to pass in the load circuit via the diode 33 (Figure 1) during the space interval.

Increasing the time interval between the pulses 37 (Figures 3 a, c) applied, respectively, to the gate electrodes of the main and recharging thyristors 25 and 27 (Figure 1) and the pulse 38 (Figure 3b) applied to the gate electrode of the dropping thyristor 26 (Figure 1) causes an increase in the duration of the pulse provided by the voltage U (Figure 3e) applied to the load, which, in turn, provides for further increase in the speed of rotation of the armature 31 (Figure 1).

To decrease the speed of rotation of the armature 31, the above time interval is decreased.

After the second regulation step has been finished, the second regulation step switching pulse output 8 of the decoder 3 provides a signal applied to the first input of the AND gate 18 whose second input receives the pulses from the subtract output 12 of the control unit 5.

The next pulse from the subtract output 12 of the control unit 5 comes to the output of the fifth AND gate 18 and causes the sign flip-flop 22 to change to the other state the result that a signal appears at the first individual output of the sign flip-flop 22 and then passes to the second inputs of the second and fourth AND gates 15 and 17.

After that, the apparatus operates to perform the first regulation step in which the main thyristor 25 is made inoperative. In this case, the regulation process is similar to that described above with the exception that the time interval between the pulse 34 (Figure 2a) applied to the time interval between the pulse 34 (Figure 2a) applied to the gate electrode of the dropping thyristor 26 (Figure 1) and the pulse 35 (Figure 2b) applied to the gate electrode of the additional thyristor 28 (Figure 1) is decreased each time the next pulse arrives at the subtract input of the bidirectional counter 4.

The apparatus of the invention therefore makes it possible to control the two-stage thyristor inverter 24 in which three trains of pulses are applied to the gate electrodes of the thyristors 26,27,28 during the first regulation step and two trains of pulses are applied to the gate electrodes of the thyristors 25, 26 27 during the second regulation step.

Claims (5)

1. A digital control circuit for a thyristor inverter supplying pulses to a load from a d.c. source, comprising a decoder coupled to a clock counter and to a bidirectional counter, the clock counter having an input connected to a master oscillator and the bidirectional counter having add and subtract inputs coupled to respective outputs of a control unit, the control unit also having an output coupled to reset inputs of the bidirectional counter and master oscillator, and a sequence control circuit and a regulation step switching circuit, the regulation step switching circuit having respective inputs connected to the add and subtract outputs of the control unit and itself having two outputs, which are connected to the sequence control circuit and select first and second stages of operation of the thyristor inverter, and the sequence control circuit comprising respective inputs connected to the outputs of the clock counter and decoder and four outputs, the first for applying a regulartrain of pulses to a main thyristor of the inverter in the second stage, the second for applying to a dropping thyristor a train of pulses, progressively time-shifted relative to the pulses of the first train, in the second stage and a regular train of pulses in the first stage, the third for applying a progressively time-shifted train of pulses to a recharging thyristor in the first stage, and a train coincident with the regular train of the second stage, and the fourth for applying to an additional thyristor in the first stage a train of pulses progressively time-shifted relative to the regular train which is applied to the dropping thyristor in said first stage.

2. A control circuit as claimed in Claim 1, in which the decoder has first and second switching outputs connected to the regulator step switching circuit for automatically switching the regulator step switching circuit to select, respectively the second stage after the first stage and the first stage after the second stage.

3. A control circuit as claimed in Claim 2, in which the sequence control circuit comprises first, second, third and fourth AND gates, the output of the clock counter being connected to first inputs of the first and second AND gates, the outputs of which feed the first and second outputs of the sequence control circuit respectively, the output of the decoder being connected to first inputs of the third and fourth AND gates, the outputs of which feed the second and fourth outputs of the sequence control circuit, respectively, the output of the fourth AND gate also feeding through a delay circuit, the third output of the sequence control circuit and the output of the first AND gate also feeding the third output of the sequence control circuit, and second inputs of the first and third AND gates being connected to one output and the second inputs of the second and fourth AND gates being connected to the other output, of the regulator step switching circuit.

4. A control circuit as claimed in Claim 3, in which the regulator step switching circuit comprises fifth, sixth and seventh AND gates and a flip-flop, the flip-flop having opposite outputs feeding the two outputs of the regulator step switching circuit, the subtract and add outputs of the control unit being connected to respective first inputs of the fifth and sixth AND gates and said add output being connected to a first input of the seventh AND gate, the first and second switching outputs of the decoder being connected to the second inputs of the seventh and fifth AND gates, respectively, and the first said switching output of the decoder being connected through a NOT gate to the second input of the sixth AND gate, with the outputs of the fifth and sixth AND gates connected to one input of the flip-flip and the output of the seventh AND gate connected to the other input of the flip-flop.

5. A digital control circuit substantially as herein described with reference to the accompanying drawings.