GB2026801A - Improvements in or relating to static content addressable memory cells - Google Patents

Abstract

The invention relates to computer memories of the kind in which an item stored in a memory is accessed according to its information content rather than by a location address. Use is made of substrate fed logic (SFL) gates in constructing cells for a content addressable memory. Each cell comprises a bistable device 12 having two inputs connected each to the output of one of two input gates 8, 9, each of which itself has two inputs from control conductors DA, DB, WE; and the bistable device having, further, two outputs Q, Q, each connected to an input of one of two output gates 10, 11, which in turn are connected to the control conductors DA, DB and to output conductors WM, RA, RB. The control and output conductors permit information to be written into or read out from a cell. <IMAGE>

Description

SPECIFICATION Improvements in or relating to static content addressable memory cells This invention relates to static addressable memory cells for associative memories.

For many large scale file storage applications, for example, a high processing speed is necessary to maintain an acceptable transaction rate. High transaction rates may be maintained by processing in parallel. Moreover in such applications it is advantageous to store the file data such that the data may be accessed by content address rather than location address. A computer architecture embodying an associative memory containing content addressable memory cells can be suited to such applications.

Content addressable memory cells employing MOS transistors are known. An example of such a cell is disclosed in UK patent specification 1457423. In that specification both static and dynamic (that is a type of cell in which the cell contents need refreshing at regular intervals) cells are disclosed.

Dynamic cells have been designed in order that the area that each cell occupied on its integrated circuit substrate can be minimised.

This present invention attempts to provide a static content addressable memory cell that occupies a smaller substrate area than hitherto.

Cells in accordance with the present invention utilise substrate fed logic (SFL) gates for performing a positive logic NAND function, hereinafter referred to as SFL NAND gates. SFL NAND gates are described in IEEE Journal of Solid State Circuits SC~10 No 5 Oct 75 Pp 336-342. The use of such gates has enabled the design of a static content addressable memory cell of compact dimensions.

According to this invention there is provided a static content addressable memory cell comprising a flip-flop having two inputs and two outputs; two SFL NAND gates, hereinafter referred to as input gates, each having two inputs and an output; two SFL NAND gates, hereinafter referred to as output gates, each having three inputs and two outputs wherein the first flip-flop input is connected to the output of an input gate and the second flip-flop input is connected to the output of the other input gate; the first inputs of each input gate are coupled together by a first control conductor; the first flip-flop output is connected to the first input of an output gate and the second flip-flop output is connected to the first input of the other output gate; the second inputs of each output gate are coupled together by a second control conductor; the first outputs of each output gate are coupled together by a first output conductor; whereby when, in use, a signal level representative of a '1' bit is applied to the first control conductor the cell may be written to by applying a signal level representative of a bit to the second input of an input gate and a signal level representative of the converse bit at the second input of the other input gate; and when, in use, a signal level representative of a '1' bit is applied to the second control conductor the cell contents may be compared with the bit present at the third input of one output gate and the converse bit present at the third input of the other output gate whereupon if the bits present at the first and third inputs of an output gate are different the first output conductor will be held at a signal level representative of a '1' bit otherwise, if the bits present are the same, the first output conductor will be held at a signal level representative of a '0' bit; and when, in use, a signal level representative of a '1' bit is applied to the second control conductor the cell contents may be read out whereupon the bit present at the second output of an output gate is the same as the bit present at the first input of the other output gate.

In one configuration of cell there is provided a second output conductor connected to the second output of an output gate and a third output conductor connected to the second output of the other output gate. In said configuration there may be also provided a first input conductor connected to the third input of an output gate and to the second input of an input gate and a second input conductor connected to the third input of the other output gate and the second input of the other input gate whereby, in use, the cell contents can be read out by means of the second and third output conductors and the cell can be written to by means of the first and second input conductors.This invention extends to a memory array comprising a plurality of cells arranged in rows and columns such that each row shares common first and second control conductors and a first output conductor and such that each column shares common second and third output conductors and first and second input conductors.

In an alternative configuration of cell there is provided a first column conductor connected to the second output of the first output gate, the third input of the second output gate and the second input of the first input gate, and a second column conductor connected to the second output of the second output gate, the third input of the first output gate and the second input of the second input gate whereby, in use, the cell contents can be read out and the cell can be written to by means of the first and second column conductors. This invention extends to a memory array comprising a plurality of cells arranged in rows and columns such that each row shares common first and second control conductors and a first output conductor and such that each column shares common first and second column conductors.

It should be understood that the terms 'rows' and 'columns' refer only to the manner of interconnection of the cells and do not restrict embodiments of this invention to any particular spatial arrangement.

It should be understood that the terms 'rows' and 'columns' refer only to the manner of interconnection of the cells and do not restrict embodiments of this invention to any particular spatial arrangement.

The invention will now be further described by way of example only and with reference to the accompanying drawings of which: Figure 1 shows an associative memory, Figure 2 is a block diagram of a configuration of memory cell in accordance with this invention.

Figure 3 is a block diagram of an alternative configuration of memory cell, and Figures 4a to 4d show four configurations of a pair of SFL NAND gates which function as a flipflop.

Figure 1 shows an associative memory which includes an array 1 of memory cells, such as 2, arranged in rows and columns. The memory also comprises a data input register 3, bit select logic 4, a match register 5, a data output register 6 and word select logic 7. Each column of cells 2 is provided with two output conductors RA and RB which are connected to the data output register 6. Each cell can provide an output signal level representing a binary digit (bit) on its appropriate conductor RA and an output signal level representing the converse bit on its appropriate conductor RB. Each column of cells is also provided with two input conductors DA and DB which are connected to the bit select logic 4.

Conductors DA and DB conduct signal levels from the bit select logic 4 representative of a bit and the converse bit respectively. Each row of cells is provided with two control conductors, WE and MRE, connected to the word select logic 7 and each row is also provided with an output conductor WM connected to the match register 5. Therefore each cell has four inputs (that is those terminals connected to the conductors DA, DB, MRE and WE) and has three outputs (that is those terminals connected to conductors RA, RB and WM).

In use the memory stores binary words in each row of cells and the memory can be searched, read from and written into. Searching is performed by setting up the data input register 3 with the data to be searched whereupon the bit select logic 4 will, by means of conductors DA and DB, access the appropriate columns of cells inputting to the accessed cells via said conductors the bits determined by the data input register. At the same time the word select logic 7, by means of conductor MRE, accesses all rows of cells. Those cells receiving an input on conductor MR and conductors DA and DB will compare their stored bit with the bit present on DA and if the bits are mismatched they will attempt to pull down (the signal level on conductorWM is normally representative of a '1' bit) the signal level on conductor WM to a level representative of a '0' bit.The outputs connected to WM of each row of cells are wire-ANDed in that if only one of the accessed cells in that row attempts to pull down the level on .WM to '0' then the level will be held at a level representative of 'a'. Hence the row (or rows) of cells that provide an output on WM of '1' contain(s) the searched data. Match register 5 receives the outputs on WM and actuates means (not shown) for presenting the data, associated with the searched data, stored in the rows of cells containing the searched data.

Selected cells may be written into by accessing the columns of cells containing the selected cells by means of the bit select logic 4 and conductors DA and DB and accessing the selected cells in those columns by means of the word select logic 7 and conductor WE. The selected cells will receive the bits present on the appropriate DA and DB conductors.

Selected cells may be read from by accessing the columns of cells containing the selected cells by means of the bit select logic 4 and conductors DA and DB and accessing the selected cells in those columns by means of the word select logic 7 and conductor MRE.

Figure 2 shows a memory cell in accordance with this invention which embodies SFL NAND gates 8 to 1 1 and which is suitable for use in an associative memory (such as shown in Figure 1). The conductors carrying signals to and from the cell are labelled in a similar manner to the conductors shown in Figure 1 and have the same functions. The cell includes a flip-flop 12 which comprises two SFL NAND gates and possible configurations of these gates to give a flip-flop function are shown in Figures 4a to 4d and will be described below. The outputs of the flip-flop are labelled Q and The bit stored by the cell is represented by the signal level at the output 0. The output of gate 8 is connected to one of the two inputs of the flip-flop 12 and the output of gate 9 is connected to the other input Gates 8 and 9 will hereinafter be referred to as input gates.Each input gate has two inputs one of which is connected to the conductor WE. The remaining input of input gate 8 is connected to the conductor DA and the remaining input of input gate 9 is connected to the conductor DB. It will be remembered from the description of Figure 1 that when the signal level on DA represents a bit the signal level on DS normally represents the converse of that bit. However there are two exceptions, firstly when the cell is in a column which has not been selected by the bit select logic and secondly when the cell is being read from. In the first case the bit select logic holds the signal levels on DA and DB at a level representative of a '0' bit and in the second case the signal levels on DA and DB are held at a level representative of a '1' bit. Setting aside these exceptions it will be seen that providing the signal level on WE is representative of a '1' bit the converse of the bit present on the inputs DA and DB as appropriate to the input gates will appear at the outputs of the input gates and therefore at the inputs of the flip-flop. Therefore the bits present on DA and DB will be written into the cell.

An input of gate 10 is connected to the output Bof the flip-flop 12 and an input of gate 1 1 is connected to the input Q of the flip-flop 12. Gates 1 1 and 12 will hereinafter be referred to as output gates. Each output gate has two further inputs one of which is connected to the conductor MRE. The remaining input of output gate 10 is connected to conductor DA and the remaining input of output gate 11 is connected to the conductor DB. Each output gate has two outputs one of which is connected to conductor WM. The remaining output of gate 10 is connected to conductor RA and the remaining output of gate 11 is connected to conductor RB.The cell may be read from by holding as aforesaid the signals levels on DA and DB at a level representative of a '1' bit and by holding the signal level on MRE to a level representative of a '1' bit thereby causing the output connected to RA or RB as appropriate of the output gates to go to a signal level representative of the bit converse to that fed to it from the flipflop 12. Therefore the bit present on RA indicates the bit present at Q and the bit present on RB indicates the bit present at O. The cell may also perform a match function in that it will indicate by holding the signal level on conductor WM to a level representative of a '1' bit when the bit present on DA is the same as that present at Q. To perform this function it is necessary to hold the signal level of conductor MRE at a level representative of a '1' bit.It must be remembered (from the description of Figure 1) that the outputs of the output gates connected to conductor WM are wire-ANDed such that should there be a mismatch between the bit present on DA and that present at Q whereupon one of the output gates will attempt to hold the signal level of the conductor WM to a level representative of a '1' bit while the other output gate will attempt to hold the signal level of the conductor WM to a level representative of a '0' bit then the latter gate will dominate.

In use the signal level representative of a '0' bit will be about 300 mV or less and the signal level representative of a '1' bit will be about 650 mV or greater.

The following table is a function table for the cell shown in Figure 3.

Inputs Outputs Function MRE DA DB WE RA RB WM 0 oi o 1 I STANDBY O O O O 1 1 1 WRITE O 0 0 1 1 1 1 1 WRITE 1 0 1 0 1 1 1 1 WRITE O X X O 1 1 1 Unselected word row MASKED WRITE O 0 O 1 1 1 1 Unselected bit column READ O 1 1 1 0 0 1 0 READ 1 1 1 1 0 1 0 0 READ O 1 1 0 1 1 1 Unselected word row MASKED READ 1 0 0 0 1 1 1. Unselected bit column MATCH O Ç 1 0 1 0 1 0 O Mismatch result 1 0 O 1 0 1 1 1 Match result MATCH 1 I 1 1 0 0 0 1 O Mismatch result 1 1 1 0 O 0 1 1 1 Match result MATCH O X X O 1 1 1 Unselected word row MASKED MATCH 1 0 0 0 1 1 1 Unselected bit column

X = don't care Figure 3 shows an alternative memory cell in accordance with this invention. It will be noted that the number of conductors as compared with figure 2 has been reduced by two. As a consequence the left hand conductor running from top to bottom in the figure performs the functions previously carried out by conductors DA and RB, and the right hand conductor running from top to bottom in the figure performs the functions previously carried out by conductors DB and RA. The conductors have been labelled accordingly. It will be appreciated that this reduction in conductors will require some modification to the memory shown in figure 1. The cell embodies SFL NAND gates 13 to 16 and includes a flip-flop 12 (to be described with reference to figure 4).Gates 13 and 14 each have two inputs one of which is connected to the conductorWE. The remaining input of gate 13 is connected to the conductor DA!RB and the remaining input of gate 1 4 is connected to the conductor DB/RA. Gates 13 and 14 function as input gates in a similar manner to that described with reference to figure 2. When it is required to write into the cell the signal level on conductor MRE must be held at a level representative of a '0' bit and the data to be written in is put by means of the bit select logic onto conductors DA/RB and DB/RA.The signal level on conductor WE is at a level representative of a '1' bit when data is written into the cell consequently the converse of the bit present on the inputs DA/RB and DB/RA to the gates 13 and 14 respectively will appear at the corresponding gate outputs and therefore at the inputs of the flip-flop. Therefore the bits present on DA/RB and DB/RA will be written into the cell.

An input of gate 1 5 is connected to the output Q of the flip-flop and an input of gate 1 6 is connected to the output E. Each gate 1 5 and 1 6 has two further inputs one of which is connected to the conductor MRE. The remaining input of gate 16 is connected to the conductor DA/RB and to an output of gate 15. Each gate 1 5 and 16 has two outputs one connected as aforesaid and the remaining one connected to conductorWM. The cell may be read from by holding the signal level on conductor MRE at a level representative of a '1' bit. Assuming that the bit present at Q is '1 ' the outputs of gate 16 will go to a signal level representative of a '1' bit thereby causing a '1' bit to be present at the input of gate 15 and on the conductor DB/RA both of which are connected to an output of gate 16.Consequently '1' bits will be present on all inputs of gate 1 5 and its outputs will go to a signal level representative of a '0' bit.

Alternatively if the bit present at Q is '0' the outputs of gate 1 5 go to a signal level representative of a '1' bit and in a similar manner to that described cause a '0' bit to be present on conductor DB/RA and a '1' bit to be present on conductor DA/RB.

The cell may perform a match function providing that the data to be matched is present on the conductors DA/RB and DB/RA and that the signal level on conductor MRE is held at a level representative of a '1' bit. Assuming that there is a '1' bit present on conductor DA!RB this will also be present at the corresponding input to gate 1 6.If there is a mismatch the bit present at Q will also be a '1' and as the outputs of the gates 15 and 16 connected to conductor WM are wire-ANDed the signal level on conductor WM will be held at a level representative of a 'O' bit If there is a match the bit present at Q will be a '0' and the output of gate 1 6 connected to conductor WM will go to a signal level representative of a '1' bit but the other output of the gate (that is the output connected to conductor DB/RA) will be held by the bit select logic at a signal level representative of a '0' bit. Consequently the outputs of gate 15 will go to a signal level representative of a '1 ' bit Figures 4a to 4d show four configurations of two SFL NAND gates which are connected to function as a flip-flop.In figure 4a each gate 17 and 18 has two inputs and two outputs. An output of .each gate is connected to the input of the other gate. Assuming that a '0' bit is applied to gate 18 and '1' bit to gate 1 7 a '1' bit will appear at the outputs of gate 18 and consequently the inputs to gate 17 will each have a '1' bit present. The flip-flop may then be toggled by applying a '1' bit to gate 18 and a '0' bit to gate 17. The latter will cause '1' bits to appear at its outputs and consequently the inputs to gate 18 will each have a '1' bit present. In figure 4b each gate 19 and 20 has two inputs and one output. The output of each gate is connected to an input of the other gate. Assuming that a '0' bit is applied to gate 20 and a '1' bit to gate 19 a '1' bit will appear at the output of gate 20 and consequently the inputs to gate 19 will each have a '1' bit present.The flip-flop may then be toggled by applying a '1' bit to gate 20 and a '0' bit to gate 1 9. the latter will cause a '1' bit to appear at its output and consequently the inputs to gate 20 will each have a '1' bit present.

In Figure 4c each gate 21 and 22 has an input and two outputs. An output of each gate is connected to the input of the other. Assuming that a '0' bit is applied to gate 22 and a '1' bit is applied to gate 21 a '1' bit will appear at the outputs of gate 22 and a '0' bit will appear at the outputs of gate 21. The flip-flop may then be toggled by applying a '1' bit to gate 22 and a '0' bit to gate 21. However the '1' bit applied to the input of gate 22 will be overridden by the '0' bit already present until the flipflop has toggled. The '0' bit applied to gate 21 causes '1 bits to appear at its outputs and consequently permits the '1' bit to be applied to gate 22. In Figure 4d each gate 23 and 24 has one input and one output and the output of each gate is connected to the input of the other. Assuming that a '0' bit is applied to gate 24 and a '1' bit is applied to gate 23 a '1' bit will appear at the output of gate 24 and a '0' bit will appear at the output of gate 23. The flip-flop may then be toggled by applying a '1' bit to gate 24 and a '0' bit to gate 23. However, as for the flip-flop shown in figure 4e, the '1' bit applied to the input of gate 23 will be overridden by the '0' bit already present until the flip-flop has toggled. The '0' bit applied to the input of gate 23 causes a '1' bit to appear at its output and consequently at the input of gate 24.

The flip-flops shown in figures 4a to 4d will not toggle when '1' bits are applied to both of their inputs as when there is a '0' bit present on conductor WE.

Claims (8)

1. A static content addressable memory cell comprising a flip-flop having two inputs and two outputs; two SFL NAND input gates each ha#ving two inputs and an output; two SFL NAND output gates each having three inputs and two outputs; wherein the first input of the flip-flop is connected to the output of a said input gate and the second input of the flip-flop is connected to the output of the other said input gate; first inputs of each input gate are coupled together by a first control conductor; the first output of the flip-flop is connected to the first input of an output gate and the second output of the flip flop is connected to the first input of the other output gate; the second inputs of each output gate are coupled together by a second control conductor; first outputs of each output gate are coupled together by a first output conductor; whereby when, in use a signal level representative of a '1' bit is applied to the first control conductor the cell may be written to by applying a signal level representative of a bit to the second input of an input gate and a signal level representative of the converse bit at the second input of the other input gate; and when, in use, a signal level representative of a '1' bit is applied to the second control conductor the cell contents may be compared with the bit present at the third input of one output gate and the converse bit present at the third input of the other output gate whereupon if the bits present at the first and third inputs of an output gate are different the first output conductor will be held at a signal level representative of a '1' bit, otherwise, if the bits present are the same, the first output conductor will be held at a signal level representative of a '0' bit; and when, in use, a signal representative of a '1' bit is applied to the second control conductor the cell contents may be read out, where upon the bit present at the second output of an output gate is the same as the bit present at the first input of the other output gate.

2. A memory cell according to claim 1 having a second output conductor connected to the second output of an output gate and a third output conductor connected to the second output of the other output gate.

3. A memory cell according to claim 2 having a first input conductor connected to the third input of an output gate and to the second input of an input gate, and a second input conductor connected to the third input of the other output gate and the second input of the other input gate, whereby, in use, the cell contents can be read out by means of the second and third output conductors, and the cell can be written to by means of the first and second input conductors.

4. A memory array comprising a plurality of memory cells, according to any one of the preceding claims, arranged in rows and columns such that each row shares common first and second control conductors and a first output conductor, and such that each column shares common second and third output conductors and first and second input conductors.

5. A memory cell according to claim 1 having a first column conductor connected to the second output of the first output gate, the third input of the second output gate and the second input of the first input gate; and a second column conductor connected to the second output of the second output gate, the third input of the first output gate and the second input of the second input gate; whereby, in use, the cell contents can be read out and the cell be written to by means of the first and second column conductors.

6. A memory array comprising a plurality of memory cells, according to claim 5, arranged in rows and columns such that each row shares common first and second control conductors and a first output conductor; and such that each column shares common first and second column conductors.

7. An associative memory comprising static content addressable memory cells substantially as herein before described with reference to Fig. 1 of the accompanying drawings.

8. A static content addressable memory cell substantially as herein before described with reference to any one of Figs. 2, 3 a 4 of the accompanying drawings.