GB2025130A - N-channel non-volatile memory element - Google Patents

Abstract

An electrically alterable non-volatile memory for storing information incorporates one or an array of memory elements comprising a P- doped semiconductor substrate 20 in which there are mutually spaced N-regions 22, 24, with an insulating layer 30 overlaying a path between them and a conductive layer 36 on this insulating layer, the insulating layer-conductive layer combination being dimensioned so that in use an N-channel 40 can be formed from the first N-region 22 to a predetermined distance X from the second N-region 24, the presence of this channel being detected by applying a voltage VREAD to the second N-region 24 so that an N- channel region 48 extends therefrom a distance at least equal to X towards the first N-region 22. The thickness of the insulating layer changes at the predetermined distance X from the second N-region, and the conductive layer 36 may stop at this point. <IMAGE>

Description

SPECIFICATION N-channel non-volatile memory element This invention relates generally to semiconductor memories and more particularly to nonvolatile memories having variable threshold transistors.

In the prior art, non-volatile memories have been fabricated using P-channel variable threshold transistors. The P-channel variable threshold transistor has a large hysteresis window in the enhancement mode region and a small window in the depletion mode region.

To avoid memory sensing problems, the Pchannel variable threshold transistors are operated or written utilizing the available hysteresis window in the enhancement mode region such as from - 2 volts to - 10 volts. A desirable structure to insure that the variable threshold P-channel transistor operates in th enhancement mode region is described in U.S. Patent No. 3,836,894, issued on September 17, 1974 to James R. Cricchi, entitled MNOS/SOS Random Access Memory and assigned to the assignee herein. The patent of Crichi describes a drain source protected P-channel transistor wherein a thick insulation layer next to the source and drain diffusions keep the transistor exhibiting a threshold voltage of - 2 volts or thereabouts while a thin insulation layer between the source thick insulation regions and between the drain provides variable threshold characteristics.The memory transistor when read exhibits enchancement mode characteristics by reason of the thick insulation layer adjacent the drain and source diffusions. From a circuit standpoint, the transistor never goes into the depletion mode such as a VGS of + 1 volt but remains in the enhancement mode having a voltage such as - 2 volts for one memory state. In the other memory state the transistor may exhibit a threshold voltage of - 11 volts, for example.

For high speed non-volatile memories, Nchannel technology is desirable because Nchannel transistors are inherently faster than P-channel transistors. In N-channel transistors the majority carrier is electrons while in Pchannel transistors the majority carrier are holes having a lower mobility constant.

A non-volatile memory utilizing N-channel variable threshold transistors has a small volt; age window in the enchancement mode region such as from 4 volts to 1 volt as compared to the P-channel variable threshold transistor which has a large voltage window from - 2 volts to - 11 volts. However, while the voltage window in the depletion mode in a P-channel variable threshold transistor is from 2 volts to 0 volts, the voltage window in the depletion mode in an N-channel variable threshold transistor is from 1 volt to - 1 0 volts with a window of 11 volts.

It is therefore desirable to provide an Nchannel non-volatile memory which utilizes Nchannel transistors operating in the depletion region.

It is further desirable to provide a convenient way to read the memory state of a depletion mode N-channel variable threshold device.

It is desirable to provide an N-channel transistor structure which exhibits a variable threshold characteristic in the substrate extending from the source to a predetermined distance from the drain.

It is desirable to provide an N-channel variable threshold transistor memory which does not require the full value of its hysteresis window or variable threshold voltage swing for sensing the information stored in the transistor.

It is further desirable to provide an Nchannel variable threshold transistor memory which may have its information read without causing a read-disturb effect to individual transistors.

It is the principal object of this invention to provide a novel memory element which provides the advantages of P-channel operation in an N-channel device.

With the aforesaid object in view, the invention resides in an electrically alterable nonvolatile element comprising: a P-doped semiconductor substrate having N-doped regions spaced apart thereon, an insulation layer overlaying a path from between the regions, a conductive layer on said insulation layer overlaying a path from one of said regions to at least a given distance from the other region, said insulation layer having a thickness for varying a threshold characteristic such that the full hysteresis value is not utilized.

The invention will become more readily apparent from the following exemplary description in content with the accompanying drawings, in which: Figure 1 shows a hysteresis curve of a typical N-channel variable threshold transistor.

Figures 2A and 2B show the structures of an N-channel variable threshold transistor that may be utilized in Figs. 5 and 6.

Figure 3 shows a top view of transistor 18 in Fig. 2A.

Figure 4 shows transistor 18 of Fig. 2A with an N type depletion channel below the thin oxide.

Figure 5 shows one embodiment of the invention.

Figure 6shows a second embodiment of the invention.

Figure 7 shows circuit wave forms for typical operation of the embodiment of Fig. 5.

Figure 8 shows circuit wave forms for typical operation of the embodiment in Fig. 6.

Referring now to the drawings, Fig. 1 shows a hysteresis curve of a typical N-channel variable threshold transistor. In Fig. 1 the ordinate represents effective gate capacitance and the abscissa represents volts. The enchancement region is the area within curves 14, 12, 16 and 15. The window or variation in threshold voltage in the enhancement region is from a VH of + 4 volts to a VTHRESHDLD of 1 volt or a window of 3 volts. The depletion region is bounded by curves 10, 11, 12 and 1 3 having a low threshold voltage VL of - 10 volts an upper threshold voltage of + 1 volt or a voltage window of 11 volts.In the depletion region of operation for the transistor enough positive charge has been entrapped by the insulation layer to attract electrons in the substrate near the insulation layer which causes the upper substrate surface to have a greater number of electrons than holes causing an N-channel to form in the substrate.

Fig. 2A shows one structure of an N-channel variable threshold transistor that may be utilized in Figs. 4 and 5. Transistor 18 has a P-doped semiconductor substrate 20 whichmay be, for example, silicon doped with boron. Within semiconductor substrate 20 is a first N-doped region 22 and a second Ndoped region 24. The N-doped regions may be formed by diffusing phosphorus into the semiconductor substrate 20. N-doped region 22 may be coupled to line 26 and function as a source of transistor 18. N-doped region 24 may be coupled to line 28 and function as the drain of transistor 18. An insulation layer 30 is located over semiconductor substrate 20 overlaying a path from N-doped region 22 to N-doped region 24. Insulation layer 30 may be, for example, a first layer of silicon oxide 32 and a second layer of silicon nitride 34.A conductive layer 36 is located on top of insulation layer 30 overlaying a path from Ndoped region 22 to a least a predetermined distance from N-doped region 24. The predet ermine distance is indicated in Fig. 2 by the distance designated X from N-doped region 24 parallel to the surface of semiconductor substrate 20. Conductive layer 36 may extend over insulation layer 30 from N-doped region 22 to a point over N-doped region 24 as conductive layer 36' which is the usual practice to form the gate of a transistor as shown in Fig. 2B. Conductive layers 36 and 36' function as the gate of transistor 18 and is coupled to line 38.

The insulation layer 30 between semiconductor substrate 20 and conductive layer 36 is adjusted in thickness to exhibit a variable threshold characteristic in the semiconductor substrate 20 extending from N-doped region 22 to a predetermined distance from N-doped region 24. Insulation layer 30 may, for exam ple, include a silicon oxide layer 32 having a thickness of 20 Angstroms and a silicon nitride ayer 34 having a thickness t1 of several hundred Angstroms. As shown in Figs. 2A and 2B in the region where no variable threshold characteristic is desired thickness t2 of the silicon oxide layer 32 is, for example, 400 Angstroms while the thickness of the silicon nitride layer may be uniform throughout with a thickness t3 of several hundred Angstroms.The thin silicon dioxide layer 32 of thickness tl is capable of holding positive charge when a voltage potential is placed across the gate and N-doped region 22 charged from N-doped region 22 and substrate 20 will tunnel into silicon oxide 32 in the region where the oxide is thin as shown in Figs. 2A and 2B. The positive charge in the oxide layer 32 causes electrons to be attracted to the area below the positive charge in semiconductor substrate 20. When the number of electrons exceeds the number of holes in the P-doped semiconductor region, the region is inverted and has a characteristic of an N-type region or N-channel.

Fig. 2B shows an alternate structure of an N-channel variable threshold transistor that may be utilized in Figs. 4 and 5. In Fig. 2B, like references are used for functions corresponding to apparatus of Fig. 2A. In Fig. 2B, conductive layer 36' may cover the entire gate region between N-doped regions 22 and 24 of transistor 18'. By covering the thick oxide layer 32 of thickness t2 in the drain area 24, field enhancement of the drain junction is obtained improving the read mechanism, the formation of N channel region 48. It is noted that for purposes of illustration of view, Figs. 2A and 2B are not in precise proportion.

A A top view of transistor 18 which appears in Fig. 2A is shown in Fig. 3.

Fig. 4 shows transistor 18 of Fig. 2A with an N type depletion channel 40 below the region of thin silicon oxide layer 32.

Positive charge 42 shown in silicon oxide layer 32 had previously tunneled into the silicon oxide layer 32 from semiconductor substrate 20 by voltage between the gate and source of transistor 18, lines 38 and 26. As shown in Fig. 4, lines 38 and 26 are ground potential. Substrate 20 is coupled over line 44 to ground potential. The N-channel 40 extends from N-doped region 22 to a predetermined distance from N-doped region 24.

The predetermined distance is determined by the extent of the thin oxide layer 32 which stops at a distance of X from N-doped region 24.

As shown in Fig. 4, line 28 has a potential of + VREAD voltage. The positive voltage on Ndoped region 24 causes electrons to be attracted in semiconductor substrate 20 towards the N-doped region 24, causing the area immediately around region 24 and extending out to dotted line 46 to have an N-channel characteristic. Dotted line 46 delineates a depletion region between the N-channel region 48 and the P-type region of semiconductor substrate 20. Of course, the N-channel region 48 reverts back to a P-type region when the voltage on line 28 is reduced. The interaction of N-channel 40 and N-channel region 48 causes a conductive path to be formed between N-doped region 22 through channel 40 through region 48 to N-doped region 24.

The potential of the voltage VREAD on line 28 can be adjusted to cause the N-channel region 48 to extend past a predetermined distance from N-doped region 24. If the N-channel region 48 extends beyond the predetermined distance X then the N-channel region 48 will intersect with N-type channel 40 if N-channel 40 is present which depends upon the existence of positive charge 42 in oxide layer 32.

If N-channel 40 is non-existent, then there will be no path between N-doped region 22 to Ndoped region 24 and no current will pass through or only a negligible amount of current will pass. The presence of N-channel 40 determines one memory state of transistor 18 while the non-existence of N-channel 40 determines the other memory state of transistor 18. The information state in transistor 18 is read by placing a positive potential on Ndoped region 24 causing N-channel region 48 to extend a predetermined distance X from Ndoped region 24 to intersect with an Nchannel if N-channel 40 is present. Transistor 18 is therefore sensed by determining whether there is or is not conduction between N-doped regions 22 and 24 when a positive charge sufficient to cause an N-channel region 48 to extend a predetermined distance from N-doped region 24.

Fig. 5 shows an array 50 of electrically alterable non-volatile memory elements 52 through 60. In Fig. 5 the memory elements 52 through 60 are shown as N-channel transistors each having a gate, drain and source electrode. The body of each transistor 52 through 60 is coupled to the semiconductor substrate of memory array 50 and signal CLEAR on line 61. As shown in Fig. 5, memory elements 52 through 60 are arranged into three rows and three columns. The gate electrode of transistors 52, 55 and 58 of row 1 are coupled over line 62 to an output of gate row decoder 64. The gate electrode of transistors 53, 56 and 59 of row 2 are coupled over line 66 to an output of gate row decoder 64.

The gate electrode of transistors 54, 57 and 60 of row 3 are coupled over line 68 to an output of gate row decoder 64. Gate row decoder 64 has address signals Al and A2 coupled over lines 69 and 70, respectively, to its input. Signal write is coupled over line 65 to a control input of gate row decoder 64.

Gate row decoder 64 functions to decode the address signals on lines 69 and 70 to select one of the three rows in memory array 50 in response to signal WRITE on line 65. The drain electrode of transistors 52, 55 and 58 are coupled over line 71 to an output of drain row decoder 72. The drain electrode of transistors 53, 56 and 59 are coupled over line 73 to an output of drain row decoder 72. The drain electrode of transistors 54, 57 and 60 are coupled over line 74 to an output of drain row decoder 72. Address signals Al and A2 are coupled over lines 69 and 70 to an input of drain row decoder 72. Signal READ is coupled over line 75 to a control input of drain row decoder 72. Drain row decoder 72 functions to select one of the row lines 71, 73 or 74 in response to the address signals on lines 79 and 70 and signal READ on line 75.

The source electrode of transistors 52, 53 and 54 in column 1 are coupled over line 76 to one side of resistor 77, the source electrode of transistor 78. Line 76 functions as an output of memory array 50 during read operation as bit 1. The source electrode of transistors 55, 56 and 57 are coupled over line 79 to one side of resistor 80 and to the source electrode of transistor 81. Line 79 functions as an output during read operation of memory array 50 as bit 2. The source electrode of transistors 58, 59 and 60 are coupled over line 82 to one side of resistor 83 and to the source electrode of transistor 84. Line 82 functions as a data output line during read operation of memory array 50 as bit 3. The other side of resistors 77, 80 and 83 are coupled over line 85 as a return path to drain row decoder 72.The drain electrode of transistors 78, 81 and 84 are coupled over line 86 to a voltage potential E1. The gate electrode of transistor 78 is coupled over line 87 to write data 1 signal. The gate electrode of transistor 81 is coupled over line 88 to signal write data 2. The gate electrode of transistor 84 is coupled over line 89 to signal write data 3.

At least one of the non-volatile memory elements 52 through 60 of memory array 50 corresponds to the transistor structure shown in Figs. 2 and 3 insofar as an N-channel is formed in semiconductor substrate 20 from Ndoped region 24 in response to a thin oxide layer above forming part of insulation 30. The gate formed by conductive layer 36 may extend over only the thin portion causing the variable threshold characteristic or over the entire region between the two N-doped regions in a normal gate structure.

Fig. 6 shows a second embodiment of the invention. Memory array 90 comprises a plurality of electrically alterable non-volatile memory elememts where each memory cell comprises at least two memory elements for storing information. Normally, one memory element is written in one direction or memory state while the other is written in the other direction or memory state. The memory elements in memory array 90 are arranged in rows and columns. As shown in Fig. 6, the memory elements in memory array 90 are variable threshold transistors. At least one memory cell of memory array 90 is comprised of variable threshold transistors of the type shown in Figs. 2 and 3. Transistors 91 through 94 are in row one with transistors 91 and 92 forming a first memory cell and transistors 93 and 94 forming a second memory cell.Transistors 95 through 98 are in row 2 with transistors 95 and 96 forming a third memory cell and transistors 97 and 98 forming a fourth memory cell. Memory cells 1 and 3 are in the first column of memory array 90 and memory cells 2 and 4 are in the second column.

Transistors 91 through 98 each have a gate, source and drain electrode. The body of each transistor is coupled to the semiconductor substrate of memory array 90 and signal CLEAR on line 99. The gate electrode of transistors 91 through 94 are coupled over line 110 to an output of gate row decoder 11 2. The gate electrode of transistors 95 through 98 are coupled over line 116 to an output of gate row decoder 112. Signal Al representing the row address is coupled over line 120 to an input of gate row decoder 11 2.

Signal write is coupled over line 122 to an input of gate row decoder 112. Gate row decoder 11 2 functions to select either line 110 or 116 in response to the address on line 1 20.

The drain electrode of transistors 91 through 94 are coupled over line 124 to an output of drain row decoder 1 26. The drain electrode of transistors 95 through 98 are coupled over line 128 to an output of drain row decoder 1 26. Address signal Al is coupled over line 120 to an input of drain row decoder 1 26. Signal read is coupled over line 129 to an input of drain row decoder 126.

Drain row decoder 126 functions to select either line 124 or 128 in response to the address signal on line 120 during read operation to read the information from memory array 90.

The source electrode of transistors 91 and 95 is coupled over line 132 to an input of flip-flop 1 34r one side of resistor 168 and to the source electrode of transistor 1 36. The source electrode of transistors 92 and 96 are coupled over line 138 to an input of flip-flop 134, one side of resistor 169 and to the source electrode of transistor 140. The source electrode of transistors 93 and 97 are coupled over line 142 to an input of flip-flop 144, one side of resistor 170 and to the source electrode of transistor 146. The source electrode of transistors 94 and 98 are coupled over line 148 to an input of flip-flop 144, one side of resistor 171 and to the source electrode of transistor 150.Flip-flops 134 and 144 and one side of resistors 168 through 171 have a current return over line 152 to drain row decoder 1 26. Signal clock is coupled over line 167 to a control input on flip-flops 134 and 144. Flip-flop 134 has an output on line 154 and flip-flop 144 has an output on line 156.

Line 154 represents bit 1 of memory array 90 during readout and line 156 represents bit 2 of memory array 90.

The drain electrode of transistors 136, 140, 146 and 150 are coupled over line 158 to a voltage potential E1. The gate electrode of transistor 136 is coupled over line 160 to signal data 1. The gate electrode of transistor 140 is coupled over line 162 to signal data 1.

The gate electrode of transistor 146 is coupled over line 164 to signal data 2. The gate electrode of transistor 150 is coupled over line 166 to signal data 2. The signals on lines 160 and 162 function to provide the true and complement data to be written in memory array 90. The signals on lines 164 and 166 function to provide the true and complement data to be written into column 2 of memory array 90. Flip-flops 134 and 144 function to read columns 1 and 2 of memory array 90.

Fig. 7 shows circuit wave forms for the operation of the memory in Fig. 5. In Fig. 7 the ordinate represents voltage and the abscissa represents time. Referring now to Figs.

5 and 7 at TO, lines 61, 62, 66, 68, 76, 79, 82, 71, 73 and 74 are at ground potential.

At T1 signal CLEAR on line 61 goes from ground potential to a positive potential such as 25 volts which causes the body of the transistors in memory array 50 to be at + 25 volts while the gate electrodes are at 0 volts.

The + 25 volts across the insulation of transistors 52 through 60 causes positive charge to tunnel into the insulation layer 30 and in particular silicon oxide layer 32. Sufficient charge is stored in insulation layer 30 to cause the transistors to be in the depletion mode for a portion of the hysteresis window (see Fig. 1) causing an N-channel to form in substrate 20 underneath the positive charge.

It is understood that the substrate of memory array 50 is in an isolation tube isolated from the other circuitry in Fig. 5. At time T2 signal CLEAR on line 61 goes from + 25 volts to O volts bringing the semiconductor substrate of the transistors is memory array 50 to ground potential. It is understood that signal CLEAR on line 61 clears all the transistors in memory array 50 since CLEAR is coupled to the body of each transistor. Clearing all the transistors in a memory array to one threshold voltage is commonly called a block clear. It is understood that individual rows could be cleared to a particular threshold voltage by bringing CLEAR bar signal to only the body of transistors in a particular row. This may be accomplished by having individual diffusion regions for each row so that the semiconductor substrate of a particular row may be isolated from the other rows of transistors in memory array 50. Individual writing of rows would then require a CLEAR row decoder for selecting a particular. row when clearing is desired.

Now that all transistors in memory array 50 have been cleared to a particular threshold state causing a channel to form underneath each thin oxide region of each transistor, information may be written into each row by merely writing or altering the threshold volt age of the transistors desired to be in the other state. At time T3 lines 76 and 82 remain at ground. Line 79 is pulled from 0 volts to + 15 volts. Line 79 is pulled to 15 volts by the conduction of transistor 81 which is turned on by write data 2 on line 88.

Transistor 81 couples voltage supply E1 on line 86 to line 79. At time T4 the voltage on line 62 goes from 0 volts to + 25 volts causing a + 25 volts voltage across the insulation of transistors 52 and~58. Since line 79 is at + 15 volts the source and channel of transistor 55 are at + 15 volts. The insulation layer between the gate and body of transistor 15 therefore only has a potential of + 10 volts across it which is irisufficient to cause a change in threshold voltage of transistor 55.

Meanwhile, transistors, 52 and 58 are written to the other threshold state or into the enhancement mode due to the + 25 volts between the gate and body. Transistors 52 and 58 will therefore no lohger have an N-channel in the substrate underneath the thin oxide portion of the transistors. At time T5 the voltage on line 62 goes from + 25 volts to O volts. At time T6 the voltage on line 79 goes from + 15 volts to 0 volts. T6 marks the end of the write cycle for writing information into a particular row, row 1, of the transistors in memory array 50.

To read the information from row 1 in memory array 50 line 71 goes from 0 volts to + + 25 volts at time T7. The voltage on line 71 raises the drain electrode of transistors 52, 55 and 58 to + 25 volts causing a depletion region to form in the substrate around the drain of transistors 52, 55 and 58. Since no channel exists in transistors 52 and 58 since they have been written into the enhancement mode region, no current will flow through transistors 52 and 58 and bit 1 on line 76 and bit 3 on line 82 will remain at ground potential or the potential of line 85 which normally would be at ground.The depletion region around the drain of transistor 55 would extend a predetermined distance so as to intersect with the channel underneath the thin oxide region of transistor 55 which would cause transistor 55 tq conduct between the drain and source electrodes. The conduction would cause a current from line 71 through line 79 and resistor 80 to line 85 causing a voltage to appear across resistor 80 on line 79 at the output on bit 2. The voltage across resistor 80 may be 8 volts, for example. If the voltage on line 71 is held at + 25 volts, current will continually flow through transistor 55. If, however, the voltage on line 71 is allowed to discharge due to the flow of current through transistor 55, the voltage on line 71 will discharge until the pinch-off voltage region is reached in transistor 55 at which time no more current would flow through transistor 55.At time T8 the voltage on line 71 goes from + 25 volts to 0 volts and the voltage on line 79 goes from + 8 volts to O volts which complete the recycle of row 1 of the transistors in memory array 50. (Line 62 or row 1 of memory array 50 was selected by gate row decoder 64 in accordance with the address signals Al and A2 on lines 69 and 70.) (Line 71 was selected in response to the address signals Al and A2 on line 69 and line 70 by drain row decoder 72.) Fig. 8 shows circuit wave forms for the operation of the memory shown in Fig. 6. In Fig. 8 the ordinate represents voltage and the abscissa represents time. At time TO lines 99, 114, 110, 132, 138, 142,148 and 124 are at ground potential as shown in Fig. 8.At time T1 signal CLEAR on line 99 goes from 0 volts to 25 volts raising the potential of the body of transistors 91 through 98 to + 25 volts while the gate electrodes are held at O volts. The 25 volt polarization potential across the insulation layer 30 (see Fig. 2) causes the variable threshold transistors 91 through 98 to be in the depletion mode with an Nchannel forming in the substrate below the thin insulation layer where positive charge is stored. It is understood that the N-channel extends from the source electrode to a predetermined distance from the drain electrode.

The action of signal CLEAR might be termed a block clear since all the bodies of the transistors in each row are commonly connected. It is understood that the transistors in memory array 90 are isolated from the rest of the circuitry shown in Fig. 6. This may be accomplished by providing a separate isolation diffusion for memory array 90. Since all the transistors in memory array 90 have been cleared to the depletion mode data may be written into the memory array by writing the selected transistors to the enhancement mode condition. Since two transistors are used per memory cell in memory array 90, one transistor in each memory cell per row would be written to the enchancement mode. The other transistor would remain in the depletion mode.At time T3 lines 132 and 148 go from 0 volts to + 15 volts caused by the conduction of transistors 136 and 150 which couples voltage supply E, to lines 132 and 148. Transistors 136 and 150 are controlled by signals data 1 on line 160 and data 2 on line 166 respectively. The source electrode of transistors 91 and 94 are raised to + 15 volts and the N-channel of transistors 91 and 94 is likewise raised to + 15 volts. At time T4 the voltage on line 110 goes from 0 volts to + 25 volts. Since the source electrode of transistors 91 and 94 are at + 15 volts a polarization voltage of only 10 volts appears across the insulation layer of transistors 91 and 94.The source electrode of transistors 92 and 93 are at 0 volts causing a + 25 volt polarization voltage across the insulation layer of transistors 92 and 93 causing transistors 92 and 93 to be shifted to the enhancement mode with the N-channel being removed. At time T4 the voltage on line 110 goes from 25 volts to 0 volts. At time T5 the voltage on lines 132 and 148 go from + 15 volts to O volts. Row 1 of memory array 90 has now been written with information where the information is determined by comparing the status or polarization of the two transistors per memory cell.

To read the information in row 1 of memory array 90 line 124 goes from 0 volts to + 25 volts at T6. The drain electrode of transistors 91 through 94 is raised to the voltage of + 25 volts and a depletion region forms around the drain extending a predetermined distance from the drain into the body of transistors 91 through 24. The depletion region around the drain intersects with the Nchannel in transistors 91 and 94 causing transistors 91 and 94 to be conductive while transistors 92 and 93 are non-conductive since no N-channel exists. Lines 132 and 148 are pulled positive to, for example, + 8 volts at T6 due to the conduction of transistors 91 and 94. Lines 138 and 142 remain at ground potential due to the non-conduction of transistors 92 and 93. The data of memory cell 1 consisting of transistors 91 and 92 may be read out by comparing the polarity of the voltage on lines 132 and 138.The memory state of memory cell 2 consisting of transistors 93 and 94 may be read by comparing the polarity of the voltage on lines 142 and 148. As shown in Fig. 6, flip-flop 134 is coupled to lines 132 and 138 for sensing the polarity of the voltage upon a clock signal on line 167. Flip-flop 144 functions to sense the polarity of the voltage on lines 142 and 148 upon a clock signal on line 167. The output of flip-flops 134 and 148 is on lines 154 and 156 respectively and represents the readout of memory cell 1 or bit 1 and memory cell 2 or bit 2. At time T7 the voltage on line 124 goes from + 25 volts to 0 volts. The voltage on lines 132 and 148 go from + 8 volts to O volts.

The invention provides an electrically alterable non-volatile memory for storing information comprising an array of electrically alterable non-volatile memory elements, means for writing information into the array, means for reading information from the array, at least one of the non-volatile memory elements including a P-doped semiconductor substrate having first and second N-doped regions spaced apart, an insulation layer over the substrate overlaying a path from the first Ndoped region to the second N-doped region, a conductive layer on top of the insulation layer overlaying a path from the first N-doped region to at least a predetermined distance from the second N-doped region, the insulation layer between the substrate and the conductive layer having a thickness to exhibit a variable threshold characteristic upon application of a polarization voltage to cause at selected times a depletion mode channel to form in the substrate extending from the first N-doped region to a predetermined distance from the second N-doped region to enable conduction between the first and second Ndoped regions at times when the depletion mode channel in the substrate intersects with a depletion region extending from the second N-doped region caused by a predetermined potential of the second N-doped region.

The invention further provides an electrically alterable non-volatile memory element for storing information comprising a P-doped semiconductor substrate having first and second N-doped regions spaced apart, an insulation layer over the substrate overlaying a path from the first N-doped region to the second Ndoped region, a conductive layer on top of said insulation layer overlaying a path from the first N-doped region to at least a predetermined distance from the second N-doped region, the insulation layer between the substrate and the conductive layer having a thickness to exhibit a variable threshold characteristic upon application of a polarization voltage to cause at selected times a depletion mode channel to form in the substrate extending from the first N-doped region to a predetermined distance from the second N-doped region to enable conduction between the first and second N-doped regions at times when the depletion mode channel in the substrate intersects with a depletion region extending from said second N-doped region caused by a predetermined potential of said second Ndoped region.

Claims (6)

1. An electrically alterable non-volatile element comprising: a P-doped semiconductor substrate having N-doped regions spaced apart thereon, an insulation layer overlaying apath from between the regions, a conductive layer on said insulation layer overlaying a path from one of said regions to at least a given distance from the other region, said insulation layer having a thickness for varying a threshold characteristic such that the full hysteresis value is not utilized.

2. An element according to claim 1 wherein said insulation layer has a first thickness and a second thickness greater than said first thickness.

3. An element according to claim 2 wherein said first and second thickness meet at a given distance from one of the N-regions.

4. An element according to claim 1, 2 or 3 wherein said insulation layer comprises a layer of silicon oxide and a layer of silicon nitride.

5. An element according to claim 4 wherein said layer of nitride has a given thickness.

6. The elments according to any one of the preceding claims forming an array of electrically alterable non-volatile memory elements, means for writing information into said array, and means for reading information from said array.