GB202204510D0 - Multicore master/slave communications - Google Patents

Multicore master/slave communications

Info

Publication number
GB202204510D0
GB202204510D0 GBGB2204510.8A GB202204510A GB202204510D0 GB 202204510 D0 GB202204510 D0 GB 202204510D0 GB 202204510 A GB202204510 A GB 202204510A GB 202204510 D0 GB202204510 D0 GB 202204510D0
Authority
GB
United Kingdom
Prior art keywords
multicore
master
slave communications
slave
communications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GBGB2204510.8A
Other versions
GB2617114A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB2204510.8A priority Critical patent/GB2617114A/en
Publication of GB202204510D0 publication Critical patent/GB202204510D0/en
Priority to US18/127,579 priority patent/US20230410243A1/en
Priority to US18/127,554 priority patent/US20230377088A1/en
Priority to GB2304554.5A priority patent/GB2620226A/en
Priority to EP23164911.2A priority patent/EP4254308A1/en
Priority to CN202310318697.6A priority patent/CN116894755A/en
Priority to EP23164917.9A priority patent/EP4254311A1/en
Publication of GB2617114A publication Critical patent/GB2617114A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/522—Barrier synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/509—Offload
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00—Indexing scheme for image generation or computer graphics
    • G06T2210/52—Parallel processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Image Processing (AREA)
GB2204510.8A 2022-03-30 2022-03-30 Multicore master/slave communications Pending GB2617114A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
GB2204510.8A GB2617114A (en) 2022-03-30 2022-03-30 Multicore master/slave communications
US18/127,579 US20230410243A1 (en) 2022-03-30 2023-03-28 Multicore master/slave communications
US18/127,554 US20230377088A1 (en) 2022-03-30 2023-03-28 Multicore state caching in graphics processing
GB2304554.5A GB2620226A (en) 2022-03-30 2023-03-29 Multicore master/slave communications
EP23164911.2A EP4254308A1 (en) 2022-03-30 2023-03-29 Multicore state caching in graphics processing
CN202310318697.6A CN116894755A (en) 2022-03-30 2023-03-29 Multi-core state caching in graphics processing
EP23164917.9A EP4254311A1 (en) 2022-03-30 2023-03-29 Multicore master/slave communications

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2204510.8A GB2617114A (en) 2022-03-30 2022-03-30 Multicore master/slave communications

Publications (2)

Publication Number Publication Date
GB202204510D0 true GB202204510D0 (en) 2022-05-11
GB2617114A GB2617114A (en) 2023-10-04

Family

ID=81449555

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2204510.8A Pending GB2617114A (en) 2022-03-30 2022-03-30 Multicore master/slave communications

Country Status (2)

Country Link
CN (1) CN116894755A (en)
GB (1) GB2617114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117274027A (en) * 2023-08-22 2023-12-22 北京辉羲智能科技有限公司 Image processing chip with hardware safety redundancy

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8074224B1 (en) * 2005-12-19 2011-12-06 Nvidia Corporation Managing state information for a multi-threaded processor
GB2547252B (en) * 2016-02-12 2019-12-11 Advanced Risc Mach Ltd Graphics processing systems
EP3555760A1 (en) * 2016-12-19 2019-10-23 Centre National De La Recherche Scientifique Parallel processing on demand using partially dynamically reconfigurable fpga

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117274027A (en) * 2023-08-22 2023-12-22 北京辉羲智能科技有限公司 Image processing chip with hardware safety redundancy
CN117274027B (en) * 2023-08-22 2024-05-24 北京辉羲智能科技有限公司 Image processing chip with hardware safety redundancy

Also Published As

Publication number Publication date
CN116894755A (en) 2023-10-17
GB2617114A (en) 2023-10-04

Similar Documents

Publication Publication Date Title
GB202204510D0 (en) Multicore master/slave communications
GB202304554D0 (en) Multicore master/slave communications
GB202203837D0 (en) Communication system
GB202202786D0 (en) Communication system
GB202303395D0 (en) Communications system
GB202303371D0 (en) Communications system
GB202216172D0 (en) Communications system
GB202203232D0 (en) Communications system
GB202012333D0 (en) Communications system
GB202313284D0 (en) Transmission system
GB202202630D0 (en) Transmission system
GB202206043D0 (en) State Transmission System
GB202106911D0 (en) Waveguide
GB202108320D0 (en) Transmission system
GB202009731D0 (en) Waveguide
GB202210428D0 (en) Waveguide manufacture
GB202305383D0 (en) Connectors
GB202313681D0 (en) System for facilitating direct communications
GB202313011D0 (en) Transmission
GB202218593D0 (en) A communications system
GB202302224D0 (en) Communication system
GB202301235D0 (en) Communication system
GB202301029D0 (en) Communication system
GB202300921D0 (en) Communication system
GB202218671D0 (en) Communication System